A GaN-based enhancement-mode HEMT device with barrier layer recess etching and a preparation method thereof

Abstract

The application discloses a GaN-based enhancement-mode HEMT device with barrier layer groove etching and a preparation method thereof, and relates to the technical field of semiconductor device manufacturing. The GaN-based enhancement-mode HEMT device with barrier layer groove etching comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a first barrier layer, an etching blocking layer, a second barrier layer, an ion implantation region, a source and a drain, a gate dielectric layer, a gate, a passivation layer and a metal interconnection layer. By introducing the high-Al-component etching blocking layer and combining the multi-groove structure design, the gate leakage performance, the ohmic contact characteristic and the breakdown voltage capacity are significantly improved. The application can effectively solve the problems of interface state defects, gate leakage and insufficient breakdown voltage in the enhancement-mode GaN-based HEMT device with the barrier layer etching method, and has important practical application value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and more specifically, to a GaN-based enhancement-mode HEMT device with barrier layer groove etching and its fabrication method. Background Technology

[0002] GaN-based high electron mobility transistors (HEMTs) have shown great promise in 5G communications, power electronics, and high-frequency devices due to their high electron mobility, high voltage resistance, low loss, and excellent thermal stability. The two-dimensional electron gas (2DEG) density formed by their heterojunctions far exceeds that of traditional materials, and they possess high saturation velocity, making them suitable for high-frequency, high-power applications. Specifically, GaN-based HEMTs mainly have depletion-mode (normally on, D-mode) and enhancement-mode (normally off, E-mode) structures. While depletion-mode HEMTs are widely studied and applied due to their simpler design, the normally on switching mechanism poses circuit safety and loss problems. Therefore, research on normally off HEMTs is of practical significance. Currently, methods for realizing enhancement-mode GaN-based HEMTs mainly include grooved gate barrier layer etching, P-GaN layer insertion, and fluorine ion implantation. Among these, barrier layer etching weakens the polarization effect by etching the barrier layer in the region below the gate, thus achieving enhancement-mode devices. This method is relatively simple and feasible, but it suffers from reliability issues such as large gate leakage current, current collapse, and low gate breakdown voltage. These issues are related to lattice mismatch between the barrier layer and the gate dielectric, large interface state defects, and etching precision errors. Therefore, it is necessary to find methods to improve the interface state defects between the barrier layer and the gate dielectric and to control the etching precision, thereby enhancing the gate control performance of enhancement-mode HEMT devices. Summary of the Invention

[0003] The purpose of this invention is to provide a GaN-based enhancement-mode HEMT device with a barrier layer groove etching and its fabrication method, mainly to solve the performance degradation problem caused by shallow or over-etching of the barrier layer in HEMT devices, as well as the interface state defect problem caused by lattice mismatch between the barrier layer and the gate dielectric.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0005] A GaN-based enhancement-mode HEMT device with barrier layer groove etching includes a substrate and an epitaxial layer fabricated on one side of the substrate. The epitaxial layer includes a nucleation layer, a buffer layer, a channel layer, a first barrier layer, and an etch barrier layer stacked sequentially from bottom to top on the substrate, and a second barrier layer fabricated on the etch barrier layer after selective etching. An ion implantation region extending downward from the second barrier layer to the buffer layer is also fabricated on the epitaxial layer. Source and drain electrodes are disposed at the bottom of the groove in the second barrier layer. A gate dielectric is deposited on the epitaxial layer on the side away from the substrate. The gate is fabricated above the gate trench region of the gate dielectric layer, and a passivation layer is fabricated above the gate dielectric layer and the gate. An opening is formed by sequentially etching the passivation layer and the gate dielectric layer above the source drain and the gate. Metal is deposited in the opening to obtain a metal interconnect layer. The etching barrier layer in the gate trench region is etched into a multi-groove structure due to the uniformly arranged regular shape mask. The bottom of the trench is a first barrier layer, and the gate dielectric fills the trench structure. A two-dimensional electron gas layer is formed at the interface between the channel layer and the first barrier layer due to the polarization effect.

[0006] Furthermore, in this invention, the material of the first barrier layer is a group III-V compound Al. x Ga 1-x N, 0.1≤x≤0.2, thickness 3~5nm; the etching barrier layer material is a group III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness 5~10nm; the second barrier layer 107 is made of a III-V group compound Al. z Ga 1-z N, 0.2≤z≤0.3, thickness is 23~25nm.

[0007] The present invention also provides a method for preparing the above-mentioned device, comprising the following steps:

[0008] S1, Select a substrate, and prepare an epitaxial layer on one side of the substrate using metal-organic chemical vapor deposition (MOCVD) technology;

[0009] S2, Barrier layer grooves are prepared by selective etching on the epitaxial layer using photolithography mask technology;

[0010] S3. The gate dielectric, passivation layer and electrodes of the HEMT device are fabricated above the epitaxial layer etched in the barrier layer groove, thus completing the fabrication of the HEMT device.

[0011] Furthermore, in this invention, the specific process of step S1 is as follows:

[0012] S11, Provide a substrate and clean the substrate;

[0013] S12, using metal-organic chemical vapor deposition to sequentially grow a core layer, a buffer layer, a channel layer, a first barrier layer, and an etch barrier layer on a substrate;

[0014] S13, a mask is formed on the etch barrier layer of the source drain and gate recess regions using photolithography and development technology, and selective etching is performed using inductively coupled plasma etching equipment to remove the etch barrier layer outside the source drain and gate regions to form an epitaxial wafer.

[0015] S14, clean the epitaxial wafer, remove the photoresist, and wet the epitaxial wafer with dilute HCl and ultrapure water at a ratio of 1:10 to remove residual stains after etching. Then passivate the defects after etching by plasma cleaning.

[0016] S15, using metal-organic chemical vapor deposition, a second barrier layer is grown on the first barrier layer. After the second barrier layer covers the etch barrier layer, an epitaxial layer is grown. After the second barrier layer is grown, a two-dimensional electron gas layer is formed due to the polarization between the channel layer and the first and second barrier layers.

[0017] Furthermore, in this invention, the substrate is any one of a sapphire substrate, a Si substrate, a GaN substrate, and a SiC substrate.

[0018] Furthermore, in this invention, the specific process of step S2 is as follows:

[0019] S21, the active region of the HEMT device is defined by the photolithography and development technology of the epitaxial layer to form a device isolation mask, and the device isolation is completed by the ion implantation equipment.

[0020] S22, after cleaning the epitaxial layer of the device isolation, a mask is formed on the second barrier layer of the source drain and gate recess regions using a photolithography development technique, and a plasma etching device is used to selectively etch and remove the second barrier layer of the source drain and gate recess regions.

[0021] S23, clean the etched epitaxial layer, and use photoresist photolithography to form a mask for the etch barrier layer of the source / drain trench region and the gate trench region; use ICP to etch the etch barrier layer of the source / drain trench region and the etch barrier layer of the gate trench region; wherein, due to multiple uniformly distributed photoresist masks, the etch barrier layer of the gate trench region is etched into a structure with multiple trenches, and the bottom of the etch barrier layer of the multiple trenches is a first barrier layer;

[0022] S24. After etching, the epitaxial layer is cleaned to remove photoresist. Then, dilute HCl and ultrapure water are diluted at a ratio of 1:10 and used to wet the epitaxial layer to remove residual stains after etching. Finally, plasma cleaning is used to passivate the defects after etching, and the barrier layer groove etching is completed.

[0023] Furthermore, in this invention, the specific process of step S3 is as follows:

[0024] S31, after etching the epitaxial layer, it is cleaned, and a mask is formed in the groove area of ​​the source and drain electrode using a photolithography development technique. The source and drain electrode is metal vaporized using an electron beam evaporation device. After the metal is stripped off, the source and drain electrode is obtained by high-temperature rapid annealing and is in ohmic contact with the first barrier layer.

[0025] S32, a gate dielectric layer is deposited above the second barrier layer using a plasma-enhanced chemical vapor deposition (PECVD) device. The bottom of the gate dielectric layer in the groove region of the gate contacts the first barrier layer, and after filling the groove region of the etch barrier layer, the deposition continues to cover the groove structure.

[0026] S33, a mask is formed in the groove region of the gate using photolithography, and metal is deposited on the gate dielectric in the gate groove region using an electron beam evaporation device to prepare the gate.

[0027] S34, a passivation layer is prepared on top of the gate dielectric layer using plasma-enhanced chemical vapor deposition, and the opening mask of the source, drain and gate is formed using photoresist homogenization and photolithography.

[0028] S35, using plasma etching equipment to sequentially etch the passivation layer and the gate dielectric layer of the source and drain regions to form an opening;

[0029] S36. After the aperture etching is completed, dilute HCl and ultrapure water are diluted at a ratio of 1:10 and then used to wet the epitaxial wafer to remove residual stains after etching. Metal interconnect layer is prepared by evaporating metal in the aperture area using electron beam evaporation equipment to complete the fabrication of HEMT device.

[0030] Furthermore, in this invention, the nucleation layer is an AlN material with a thickness of 20-100 nm; the buffer layer is a high-resistivity GaN material doped with carbon or Al components with a thickness of 500-650 nm; and the channel layer is a lightly doped GaN material with a thickness of 150-200 nm.

[0031] Furthermore, in this invention, the groove etching shape of the etching barrier layer is a structure of multiple uniformly and regularly arranged vertical grooves, trapezoidal grooves, and inverted trapezoidal grooves.

[0032] Furthermore, in this invention, the electrode structure of the source and drain electrodes is a Ti / Al / Ni / Au metal stacked structure with a corresponding metal thickness of 20 / 130 / 50 / 100 nm; the electrode structure of the gate electrode is a Ni / Au metal stacked structure with a corresponding metal thickness of 50 / 100 nm; the electrode metal of the metal interconnect layer is the same as the metal stacked structure of the gate; and the gate dielectric is dense Si3N4 with a thickness of 35~50 nm.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) By inserting an etch barrier layer, the barrier layer is divided into a first barrier layer and a second barrier layer, which can better control the etching rate of the barrier layer. The high selective etching capability of the etch barrier layer prevents the bottom first barrier layer from being over-etched and causing interface defects, forming a natural ohmic groove that is conducive to ohmic contact, thereby greatly reducing the ohmic contact resistance and improving the device output current and high frequency response capability.

[0035] (2) By inserting an etch barrier layer, the present invention avoids the problem of insufficient gate turn-off capability caused by shallow etching of the barrier layer or the loss of the channel 2DEG caused by over-etching, which is beneficial to the precise etching requirements of the thin barrier layer in the gate region of the enhancement device. More importantly, the lattice matching degree between the etch barrier layer and the gate dielectric is lower. Through the design of the etch barrier layer groove, the gate dielectric can better form a lattice buffer with the first barrier layer during the filling process, reducing the interface defects caused by lattice mismatch and improving the gate control capability and leakage performance. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a GaN-based HEMT device provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the epitaxial layer fabrication process for a GaN-based HEMT device provided in an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the barrier layer groove etching process of a GaN-based HEMT device provided in an embodiment of the present invention;

[0039] Figure 4 This is a top view of the epitaxial layer of a GaN-based HEMT device after etching, as provided in an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of the electrode fabrication process for a GaN-based HEMT device provided in an embodiment of the present invention;

[0041] Figure 6This is a schematic diagram of another GaN-based HEMT device provided in Comparative Example 1 of the present invention;

[0042] Figure 7 This is a schematic diagram of another GaN-based HEMT device provided in Comparative Example 2 of the present invention;

[0043] The names corresponding to the reference numerals in the attached figures are as follows:

[0044] 100. HEMT device; 101. Substrate; 102. Nucleation layer; 103. Buffer layer; 104. Channel layer; 105. First barrier layer; 106. Etching barrier layer; 107. Second barrier layer; 108. Two-dimensional electron gas layer; 109. Ion implantation region; 110. Source and drain; 111. Gate dielectric layer; 112. Gate; 113. Passivation layer; 114. Metal interconnect layer. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0046] like Figure 1 As shown, this invention discloses a GaN-based enhancement-mode HEMT device with barrier layer groove etching and its fabrication method. A schematic diagram of the HEMT device structure is shown below. Figure 1 As shown, from bottom to top, the layers are: substrate 101, nucleation layer 102, buffer layer 103, channel layer 104, first barrier layer 105, etch stop layer 106, second barrier layer 107, ion implantation region 109, source / drain electrode 110, gate dielectric layer 111, gate electrode 112, passivation layer 113, and metal interconnect layer 114. A two-dimensional electron gas layer 108 is generated at the interface between channel layer 104 and first barrier layer 105 due to polarization effect. The first barrier layer 105 is made of a III-V group compound Al. x Ga 1-x N, 0.1≤x≤0.2, thickness 3~5nm; etch barrier layer 106 material is a III-V group compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness 5~10nm. The second barrier layer 107 is made of a III-V group compound Al. z Ga 1-z N, 0.2≤z≤0.3, thickness 23~25nm. Due to different Al compositions, Al... x Ga 1-x Materials with N, 0≤x≤1 have different etching rates under the same etching conditions. Generally, the higher the Al content, the slower the etching rate. Therefore, Al with a high Al content has different etching rates. y Ga 1-yThe material with N, 0.75≤y≤0.8, used as the etch stop layer 106, acts as an etch stop layer, protecting the underlying first barrier layer 105 from over-etching and resulting grain boundary defects. It also facilitates precise control of the groove etching process. The etch stop layer 106 in the gate region has a uniformly arranged periodic groove structure, with the first barrier layer 105 exposed at the bottom of the groove. The gate dielectric layer 111 is filled in the groove, and the thickness of the gate dielectric layer 111 is greater than the thickness of the etch stop layer 106. The gate dielectric layer 111 covers the etch stop layer 106 to form the gate structure groove.

[0047] like Figure 2 The diagram shows a schematic of the epitaxial layer fabrication process for a GaN-based HEMT device 100 with barrier layer groove etching. The barrier layer is divided into a first barrier layer 105 and a second barrier layer 107 by inserting an etch stop layer 106. The method includes the following steps:

[0048] A substrate is provided, which can be any one of sapphire Al2O3 substrate, Si substrate, GaN substrate, and SiC substrate. In this embodiment, Si is selected as the substrate;

[0049] After cleaning the Si substrate, a nucleation layer 102, a buffer layer 103, a channel layer 104, a first barrier layer 105, and an etch barrier layer 106 are sequentially grown on substrate 101 using MOCVD (metal-organic chemical vapor deposition). The nucleation layer 102 is made of AlN material with a thickness of 20–100 nm; the buffer layer 103 is made of carbon-doped or Al-doped high-resistivity GaN material with a thickness of 500–650 nm; the channel layer 104 is made of lightly doped GaN material with a thickness of 150–200 nm; and the first barrier layer 105 is made of group III-V compound Al. x Ga 1-x N, 0.1≤x≤0.2, thickness 3~5nm; etch barrier layer 106 material is a III-V group compound Al y Ga 1-y N, 0.75≤y≤0.8, thickness 5~10nm; a mask is formed on the etching barrier layer 106 in the source drain and gate recess regions using photolithography and development technology; selective etching is performed using inductively coupled plasma etching equipment (ICP) to remove the etching barrier layer 106 outside the source drain and gate recess regions; after etching, the epitaxial wafer is cleaned to remove the photoresist, and the epitaxial wafer is wetted with a solution of 15% dilute HCl and ultrapure water diluted at a ratio of 1:10 to remove residual stains after etching, and then the defects after etching are passivated by plasma cleaning.

[0050] After cleaning and etching the epitaxial wafer, a second barrier layer 107 is grown on the substrate using MOCVD. The second barrier layer 107 is then covered by an etch stop layer 106, and the epitaxial layer continues to grow. The second barrier layer 107 is a III-V group compound Al. zGa 1-z N, 0.2≤z≤0.3, thickness is 23~25nm; after the second barrier layer 107 is grown, a two-dimensional electron gas layer 108 is formed due to the polarization between the channel layer 104, the first barrier layer 105 and the second barrier layer 107.

[0051] like Figure 3 The diagram shows the epitaxial layer trench etching process of the GaN-based HEMT device 100, where the barrier layer trench is etched. Precise etching of the source / drain trench regions and the gate trench regions is achieved by selectively etching the barrier layer 106. This fabrication step includes:

[0052] The epitaxial layer 107, after being grown, is used to define the active region of the device by photolithography and development technology to form a device isolation mask, and the device isolation is completed by ion implantation equipment (IMP).

[0053] After cleaning the epitaxial layer isolated by the device, a mask is formed on the second barrier layer 107 of the source-drain and gate trench regions using photoresist photolithography. Selective etching is then performed using ICP to remove the second barrier layer 107 of the source-drain and gate trench regions. After etching, the epitaxial layer is cleaned to remove the photoresist. Then, a mixture of 15% dilute HCl and ultrapure water at a ratio of 1:10 is used to wet the epitaxial layer to remove residual stains after etching. Finally, plasma cleaning is used to passivate the defects after etching.

[0054] After cleaning and etching the epitaxial layer, a photoresist photolithography technique is used to form a mask for the etch barrier layer 106 in the source / drain and gate trench regions. ICP is used for selective etching to remove the etch barrier layer 106 in the source / drain and gate trench regions. The etch barrier layer 106 in the source / drain trench is completely etched. The etch barrier layer 106 in the gate trench region forms an etch barrier layer 106 with multiple trenches due to the uniformly distributed photoresist mask. The bottom of the etch barrier layer 106 with multiple trenches is the first barrier layer 105. After etching, the epitaxial layer is cleaned to remove the photoresist. The epitaxial layer is then wetted with a mixture of 15% dilute HCl and ultrapure water at a ratio of 1:10 to remove residual stains after etching. Finally, plasma cleaning is used to passivate the defects after etching, completing the etching of the barrier layer trench.

[0055] like Figure 4The diagram shown is a top view of the epitaxial layer of the GaN-based HEMT device 100 provided in this embodiment of the invention after etching. The etch barrier layer 106 in the gate recess region is etched into a plurality of uniformly arranged recess structures through a mask, and the bottom of the recess of the etch barrier layer 106 is a first barrier layer 105. That is, the gate recess region is a region in which the etch barrier layer 106 at the top of the recess and the first barrier layer 105 at the bottom of the recess are arranged in a uniform manner. The recess shape of the etch barrier layer 106 can include not only elongated distribution, but also circular pillars, square pillars and other structures. The etching of the recess of the etch barrier layer 106 includes not only vertical etching methods, but also trapezoidal etching, inverted trapezoidal etching and other methods.

[0056] like Figure 5 The diagram shows the electrode fabrication process of the GaN-based HEMT device 100 in an embodiment of the present invention. The fabrication steps include:

[0057] After etching the epitaxial layer, the area is cleaned, and a mask is formed in the source and drain trench region using photolithography. The source and drain metals are deposited using an electron beam evaporation (E-beam) system. The electrode structure is a Ti / Al / Ni / Au metal stack structure. The electrode thickness can be 20 / 130 / 50 / 100 nm. After metal stripping, the source and drain are rapidly annealed at 875℃ for 30 s to achieve ohmic contact, resulting in source and drain 110. Due to the presence of natural trenches in source and drain 110, the ohmic contact resistance is greatly reduced, thereby increasing the device drive current.

[0058] A dense Si3N4 gate dielectric layer 111 with a thickness of 35-50 nm is deposited on top of the device using PECVD (plasma-enhanced chemical vapor deposition). The bottom of the gate dielectric layer 111 in the gate recess region is in contact with the first barrier layer 105. After filling the recess region with the etch stop layer 106, the recess structure is further deposited to cover it. Subsequently, a mask is formed in the gate recess region using spin coating, photolithography, and development. Metal is deposited in the gate recess region using E-beam to prepare the gate 112. The gate metal is a Ni / Au metal stack structure, and the electrode thickness can be 50 / 100 nm. The contact between the gate 112 and the dense Si3N4 gate dielectric layer 111 in the gate recess is a Schottky contact, thereby realizing the gate 112 to control the turn-off of the GaN-based HEMT device 100.

[0059] A 350-500 nm thick Si3N4 layer was deposited on top of the device using PECVD to prepare a passivation layer 113. A photoresist homogenization, photolithography, and development technique was used to form an aperture mask for the source / drain 110 and the gate 112. In the aperture region, ICP etching was used to sequentially etch the passivation layer 113 and the gate dielectric layer 111 in the source / drain region to form vias. After the aperture etching was completed, a mixture of 15% dilute HCl and ultrapure water at a 1:10 ratio was used to wet the epitaxial layer to remove residual stains. E-beam was then used to vapor-deposit metal in the via region to prepare a metal interconnect layer 114, completing the fabrication of the GaN-based HEMT device 100. The metal interconnect layer 114 has the same metal stacking structure as the gate 112.

[0060] Due to the high Al content of Al y Ga 1-y An N (0.75≤y≤0.8) etch barrier layer 106 is inserted between the first barrier layer 105 and the second barrier layer 107. Through selective etching of different Al compositions, over-etching of the first barrier layer 105 is avoided, improving the ohmic contact performance of the source and drain. In addition, the etch barrier layer 106 in the gate region is uniformly etched into a groove structure. Filling the groove of the etch barrier layer 106 with the gate dielectric layer 111 not only increases the contact area between the gate dielectric layer 111 and the etch barrier layer 106, but also forms a natural barrier at the boundary of the groove structure, which plays a better role in blocking carrier diffusion and greatly improves the gate leakage problem. Furthermore, the presence of the groove releases lattice mismatch stress and avoids interface state problems caused by material interface mismatch. In addition, since the electric field is concentrated at the corner of the groove, filling the groove with the gate dielectric layer 111 can realize the field plate effect, which is also of practical significance for improving the breakdown voltage of the device.

[0061] Comparative Example 1

[0062] In comparison with the above embodiments, the present invention also provides another GaN-based HEMT device 100, the schematic diagram of which is shown below. Figure 6 As shown, the structural difference between this device and the GaN-based HEMT device 100 in the embodiment lies only in the different groove etching of the etch stop layer 106 in the gate region. In this comparative example, the etch stop layer 106 in the gate groove region of the GaN-based HEMT device 100 does not employ a groove etching structure; that is, only a photolithography technique is needed to form a mask for the etch stop layer 106 in the source and drain regions before ICP etching, without needing to remove the etch stop layer 106 in the gate groove region. The gate dielectric layer 111 in the device's gate groove region is deposited on the flat, unetched etch stop layer 106. Since the etch stop layer 106 is made of a III-V group compound Al... y Ga 1-yN, 0.75≤y≤0.8, has a large lattice mismatch with the Si3N4 gate dielectric layer 111. Therefore, the interface trap states generated by the two will increase the gate leakage current and reduce the gate's turn-off capability of the device.

[0063] Comparative Example 2

[0064] In comparison with the above embodiments, the present invention also provides another GaN-based HEMT device 100, the schematic diagram of which is shown below. Figure 7 As shown; the epitaxial structure of the device in this comparative example differs from that of the GaN-based HEMT device 100 in the embodiment; in this comparative example, no etch stop layer is inserted in the first barrier layer 105, that is, the epitaxial growth process sequentially grows the nucleation layer 102, buffer layer 103, channel layer 104, and first barrier layer 105 on the substrate 101, wherein the first barrier layer 105 is a III-V group compound Al. x Ga 1-x N, 0.1≤x≤0.3, thickness is 28~30nm; after device isolation, the epitaxial layer is masked by photolithography to form the first barrier layer 105 of the source, drain and gate regions. ICP etching is used to etch to a distance of 3~6nm from the bottom of the first barrier layer 105, then source and drain metal is deposited and annealed to obtain source and drain 110; gate dielectric layer 111 is deposited on the device, and finally gate metal is deposited on the gate dielectric layer 111 in the gate recess region to obtain gate 112; since the Al composition in the first barrier layer 105 is not much different, the precise control capability of ICP selective etching is poor. Over-etching and under-etching of the first barrier layer 105 in the source, drain and gate regions will lead to a decrease in device performance; in addition, the first barrier layer 105 and the Si3N4 gate dielectric layer 111 have a large lattice mismatch problem, similar to the device in Comparative Example 1, which is not conducive to the improvement of gate leakage capability and gate control capability.

[0065] Through the above design, the present invention divides the barrier layer into a first barrier layer and a second barrier layer by inserting an etch barrier layer, which can better control the etching rate of the barrier layer. The high selective etching capability of the etch barrier layer prevents the bottom first barrier layer from being over-etched and causing interface defects, forming a natural ohmic groove that is conducive to ohmic contact, thereby greatly reducing the ohmic contact resistance and improving the device output current and high frequency response capability.

[0066] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A GaN-based enhancement-mode HEMT device with barrier layer recess etching, comprising a substrate (101) and an epitaxial layer prepared on one side of the substrate (101), characterized in that, The epitaxial layer comprises, from bottom to top, a nucleation layer (102), a buffer layer (103), a channel layer (104), a first barrier layer (105), and an etching stop layer (106) which are sequentially stacked on a substrate (101), and a second barrier layer (107) on the first barrier layer (105); the epitaxial layer further comprises an ion implantation region (109) extending from the second barrier layer (107) to the buffer layer (103), a source / drain electrode (110) provided at the bottom of a source / drain recess region of the second barrier layer (107), a gate dielectric layer (111) deposited on the epitaxial layer away from the substrate (101), a gate electrode (112) provided above a gate recess region of the gate dielectric layer (111), a passivation layer (113) provided above the gate dielectric layer (111) and the gate electrode (112), an opening formed by sequentially etching the passivation layer (113) and the gate dielectric layer (111) above the source / drain electrode (110) and the gate electrode (112), and a metal interconnection layer (114) obtained by depositing metal in the opening; wherein the etching stop layer in the gate recess region of the second barrier layer is etched into a multi-recess structure, the bottom of the multi-recess structure is the first barrier layer, and the gate dielectric is filled in the recess structure; a two-dimensional electron gas layer (108) is formed at the interface between the channel layer (104) and the first barrier layer (105) due to polarization effect.

2. The barrier recessed etched GaN-based enhancement mode HEMT device of claim 1, wherein, The material of the first barrier layer (105) is a III-V compound Al x Ga 1-x N, 0.1≤x≤0.2, and the thickness is 3-5 nm; the material of the etching stop layer (106) is a III-V compound Al y Ga 1-y N, 0.75≤y≤0.8, and the thickness is 5-10 nm; the material of the second barrier layer (107) is a III-V compound Al z Ga 1-z N, 0.2≤z≤0.3, and the thickness is 23-25 nm.

3. A method for fabricating a GaN-based enhancement-mode HEMT device by etching a barrier layer groove, characterized in that, A GaN-based enhancement-mode HEMT device as claimed in claim 2 is prepared by the following steps: S1, selecting a substrate and preparing an epitaxial layer on one side of the substrate by metal organic chemical vapor deposition; S2, using photolithography mask technology to selectively etch the epitaxial layer to prepare a barrier layer recess, so that part of the source / drain recess region and the gate recess region of the second barrier layer is removed, and the etching stop layer (106) in the gate recess region is etched into a structure with the multi-recess; S3, preparing a gate dielectric, a passivation layer, and an electrode of the HEMT device above the epitaxial layer etched by the barrier layer recess, and completing the preparation of the HEMT device.

4. The method of claim 3, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The specific process of step S1 is as follows: S11, providing a substrate and cleaning the substrate; S12, using metal organic chemical vapor deposition to sequentially grow a nucleation layer (102), a buffer layer (103), a channel layer (104), a first barrier layer (105), and an etching stop layer (106) on the substrate (101); S13, using uniform glue photolithography development technology to form a mask on the etching stop layer (106) in the source / drain (110) recess region and the gate (112) recess region, and using an inductively coupled plasma etching device to selectively etch and remove the etching stop layer (106) except in the source / drain (110) and gate (112) regions to form an epitaxial wafer; S14, cleaning the epitaxial wafer, removing the photoresist, and using dilute HCl and ultrapure water diluted at a ratio of 1:10 to soak the epitaxial wafer, remove the etching residue, and then clean the defects after etching and passivation by plasma; S15, continuing to grow a second barrier layer (107) on the first barrier layer (105) using metal organic chemical vapor deposition, the second barrier layer (107) covering the etching stop layer (106) and continuing to grow to obtain an epitaxial layer; wherein, after the growth of the second barrier layer (107) is completed, a two-dimensional electron gas layer (108) is formed due to the polarization between the channel layer (104) and the first barrier layer (105) and the second barrier layer (107).

5. The method of claim 3, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The substrate is any one of a sapphire substrate, a Si substrate, a GaN substrate, and a SiC substrate.

6. The method of claim 3, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The specific process of the step S2 is as follows: S21, using a uniform glue photoetching and developing technology to define an active region of the HEMT device to form a device isolation mask on the epitaxial layer, and using an ion implantation device to complete device isolation; S22, cleaning the epitaxial layer after device isolation, using a uniform glue photoetching and developing technology to form a mask on the second barrier layer (107) in a source-drain recess region and a gate recess region, and using a plasma etching device to perform selective etching to remove the second barrier layer (107) in the source-drain recess region and the gate recess region; S23, cleaning the epitaxial layer after etching, using a uniform glue photoetching and developing technology to form a mask on the etching stop layer (106) in the source-drain recess region and the gate recess region, and using an ICP to etch the etching stop layer (106) in the source-drain recess region and the etching stop layer (106) in the gate recess region; wherein, due to a plurality of uniformly distributed photoresist masks, the etching stop layer (106) in the gate recess region is etched into a structure with a plurality of recesses, and the bottom of the etching stop layer (106) in the plurality of recesses is the first barrier layer (105); S24, after etching, cleaning the epitaxial layer to remove photoresist, and then immersing the epitaxial layer in diluted HCl and ultrapure water at a ratio of 1:10 to remove residual stains after etching, and finally using plasma cleaning to passivate and etch defects after etching, to complete barrier layer recess etching.

7. The method of claim 3, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The specific process of the step S3 is as follows: S31, cleaning the epitaxial layer after etching, using a uniform glue photoetching and developing technology to form a mask on the source-drain recess region, using an electron beam evaporation device to perform metal evaporation on the source-drain, and obtaining an ohmic contact between the source-drain (110) and the first barrier layer (105) through high-temperature rapid annealing after metal stripping; S32, using a plasma-enhanced chemical vapor deposition device to deposit a gate dielectric layer (111) above the second barrier layer (107), the bottom of the gate dielectric layer (111) in the gate recess region being in contact with the first barrier layer (105), and the gate dielectric layer (111) filling the recess region of the etching stop layer (106) and continuing to deposit and cover the recess structure; S33, using uniform glue photoetching and developing to form a mask on the gate recess region, and using an electron beam evaporation device to evaporate metal on the gate dielectric in the gate recess region to prepare a gate (112); S34, using plasma-enhanced chemical vapor deposition to prepare a passivation layer (113) above the gate dielectric layer, and using photoresist uniform glue photoetching and developing technology to form an opening mask of the source-drain (110) and the gate (112); S35, using the plasma etching equipment to etch the passivation layer (113) and the gate dielectric layer (111) of the source-drain region in sequence to form an opening; S36, after the opening etching is completed, the epitaxial wafer is soaked after being diluted according to a ratio of 1:10 using dilute HCl and ultrapure water, residual stains after etching are removed, a metal interconnection layer (114) is prepared by using an electron beam evaporation equipment to evaporate metal in the opening area, and the HEMT device preparation is completed.

8. The method of claim 4, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The nucleation layer (102) is AlN material with a thickness of 20-100 nm; the buffer layer (103) is high-resistance GaN material doped with carbon or Al components with a thickness of 500-650 nm; and the channel layer (104) is low-doped GaN material with a thickness of 150-200 nm.

9. The method of claim 6, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The groove etching shape of the etching barrier layer is a structure of vertical grooves, trapezoidal grooves or inverted trapezoidal grooves arranged uniformly and regularly.

10. The method of claim 7, wherein the barrier layer recess etching of the GaN-based enhancement-mode HEMT device is characterized by: The electrode structure of the source-drain electrode is a Ti / Al / Ni / Au metal stack structure, and the corresponding metal thickness is 20 / 130 / 50 / 100 nm; the electrode structure of the gate electrode is a Ni / Au metal stack structure, and the corresponding metal thickness is 50 / 100 nm; the electrode metal of the metal interconnection layer (114) is the same as the metal stack structure of the gate electrode (112); and the gate dielectric is dense Si3N4 with a thickness of 35-50 nm.

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