Groove MOS device and manufacturing method thereof
By using a hard mask layer and polysilicon gate self-aligned mask technology in trench MOS devices, the position of the P+ region is precisely controlled, solving the Rdson and VTH discrete problems caused by lithography alignment errors, improving device consistency and yield, and is suitable for the power semiconductor field.
Patent Information
- Application Number
- CN202510929984.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-10-03
AI Technical Summary
In the manufacturing of trench MOS devices, insufficient lithography alignment accuracy in the P+ region or deviations in the etching and ion implantation processes result in inconsistencies between the P+ region and the gate position, leading to discrete Rdson and VTH, affecting device performance and system stability, especially in automotive and industrial applications, resulting in a decrease in yield.
A hard mask layer is used to process trenches and generate a polysilicon gate as a self-aligned mask. High-concentration N-type heavily doped regions are implanted through the polysilicon gate. Combined with the etching window of the masking oxide layer, the position of the source and gate are precisely controlled. The polysilicon gate is used as a physical mask for the high-concentration P-type doped region, and the lateral deviation between the drain region and the gate is controlled within ±50Å.
It improves alignment accuracy, reduces P+ area offset, stabilizes Rdson and VTH, improves device consistency, reduces yield loss, and is suitable for application scenarios with high reliability requirements.
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Figure CN120751730A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor processing technology, and in particular to a trench MOS device and a manufacturing method thereof. Background Art
[0002] Trench MOS devices, due to their vertical trench structure, have lower on-resistance (Rdson) and higher power density than traditional planar MOSFETs and are widely used in the power semiconductor field (such as power management and motor drive).
[0003] In traditional trench MOS manufacturing, the injection of the N-type source region into the P-type body region (P+ region) usually relies on multiple alignments of the photolithography mask. If the photolithography alignment accuracy is insufficient (such as an offset of more than ±500Å) or there are process deviations during etching and ion implantation, the relative position of the P+ region and the gate will be inconsistent, resulting in regional offset.
[0004] The offset of the P+ region will change the channel length and current path. If the P+ region deviates from the bottom of the gate, the effective length of the channel increases, and the resistance path through which the current flows becomes longer, resulting in an increase in Rdson. Conversely, if the offset is too close, it may cause local current concentration and Rdson fluctuations. The difference in the position of the P+ region of different devices on the same wafer will cause the Rdson to be significantly discrete within the chip, affecting the parallel application of power devices and system thermal management.
[0005] At the same time, the offset of the P+ region will also lead to uneven distribution of doping concentration in the channel or changes in the effective channel length, thereby causing VTH to deviate from the designed value. VTH dispersion will lead to inconsistent turn-on timing of transistors on the same chip, causing timing errors in the logic circuit or differences in switching losses of power devices, reducing system stability.
[0006] When Rdson and VTH dispersion exceeds the design tolerance, unqualified devices must be removed through screening tests, resulting in a decrease in yield and increased manufacturing costs. This dispersion issue is particularly prominent in high-reliability scenarios such as automotive and industrial applications. Therefore, it is necessary to design a trench MOS device and trench MOS device manufacturing method that can eliminate P+ region skew. Summary of the Invention
[0007] The present application provides a trench MOS device.
[0008] The present application provides a trench MOS device that adopts the following technical solution: A trench MOS device comprises a substrate and an epitaxial layer, wherein a plurality of polysilicon gates are provided on the epitaxial layer and the plurality of polysilicon gates are embedded in the epitaxial layer, a gate oxide layer is provided at the bottom and sides of the polysilicon gates, P-type lightly doped ions are vertically implanted on the epitaxial layer to form a P-type body region, N-type heavily doped ions are vertically implanted on the epitaxial layer to form a high-concentration N-type doped region, the high-concentration N-type doped region is located between the plurality of polysilicon gates, P-type heavily doped ions are vertically implanted between the polysilicon gates to form a high-concentration P-type doped region, the high-concentration P-type doped region is located in the middle of the high-concentration N-type doped region, an interlayer dielectric is generated on the epitaxial layer, an inverted trapezoidal contact hole is etched on the interlayer dielectric, the bottom of the contact hole is connected to the gate oxide layer and the high-concentration P-type doped region, a first metal layer is formed in the contact hole, a second metal layer is formed on the interlayer dielectric and the second metal layer is connected to the gate oxide layer and the high-concentration P-type doped region.
[0009] This application provides a method for manufacturing a trench MOS device, which adopts the following technical solution: A method for manufacturing a trench MOS device comprises the following steps: S1: growing an epitaxial layer on a substrate and depositing a hard mask layer on the epitaxial layer; S2, coating a photoresist on the hard mask layer, performing photolithography on the hard mask layer and producing a groove pattern; S3, removing the photoresist, etching the trench on the epitaxial layer using the hard mask layer as a masking layer, and removing the hard mask layer; S4, growing or depositing a gate oxide layer on the bottom and sidewalls of the trench, and depositing a polysilicon gate in the gate oxide layer, wherein the height of the polysilicon gate is equal to the height of the gate oxide layer; S5, etching away the polysilicon gate and the gate oxide layer outside the preset body region, and reducing the height of the gate oxide layer so that the polysilicon gate protrudes from the gate oxide layer, performing body ion implantation and body ion drive on the epitaxial layer in a vertical direction, wherein the implanted ions are P-type lightly doped ions to form a P-type body region; S6, using the polysilicon gate as a self-aligned mask to vertically perform source implantation on both sides of the P-type body region, where the implanted ions are N-type heavily doped ions, to form a high-concentration N-type doped region; S7, removing the gate oxide layer, forming a masking oxide layer on the epitaxial layer and the polysilicon gate, etching and ion implantation between the polysilicon gate on the masking oxide layer, wherein the implanted ions are P-type heavily doped ions, to form a high-concentration P-type doped region; S8, trimming the polysilicon gate and the masking oxide layer until the polysilicon gate and the masking oxide layer are at the same height and have a flat surface, and depositing an interlayer dielectric on the trimmed surface; S9, photolithographically defining the position of the contact hole on the interlayer dielectric, etching through the masking oxide layer to expose the contact point between the high-concentration P-type doped region and the polysilicon gate; S10, generating a first metal layer in the contact hole, depositing a second metal layer on the interlayer dielectric and forming an electrode lead.
[0010] Preferably, in step S1, a first buffer oxide layer is first generated on the epitaxial layer, and then the hard mask layer is formed on the first buffer oxide layer by chemical vapor deposition, the hard mask layer is silicon nitride, and a second buffer oxide layer is arranged between the hard mask layer and the photoresist, the first buffer oxide layer and the second buffer oxide layer are both silicon dioxide, the thickness of the first buffer oxide layer is 50A-500A, and the thickness of the second buffer oxide layer is 100A-200A.
[0011] Preferably, in step S2, the etching depth of the groove is 6000A-10000A.
[0012] Preferably, in step S4, before forming the gate oxide layer, a sacrificial oxide layer is formed in the hard mask layer and the trench by thermal oxidation, and the sacrificial oxide layer is removed with a hydrofluoric acid solution to repair damage defects in the hard mask layer and the trench.
[0013] Preferably, the gate oxide layer in step S4 is formed by thermal oxidation, and the thickness of the gate oxide layer is 200Å-250Å.
[0014] Preferably, in step S5, a diluted hydrofluoric acid solution is used to perform wet etching to selectively remove the gate oxide outside the polysilicon gate and on the preset body region), and then a CF4 dry etching is used to etch back the gate oxide layer.
[0015] Preferably, in step S8, the polysilicon gate and the masking oxide layer are trimmed by chemical etching, mechanical grinding or a combination of the two.
[0016] Preferably, in step S9, the contact hole is made by dry etching, and the cross-sectional shape of the contact hole is an inverted trapezoid.
[0017] Preferably, in step S10, the first metal layer is titanium, titanium nitride or a copper-aluminum alloy layer, and the second metal layer is copper, aluminum or tungsten.
[0018] In summary, this application includes at least one of the following beneficial technical effects: 1. In this application, a hard mask layer is generated on the epitaxial layer and a trench is processed through the hard mask layer to generate a polysilicon gate in the trench. The polysilicon gate is used as a self-aligned mask for high-concentration N-type heavily doped region (source). No additional photolithography steps are required, and the relative positions of the source and gate can be precisely controlled to reduce alignment errors. At the same time, the polysilicon gate is raised above the gate oxide layer. When the drain region is injected, the raised polysilicon gate can be used as a physical mask for the injection of the high-concentration P-type doped region (drain region). Combined with the etching window of the masking oxide layer, the lateral deviation between the drain region and the gate can be controlled within ±50Å, further improving the alignment accuracy and avoiding offset. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a schematic diagram of the structure of the groove in Example 1 of the present application.
[0020] Figure 2 This is a structural diagram of the second embodiment of the present application. Figure 3 This is a structural diagram of the second embodiment of the present application. Figure 4 This is a structural diagram of Example 2 of the present application.
[0021] Figure 5 This is a structural diagram of Example 2 of the present application.
[0022] Figure 6 This is a structural diagram of Example 2 of the present application.
[0023] Figure 7 This is a structural diagram of Example 2 of the present application.
[0024] Figure 8 This is a structural diagram of Example 2 of the present application.
[0025] Figure 9 This is a structural diagram of Example 2 of the present application.
[0026] Figure 10 This is a structural diagram of Example 2 of the present application.
[0027] Figure 11 This is a structural diagram of Example 2 of the present application.
[0028] Explanation of the accompanying symbols: 1. substrate; 2. epitaxial layer; 3. hard mask layer; 4. photoresist; 5. trench; 6. gate oxide layer; 7. polysilicon gate; 8. P-type body region; 9. high-concentration N-type doped region; 10. masking oxide layer; 11. high-concentration P-type doped region; 12. interlayer dielectric; 13. first metal layer; 14. second metal layer. DETAILED DESCRIPTION
[0029] The present application is further described in detail below with reference to the accompanying drawings.
[0030] Example 1: An embodiment of the present application discloses a trench MOS device.
[0031] Reference Figure 1 and Figure 11 A trench MOS device includes a substrate 1 and an epitaxial layer 2. A plurality of polysilicon gates 7 are provided on the epitaxial layer 2 and the plurality of polysilicon gates 7 are embedded in the epitaxial layer 2. A gate oxide layer 6 is provided at the bottom and side of the polysilicon gate 7. P-type lightly doped ions are vertically implanted on the epitaxial layer 2 to form a P-type body region 8. N-type heavily doped ions are vertically implanted on the epitaxial layer 2 to form a high-concentration N-type doped region 9. The high-concentration N-type doped region 9 is located between the plurality of polysilicon gates 7. P-type heavily doped ions are introduced to form a high-concentration P-type doped region 11, which is located in the middle of the high-concentration N-type doped region 9. An interlayer dielectric 12 is generated on the epitaxial layer 2, and an inverted trapezoidal contact hole is etched on the interlayer dielectric 12. The bottom of the contact hole is connected to the gate oxide layer 6 and the high-concentration P-type doped region 11. A first metal layer 13 is formed in the contact hole, and a second metal layer 14 is formed on the interlayer dielectric 12, and the second metal layer 14 is connected to the gate oxide layer 6 and the high-concentration P-type doped region 11.
[0032] Example 2: A method for manufacturing a trench MOS device comprises the following steps: S1: Reference Figure 2 An epitaxial layer 2 is grown on a substrate 1, and a hard mask layer 3 is deposited on the epitaxial layer 2. Specifically, in this embodiment, a first buffer oxide layer is first generated on the epitaxial layer 2, and then a hard mask layer 3 is formed on the first buffer oxide layer by chemical vapor deposition. The hard mask layer 3 is silicon nitride. A second buffer oxide layer is provided between the hard mask layer 3 and the photoresist 4. Both the first buffer oxide layer and the second buffer oxide layer are silicon dioxide. The thickness of the first buffer oxide layer is 50A-500A, and the thickness of the second buffer oxide layer is 100A-200A.
[0033] S2, reference Figure 3 , a photoresist 4 is coated on the hard mask layer 3, and a pattern of a groove 5 is produced by photolithography on the hard mask layer 3. The etching depth of the groove 5 is 6000A-10000A.
[0034] S3. Reference Figure 3 and Figure 4 , remove the photoresist 4, etch a trench 5 on the epitaxial layer 2 using the hard mask layer 3 as a masking layer, and remove the hard mask layer 3; S4, reference Figure 5A gate oxide layer 6 is grown or deposited on the bottom and sidewalls of the trench 5. The gate oxide layer 6 is generated by thermal oxidation and has a thickness of 200 Å to 250 Å. Then, a polysilicon gate 7 is deposited in the gate oxide layer 6. The height of the polysilicon gate 7 is equal to the height of the gate oxide layer 6. Specifically, in this embodiment, before generating the gate oxide layer 6, a sacrificial oxide layer is first generated on the hard mask layer 3 and in the trench 5. The sacrificial oxide layer is thermally oxidized in a wet oxygen environment at 850° C. to grow and cut to a thickness of 10 nm to 15 nm. Then, a diluted hydrofluoric acid solution or a buffered oxide etchant is used to remove the sacrificial oxide layer to repair damage defects in the hard mask layer 3 and the trench 5.
[0035] S5. Etch away the polysilicon gate 7 and the gate oxide layer 6 outside the preset body region, and reduce the height of the gate oxide layer 6 so that the polysilicon gate 7 protrudes from the gate oxide layer 6, perform body ion implantation and body ion drive on the epitaxial layer 2 in a vertical direction, and the implanted ions are P-type lightly doped ions to form a P-type body region 8; specifically, use a diluted hydrofluoric acid solution to perform wet etching to selectively remove the gate oxide layer 6 outside the polysilicon gate 6 and on the preset body region, and then use CF4 dry etching to etch back the gate oxide layer 6. Specifically, in this embodiment, the height of the polysilicon gate protrudes from the height of the gate oxide layer by 500Å-1000Å.
[0036] S6, reference Figure 7 , using the polysilicon gate 7 as a self-aligned mask to vertically perform source implantation on both sides of the P-type body region 8, the implanted ions are N-type heavily doped ions, forming a high-concentration N-type doped region 9; S7, reference Figure 8 , removing the gate oxide layer 6, forming a masking oxide layer 10 on the epitaxial layer 2 and the polysilicon gate 7, performing etching and ion implantation between the polysilicon gate 7 on the masking oxide layer 10, wherein the implanted ions are P-type heavily doped ions, forming a high-concentration P-type doped region 11; S8. Reference Figure 9 , using chemical etching, mechanical grinding or a combination of the two to trim the polysilicon gate 7 and the masking oxide layer 10 until the polysilicon gate 7 and the masking oxide layer 10 are highly consistent and have a flat surface, and depositing an interlayer dielectric 12 on the modified surface; S9, reference Figure 10 The contact hole is formed by photolithography on the interlayer dielectric 12. The contact hole is made by dry etching. The cross-section of the contact hole is an inverted trapezoid. The etching penetrates the masking oxide layer 10 to expose the contact point between the high-concentration P-type doped region 11 and the polysilicon gate 7. S10, reference Figure 11A first metal layer 13 is generated in the contact hole, and a second metal layer 14 is deposited on the interlayer dielectric 12 to form an electrode lead. The first metal layer 13 is titanium, titanium nitride or a copper-aluminum alloy layer, and the second metal layer 14 is copper, aluminum or tungsten.
[0037] The implementation principle is as follows: in this application, a hard mask layer 3 is generated on the epitaxial layer 2 and a groove 5 is processed through the hard mask layer 3, a polysilicon gate 7 is generated in the groove 5, and the high-concentration N-type heavily doped region 9 is injected using the polysilicon gate 7 as a self-aligned mask. Without the need for additional photolithography steps, the relative position of the source and the gate can be accurately controlled to reduce alignment errors; at the same time, the polysilicon gate 7 is protruded from the gate oxide layer 6, and when the drain region is injected, the protruding polysilicon gate 7 can be used as a physical mask for injecting a high-concentration P-type doped region (drain region). Combined with the etching window of the masking oxide layer 10, the lateral deviation between the drain region and the gate can be controlled within ±50Å, further improving the alignment accuracy and avoiding offset.
[0038] The above are all preferred embodiments of the present application, and are not intended to limit the scope of protection of the present application. Therefore, any equivalent changes made based on the structure, shape, and principle of the present application should be included in the scope of protection of the present application.
Claims
1. A trench MOS device, characterized in that: The invention comprises a substrate (1) and an epitaxial layer (2), wherein a plurality of polysilicon gates (7) are provided on the epitaxial layer (2) and the plurality of polysilicon gates (7) are embedded in the epitaxial layer (2), a gate oxide layer (6) is provided at the bottom and side of the polysilicon gates (7), a P-type body region (8) is formed by vertically injecting P-type lightly doped ions into the epitaxial layer (2), a high-concentration N-type doped region (9) is formed by vertically injecting N-type heavily doped ions into the epitaxial layer (2), the high-concentration N-type doped region (9) is located between the plurality of polysilicon gates (7), and the P-type heavily doped ions are vertically injected between the polysilicon gates (7). A high-concentration P-type doping region (11) is formed on the epitaxial layer (2), and the high-concentration P-type doping region (11) is located in the middle of the high-concentration N-type doping region (9). An interlayer dielectric (12) is generated on the epitaxial layer (2), and an inverted trapezoidal contact hole is etched on the interlayer dielectric (12). The bottom of the contact hole is connected to the gate oxide layer (6) and the high-concentration P-type doping region (11). A first metal layer (13) is formed in the contact hole, and a second metal layer (14) is formed on the interlayer dielectric (12), and the second metal layer (14) is connected to the gate oxide layer (6) and the high-concentration P-type doping region (11).
2. A method for manufacturing a trench MOS device, characterized in that: The following steps are involved: S1: growing an epitaxial layer (2) on a substrate (1), and depositing a hard mask layer (3) on the epitaxial layer (2); S2, coating a photoresist (4) on the hard mask layer (3), performing photolithography on the hard mask layer (3) and producing a pattern of a groove (5); S3, removing the photoresist (4), etching the groove (5) on the epitaxial layer (2) using the hard mask layer (3) as a masking layer, and removing the hard mask layer (3); S4, growing or depositing a gate oxide layer (6) on the bottom and sidewalls of the trench (5), and depositing a polysilicon gate (7) in the gate oxide layer (6), wherein the height of the polysilicon gate (7) is equal to the height of the gate oxide layer (6); S5, etching away the polysilicon gate (7) and the gate oxide layer (6) outside the preset body region, and reducing the height of the gate oxide layer (6) so that the polysilicon gate (7) protrudes from the gate oxide layer (6), performing body region ion implantation and body region ion drive on the epitaxial layer (2) in a vertical direction, wherein the implanted ions are P-type lightly doped ions, thereby forming a P-type body region (8); S6, using the polysilicon gate (7) as a self-aligned mask to vertically perform source implantation on both sides of the P-type body region (8), wherein the implanted ions are N-type heavily doped ions, thereby forming a high-concentration N-type doped region (9); S7, removing the gate oxide layer (6), forming a masking oxide layer (10) on the epitaxial layer (2) and the polysilicon gate (7), performing etching and ion implantation between the polysilicon gate (7) on the masking oxide layer (10), wherein the implanted ions are P-type heavily doped ions, thereby forming a high-concentration P-type doped region (11); S8, trimming the polysilicon gate (7) and the masking oxide layer (10) until the polysilicon gate (7) and the masking oxide layer (10) are highly consistent and have a flat surface, and depositing an interlayer dielectric (12) on the trimmed surface; S9, photolithographically defining the position of the contact hole on the interlayer dielectric (12), etching through the masking oxide layer (10), and exposing the contact point between the high-concentration P-type doping region (11) and the polysilicon gate (7); S10, generating a first metal layer (13) in the contact hole, depositing a second metal layer (14) on the interlayer dielectric (12) and forming an electrode lead.
3. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S1, a first buffer oxide layer is first generated on the epitaxial layer (2), and then the hard mask layer (3) is formed on the first buffer oxide layer by chemical vapor deposition. The hard mask layer (3) is silicon nitride. A second buffer oxide layer is provided between the hard mask layer (3) and the photoresist (4). Both the first buffer oxide layer and the second buffer oxide layer are silicon dioxide. The thickness of the first buffer oxide layer is 50 Å-500 Å, and the thickness of the second buffer oxide layer is 100 Å-200 Å.
4. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S2, the etching depth of the groove (5) is 6000A-10000A.
5. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S4, before generating the gate oxide layer (6), a sacrificial oxide layer is generated in the hard mask layer (3) and the trench (5) by a thermal oxidation method, and the sacrificial oxide layer is removed with a hydrofluoric acid solution to repair damage defects in the hard mask layer (3) and the trench (5).
6. The method for manufacturing a trench MOS device according to claim 2, wherein: The gate oxide layer (6) in step S4 is generated by thermal oxidation, and the thickness of the gate oxide layer (6) is 200 Å-250 Å.
7. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S5, a diluted hydrofluoric acid solution is used to perform wet etching to selectively remove the gate oxide layer (6) outside the polysilicon gate (6) and on the preset body region, and then the gate oxide layer (6) is etched back using CF4 dry etching.
8. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S8, the polysilicon gate (7) and the masking oxide layer (10) are trimmed by chemical etching, mechanical grinding, or a combination of the two.
9. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S9, the contact hole is made by dry etching, and the cross-sectional shape of the contact hole is an inverted trapezoid.
10. The method for manufacturing a trench MOS device according to claim 2, wherein: In step S10, the first metal layer (13) is titanium, titanium nitride or a copper-aluminum alloy layer, and the second metal layer (14) is copper, aluminum or tungsten.