Power semiconductor device and method of manufacturing the same
By adopting a trench split gate structure and an electric field shielding area design in a power semiconductor device, the problem of insufficient split gate design in the prior art is solved, a balance between high current density and high breakdown voltage is achieved, and the performance of the high-power semiconductor device is optimized.
Patent Information
- Application Number
- CN202410357219.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-27
- Publication Date
- 2025-10-03
AI Technical Summary
The split-gate design of existing power semiconductor devices has shortcomings in improving switching speed and reducing on-resistance, especially in high voltage and high current applications.
A trench split gate structure is adopted. By forming separate first and second gates in the epitaxial layer and setting an electric field shielding area between them, gate oxide layers of different thicknesses are used to optimize the direction and angle of the channel region. The doping concentration and area size of the electric field shielding area are combined to adjust the on-resistance and breakdown voltage.
The current density and breakdown voltage of power semiconductor devices are improved, the process of high-power semiconductor devices is optimized, the electric field shielding effect is enhanced, and the performance indicators of the devices are improved.
Smart Images
Figure CN120751739A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a power semiconductor device, and more particularly to a power semiconductor device having a trench-type split gate. Background Art
[0002] With advances in semiconductor technology, the application of metal-oxide-semiconductor field-effect transistors (MOSFETs) is becoming increasingly widespread. Power semiconductors can be used as switches in electronic components. They are used in high-voltage and high-current device designs. The switching speed and on-resistance of power semiconductors are closely related to their split-gate design. Summary of the Invention
[0003] A technical aspect of the present disclosure is a power semiconductor device.
[0004] In one embodiment of the present disclosure, a power semiconductor device includes a drain metal, a base layer located above the drain metal, an epitaxial layer located above the base layer and having a first conductivity type, a split gate located in the epitaxial layer, an electric field shielding region, a gate oxide layer, and a source metal. The split gate includes a first gate and a second gate, with the second gate located above the first gate. The electric field shielding region is located in the epitaxial layer and surrounds at least the first gate and has the second conductivity type. The gate oxide layer is located between the split gate and the epitaxial layer. The source metal is located on the epitaxial layer.
[0005] In one embodiment of the present disclosure, the first gate and the second gate are separated from each other, and the first gate is electrically connected to the source metal.
[0006] In one embodiment of the present disclosure, the electric field shielding region includes a first shielding region, a second shielding region, and a third shielding region, and a vertical projection of the second gate on the base layer overlaps with the vertical projections of the first shielding region and the second shielding region on the base layer.
[0007] In one embodiment of the present disclosure, the power semiconductor device further includes source / drain doped regions, a first gate oxide layer, and a second gate oxide layer. The source / drain doped regions are located in the epitaxial layer adjacent to the second gate. The first gate oxide layer is located between the electric field shielding region and the first gate. The second gate oxide layer is located between the source / drain doped regions and the second gate.
[0008] In one embodiment of the present disclosure, the second thickness of the second gate oxide layer is smaller than the first thickness of the first gate oxide layer.
[0009] Another technical aspect of the present disclosure is a method for manufacturing a semiconductor device.
[0010] In one embodiment of the present disclosure, a method for manufacturing a semiconductor device includes forming an epitaxial layer on a base layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer, wherein the first trench has a trench sidewall; implanting the trench sidewall to form an electric field shielding region, wherein the electric field shielding region has a second conductivity type and surrounds at least a lower portion of the trench sidewall; expanding an upper portion of the trench sidewall to form a second trench; forming a gate oxide layer in the first trench and the second trench and forming a split gate in the first trench and the second trench.
[0011] In one embodiment of the present disclosure, forming gate oxide layers in the first trench and the second trench includes forming a first gate oxide layer in the first trench; and after forming the second trench, forming a second gate oxide layer in the second trench.
[0012] In one embodiment of the present disclosure, forming the gate oxide layer in the first trench and the second trench includes making the second thickness of the second gate oxide layer smaller than the first thickness of the first gate oxide layer.
[0013] In one embodiment of the present disclosure, forming a split gate in the first trench and the second trench includes forming a first gate oxide layer in the first trench and then forming a first gate in the first gate oxide layer; and forming a second gate on the first gate after forming a second gate oxide layer in the second trench.
[0014] In one embodiment of the present disclosure, enlarging the upper portion of the trench sidewall to form the second trench includes removing a portion of the epitaxial layer adjacent to the upper portion of the trench sidewall before forming the second gate on the first gate, so that the second width of the second trench is greater than the first width of the first trench.
[0015] In the above-mentioned embodiment, the semiconductor device with a trench-type split gate has a longitudinal channel region to increase the current density. The direction and angle of the channel region can be determined by the sidewall of the trench that accommodates the second gate. By providing an electric field shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By providing gate oxide layers with different thicknesses and providing a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific angle, gate oxide layers with different thicknesses, and a split gate to optimize the process of high-power semiconductor devices. The doping concentration and area size of the electric field shielding region can be varied to adjust the on-resistance and breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 FIG. 4 is a cross-sectional view of a power semiconductor device according to an embodiment of the present disclosure.
[0017] Figures 2 to 6 for Figure 1 A cross-sectional view of an intermediate step in a method for manufacturing a power semiconductor device. DETAILED DESCRIPTION
[0018] The following will disclose multiple embodiments of the present invention with the accompanying drawings. For the purpose of clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention.
[0019] Figure 1 FIG1 is a cross-sectional view of a power semiconductor device 100 according to an embodiment of the present disclosure. The power semiconductor device 100 includes a drain metal 110 , a base layer 120 , an epitaxial layer 130 , a split gate 140 , a source / drain doped region 150 , an electric field shielding region 160 , a gate oxide layer 170 , and a source metal 180 .
[0020] The base layer 120 is located on the drain metal 110. The epitaxial layer 130 is located on the base layer 120 and has a first conductivity type (N-type). The split gate 140 is located in the epitaxial layer 130. For example, the power semiconductor device 100 in this embodiment is an N-type metal oxide semiconductor field effect transistor (MOSFET). The base layer 120 is an N-type heavily doped substrate (N+). The base layer 120 is, for example, a silicon carbide (SiC) substrate. The doping concentration of the epitaxial layer 130 is lower than the doping concentration of the base layer 120 (N-). The epitaxial layer 130 can serve as a drift region between the source and the drain.
[0021] The split gate 140 includes a first gate 142 and a second gate 144, which are separated from each other. The second gate 144 is located above the first gate 142. The second gate 144 is a gate electrode (gate poly), while the first gate 142 is a shielding electrode and is electrically connected to the source metal 180. The second width W2 of the second gate 144 is greater than the first width W1 of the first gate 142.
[0022] The source / drain doped region 150 is located in the epitaxial layer 130 adjacent to the second gate 144. The source / drain doped region 150 includes a source region 152 having a first conductivity type (N+) and a well 154 having a second conductivity type (P). The source region 152, the well 154, and the second gate 144 form a channel region 156.
[0023] The electric field shielding region 160 is located in the epitaxial layer 130 and surrounds at least the first gate 142. It has the second conductivity type (P+). The electric field shielding region 160 includes a first shielding region 162, a second shielding region 164, and a third shielding region 166 that are connected to each other. The electric field shielding region 160 is formed by an implantation process. The first shielding region 162 and the second shielding region 164 are respectively formed in the epitaxial layer 130 on opposite sides adjacent to the first gate 142. The first shielding region 162 and the second shielding region 164 are located below the channel region 156. The third shielding region 166 is formed in the epitaxial layer 130 at the bottom of the first gate 142.
[0024] The gate oxide layer 170 is located between the split gate 140 and the epitaxial layer 130. The source metal 180 is located on the epitaxial layer 130. The gate oxide layer 170 includes a first gate oxide layer 172 and a second gate oxide layer 174. The first gate oxide layer 172 is located between the first shielding region 162, the second shielding region 164, the third shielding region 166, and the first gate 142. The second gate oxide layer 174 is located at least between the source / drain doped region 150 and the second gate 144. A portion of the second gate oxide layer 174 is located between the first gate 142 and the second gate 144. The first gate oxide layer 172 is connected to the second gate oxide layer 174 and is made of the same material. The second gate oxide layer 174 located between the source / drain doped region 150 and the second gate 144 has a second thickness T2, which is less than the first thickness T1 of the first gate oxide layer 172.
[0025] Since the split gate 140 is a trench structure, the channel region 156 is oriented vertically rather than horizontally, which increases the density of the split gate 140 and improves the current density. The electric field shielding region 160 can be provided to shield the strong electric field in the vertical power semiconductor device.
[0026] The electric field shielding region 160 includes a plurality of first shielding regions 162 and second shielding regions 164 , the length and spacing of which can be set according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100 .
[0027] like Figure 1 As shown in FIG, the direction and angle of the channel region 156 can be determined by the epitaxial layer 130 surrounding the second gate 144. The trench sidewalls 190 include a first sidewall 192, a second sidewall 194, a third sidewall 196, and a fourth sidewall 198. The channel region 156 is distributed along the trench sidewalls 190 of the second trench TR2. The first sidewall 192 is opposite to the second sidewall 194. The third sidewall 196 is opposite to the fourth sidewall 198. The first sidewall 192 is connected to the third sidewall 196, and the second sidewall 194 is connected to the fourth sidewall 198.
[0028] First sidewall 192 and second sidewall 194 correspond to the lower portion of trench sidewall 190, and third sidewall 196 and fourth sidewall 198 correspond to the upper portion of trench sidewall 190. Electric field shielding region 160 surrounds at least the lower portion of trench sidewall 190. First shielding region 162 is adjacent to first sidewall 192, and second shielding region 164 is adjacent to second sidewall 194.
[0029] A first distance L1 between the first sidewall 192 and the second sidewall 194 in the first transverse direction D1 is smaller than a second distance L2 between the third sidewall 196 and the fourth sidewall 198 in the first transverse direction D1 .
[0030] The first gate 142 is housed in the first trench TR1, and the second gate 144 is housed in the second trench TR2. The first trench TR1 communicates with the second trench TR2. The first distance L1 corresponds to the average width of the first trench TR1 that houses the first gate 142, while the second distance L2 corresponds to the average width of the second trench TR2 that houses the second gate 144. The vertical projection of the second gate 144 on the base layer 120 overlaps with the vertical projections of the first shielding region 162 and the second shielding region 164 on the base layer 120. The second trench TR2 is formed by further etching the first trench TR1, which will be described in detail later.
[0031] In other embodiments, the outer sides of the first shielding region 162 and the second shielding region 164 further include doped regions of the first conductivity type (N-type) (not shown), which are arranged corresponding to the first shielding region 162 and the second shielding region 164. The length, spacing, and interleaving distance of the doped regions of the first conductivity type (N-type) with respect to the first shielding region 162 and the second shielding region 164 can be configured according to actual needs to adjust the on-resistance and breakdown voltage of the power semiconductor device 100.
[0032] In other embodiments, a doped region (not shown) having the first conductivity type (N-type) is further included between the first shielding region 162 and the third shielding region 166 and between the second shielding region 164 and the third shielding region 166 .
[0033] Figures 2 to 6 for Figure 1 1 is a cross-sectional view of an intermediate step in a method for manufacturing a power semiconductor device 100. The connection relationship, materials, and functions of the components already described will not be repeated, but will be explained first.
[0034] See Figure 2The method for manufacturing the power semiconductor device 100 begins by providing an epitaxial layer 130 on a base layer 120. Next, a first trench TR1 is formed in the epitaxial layer 130. The step of forming the first trench TR1 may include patterning a photoresist layer (not shown), etching a mask layer 200 through the photoresist layer, and forming the first trench TR1 using the pattern of the mask layer 200. The mask layer 200 may be made of, for example, tetraethoxysilane (TEOS). Next, an implantation is performed toward the first sidewalls 192, the second sidewalls 194, and the bottom in areas corresponding to the first shielding region 162, the second shielding region 164, and the third shielding region 166 to form an electric field shielding region 160 having a second conductivity type (P-type). The method for manufacturing the power semiconductor device 100 continues by forming the source / drain doped region 150 in the epitaxial layer 130 adjacent to the upper portion of the trench sidewalls 190.
[0035] The manufacturing method of the power semiconductor device 100 continues by forming a first gate oxide layer 172 in the first trench TR1. The first gate oxide layer 172 has a first thickness T1. The first gate oxide layer 172 covers the first sidewall 192, the second sidewall 194, and the bottom of the first trench TR1. In one embodiment, the first gate oxide layer 172 is formed by thermal oxidation at a temperature of 1000 to 1600 degrees Celsius. In another embodiment, the first gate oxide layer 172 is formed by atomic layer deposition (ALD) of silicon dioxide.
[0036] See Figure 3 The manufacturing method of the power semiconductor device 100 continues with filling the polysilicon material 140M in the first trench TR1 (see Figure 2 ) and covers the first gate oxide layer 172 and the mask layer 200. The polysilicon material 140M is formed by a low pressure chemical vapor deposition (LPCVD) process.
[0037] See Figure 4 The manufacturing method of the power semiconductor device 100 continues with forming another mask layer 300 on the polysilicon material 140M. The material of the mask layer 300 is the same as that of the mask layer 200.
[0038] See Figure 5 The manufacturing method of the power semiconductor device 100 continues with forming a photoresist layer 400 to pattern the mask layer 300 . The polysilicon material 140M is patterned through the mask layer 300 .
[0039] See Figure 6The manufacturing method of the power semiconductor device 100 continues with forming the extension structure 146 that electrically connects the polysilicon material 140M to the source metal 180. The photoresist layer 400 is then removed.
[0040] See Figure 1 and Figure 6 The manufacturing method of the power semiconductor device 100 continues with etching the polysilicon material 140M (see Figure 5 ) to form the first gate 142. The manufacturing method of the power semiconductor device 100 subsequently includes patterning the mask layer 200 so that the mask layer 200 after etching has a tilt angle. For example, the tilt angle is approximately 15 degrees relative to the vertical direction, but the present disclosure is not limited to this. The manufacturing method of the power semiconductor device 100 continues to form the second trench TR2. The step of forming the second trench TR2 includes removing the epitaxial layer 130 of the first sidewall 192 and the second sidewall 194 located on the upper portion of the trench sidewall 190 through the mask layer 200 having the tilt angle to form the third sidewall 196 and the fourth sidewall 198. This step is also equivalent to removing a portion of the epitaxial layer 130 located above the first shielding area 162 and the second shielding area 164.
[0041] The manufacturing method of the power semiconductor device 100 continues by forming a second gate oxide layer 174 in the second trench TR2. The second gate oxide layer 174 is located at least on the third sidewall 196 and the fourth sidewall 198. The portion of the second gate oxide layer 174 located on the third sidewall 196 and the fourth sidewall 198 has a second thickness T2, which is less than the first thickness T1. The second gate oxide layer 174 is also located above the first gate 142 to connect to the first gate oxide layer 172. By providing gate oxide layers 170 with different thicknesses, the breakdown voltage can be increased.
[0042] The manufacturing method of the power semiconductor device 100 continues by forming a second gate 144 in the second trench TR2. This step may include first forming polysilicon material using a low-pressure chemical vapor deposition (LPCVD) process, and then removing the portion outside the second trench TR2 using etching or chemical mechanical polishing. The direction and angle of the channel region 156 are determined by the third sidewall 196 and the fourth sidewall 198.
[0043] The above steps are equivalent to forming the gate oxide layer 170 in the first trench TR1 and the second trench TR2 and forming the split gate 140 in the first trench TR1 and the second trench TR2 . Finally, a source metal 180 is formed on the epitaxial layer 130 and the split gate 140 .
[0044] In summary, a semiconductor device with a trench-type split gate makes the channel region vertical, thereby increasing the current density. The direction and angle of the channel region can be determined by the sidewalls of the trench that accommodates the second gate. By providing an electric field shielding region, the strong electric field in the vertical power semiconductor device can be shielded. By providing gate oxide layers with different thicknesses and providing a split gate, the breakdown voltage can be increased. The present disclosure can integrate the steps of forming a channel region with a specific angle, gate oxide layers with different thicknesses, and a split gate to optimize the process of high-power semiconductor devices. The doping concentration and area size of the electric field shielding region can be varied to adjust the on-resistance and breakdown voltage.
[0045] Although the present invention has been disclosed above in terms of embodiments, this is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0046]
Explanation of symbols
[0047] 100: Power semiconductor device
[0048] 110: Drain metal
[0049] 120: basal layer
[0050] 130: epitaxial layer
[0051] 140: Split Gate
[0052] 140M: Polysilicon material
[0053] 142: first gate
[0054] 144: Second gate
[0055] 146: Extended structure
[0056] 150: Source / drain doping region
[0057] 152: Source region
[0058] 154: Trap
[0059] 160: Electric field shielding area
[0060] 162: First sheltered area
[0061] 164: Second sheltered area
[0062] 166: Third Shelter Area
[0063] 170: Gate oxide layer
[0064] 172: first gate oxide layer
[0065] 174: Second gate oxide layer
[0066] 180: Source Metal
[0067] 190: Groove sidewall
[0068] 192: first side wall
[0069] 194: Second side wall
[0070] 196: Third side wall
[0071] 198: Fourth side wall
[0072] 200,300: mask layer
[0073] 400: Photoresist layer
[0074] W1: first width
[0075] W2: Second width
[0076] T1: First thickness
[0077] T2: Second thickness
[0078] D1: First horizontal
[0079] TR1: First groove
[0080] TR2: Second groove
[0081] L1: First distance
[0082] L2: Second distance.
Claims
1. A power semiconductor device, characterized in that: Include: drain metal; a base layer located on the drain metal; an epitaxial layer located on the base layer and having a first conductivity type; A split gate is located in the epitaxial layer, the split gate includes a first gate and a second gate, and the second gate is located above the first gate; an electric field shielding region located in the epitaxial layer and at least surrounding the first gate and having a second conductivity type; a gate oxide layer located between the split gate and the epitaxial layer; as well as The source metal is located on the epitaxial layer.
2. The power semiconductor device according to claim 1, wherein: The first gate and the second gate are separated from each other, and the first gate is electrically connected to the source metal.
3. The power semiconductor device according to claim 1 or 2, characterized in that: The electric field shielding region includes a first shielding region, a second shielding region and a third shielding region, and a vertical projection of the second gate on the base layer overlaps with vertical projections of the first shielding region and the second shielding region on the base layer.
4. The power semiconductor device according to claim 1, wherein: Also includes: a source / drain doped region located in the epitaxial layer adjacent to the second gate; A first gate oxide layer is located between the electric field shielding region and the first gate; and The second gate oxide layer is located between the source / drain doping region and the second gate.
5. The power semiconductor device according to claim 4, wherein: The second thickness of the second gate oxide layer is smaller than the first thickness of the first gate oxide layer.
6. A method for manufacturing a power semiconductor device, characterized in that: Include: forming an epitaxial layer on the base layer, wherein the epitaxial layer has a first conductivity type; forming a first trench in the epitaxial layer to form trench sidewalls; Implanting the trench sidewall to form an electric field shielding region, wherein the electric field shielding region has the second conductivity type and surrounds at least a lower portion of the trench sidewall; expanding an upper portion of the trench sidewall to form a second trench; forming a gate oxide layer in the first trench and the second trench; as well as A split gate is formed in the first trench and the second trench.
7. The method for manufacturing a power semiconductor device according to claim 6, wherein: The gate oxide layer is formed in the first trench and the second trench, comprising: forming a first gate oxide layer in the first trench; and After forming the second trench, a second gate oxide layer is formed in the second trench.
8. The method for manufacturing a power semiconductor device according to claim 7, wherein: The gate oxide layer is formed in the first trench and the second trench, comprising: The second thickness of the second gate oxide layer is made smaller than the first thickness of the first gate oxide layer.
9. The method for manufacturing a power semiconductor device according to claim 7, wherein: The split gate is formed in the first trench and the second trench, comprising: After forming the first gate oxide layer in the first trench, forming a first gate in the first gate oxide layer; and After forming the second gate oxide layer in the second trench, a second gate is formed on the first gate.
10. The method for manufacturing a power semiconductor device according to claim 9, wherein: The step of enlarging the upper portion of the trench sidewall to form the second trench comprises: Before forming the second gate on the first gate, a portion of the epitaxial layer located at the upper portion adjacent to the trench sidewall is removed, so that the second width of the second trench is greater than the first width of the first trench.