Method for forming semiconductor structure, semiconductor structure and electronic device

Abstract

The invention discloses a method for forming a semiconductor structure, the semiconductor structure and an electronic device, and the method comprises the steps: removing a part of thickness of a second semiconductor material from a second fin structure through employing a first wet etching technology, forming a first oxidation layer on the surface of a first fin structure, and adjusting the thickness of the first oxidation layer on the surface of the first fin structure, and a second semiconductor material which is located below the first oxide layer and has a partial thickness is removed from the adjusted first fin structure by adopting a second wet etching process, so that the etching rate of the second fin structure can be regulated and controlled by utilizing the first wet etching process. And the etching rate of the second wet etching process on the first fin structure is regulated and controlled by changing the thickness of the first oxide layer, so that independent controllable adjustment of the etching amount and the etching selection ratio of the first fin structure and the second fin structure is realized, namely, the process flexibility of the semiconductor structure is improved; and good roughness of the surface of the fin structure can be well ensured, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. Background Art

[0002] As semiconductor device sizes continue to shrink, in order to reduce short-channel effects (SCE) and improve semiconductor device performance, semiconductor processes are gradually transitioning from planar MOSFETs to more efficient three-dimensional transistors, such as fin field-effect transistors (FinFETs). Compared to planar MOSFETs, the gate structure in FinFETs has better control over the channel and can effectively suppress short-channel effects.

[0003] However, when the FinFET structure includes fins formed from two different semiconductor materials, due to the differences in the oxidation properties of the two semiconductor materials (such as silicon and silicon germanium), the formation method of the FinFET structure in the related art not only has poor flexibility, but also cannot ensure that the fin surface has good roughness, resulting in poor performance of the semiconductor structure. Summary of the Invention

[0004] In order to solve the problems of the prior art, the embodiments of the present application provide a method for forming a semiconductor structure, a semiconductor structure, and an electronic device. The technical solution is as follows:

[0005] In one aspect, a method of forming a semiconductor structure is provided, comprising:

[0006] Providing a substrate, on which a first fin structure and a second fin structure are separately disposed, wherein a material forming the first fin structure includes a first semiconductor material, a material forming the second fin structure includes a second semiconductor material, and an oxidation rate of the first semiconductor material is lower than an oxidation rate of the second semiconductor material;

[0007] Using a first wet etching process to remove a portion of the second semiconductor material from the second fin structure, and forming a first oxide layer on the surface of the first fin structure;

[0008] adjusting the thickness of the first oxide layer on the first fin structure;

[0009] A second wet etching process is used to remove a portion of the first semiconductor material below the first oxide layer from the adjusted first fin structure.

[0010] In an exemplary embodiment, adjusting the thickness of the first oxide layer on the first fin structure includes:

[0011] The first oxide layer on the first fin structure is etched using an acidic solution.

[0012] In an exemplary embodiment, the acidic solution is dilute hydrofluoric acid, and the dilution ratio of the dilute hydrofluoric acid is 100:1 to 1000:1.

[0013] In an exemplary embodiment, the etching process lasts for 0 to 60 seconds.

[0014] In an exemplary embodiment, the removing a portion of the second semiconductor material from the second fin structure by using a first wet etching process and forming a first oxide layer on the surface of the first fin structure includes:

[0015] performing an oxidation treatment on the substrate using an oxidizing solution, wherein the oxidation treatment oxidizes a portion of the thickness of the second semiconductor material on the surface of the second fin structure to form a second oxide layer, and oxidizes a portion of the thickness of the first semiconductor material on the surface of the first fin structure to form the first oxide layer; the oxidation rate of the second semiconductor material by the oxidizing solution is greater than the oxidation rate of the first semiconductor material;

[0016] The substrate after the oxidation treatment is cleaned, wherein the cleaning treatment removes the second oxide layer and retains the first oxide layer.

[0017] In an exemplary embodiment, a ratio of an oxidation rate of the second semiconductor material by the oxidizing solution to an oxidation rate of the first semiconductor material by the oxidizing solution is greater than 6.

[0018] In an exemplary embodiment, the oxidizing solution is a hydrogen peroxide solution and / or an ozonated deionized water solution.

[0019] In an exemplary embodiment, the mass concentration of the oxidant in the oxidizing solution is 30 ppm to 90 ppm.

[0020] In an exemplary embodiment, removing the second thickness of the first semiconductor material located under the first oxide layer from the adjusted first fin structure using the second wet etching process includes:

[0021] The adjusted first fin structure is etched using an alkaline solution, and the etching rate of the alkaline solution on the first semiconductor material is Furthermore, the etching rate of the alkaline solution on the first semiconductor material is greater than the etching rate on the second semiconductor material.

[0022] In an exemplary embodiment, a ratio of an etching rate of the alkaline solution on the first semiconductor material to an etching rate of the alkaline solution on the second semiconductor material is in a range of 1.5 to 3.2.

[0023] In an exemplary embodiment, the alkaline solution includes tetramethylammonium hydroxide; the mass concentration of the tetramethylammonium hydroxide in the alkaline solution is 1% to 10%.

[0024] In an exemplary embodiment, the method further comprises:

[0025] The first wet etching process and / or the second wet etching process are alternately performed until a critical dimension of the first fin structure reaches a first target critical dimension and a critical dimension of the second fin structure reaches a second target critical dimension.

[0026] In an exemplary embodiment, providing a substrate includes:

[0027] Providing a semiconductor substrate, the semiconductor substrate comprising a first device region and a second device region, wherein the first device region and the second device region are implanted with different types of trapped ions;

[0028] forming a first semiconductor material layer on the first device region of the semiconductor substrate, and forming a second semiconductor material layer on the second device region of the semiconductor substrate;

[0029] Etching the first semiconductor material layer, the second semiconductor material layer and a portion of the semiconductor substrate to form a first initial fin structure in the first device region and a second initial fin structure in the second device region;

[0030] An isolation layer is formed on the remaining semiconductor substrate, wherein a top surface of the isolation layer is lower than top surfaces of the first initial fin structure and the second initial fin structure; wherein a portion of the first initial fin structure protruding from the isolation layer is the first fin structure, and a portion of the second initial fin structure protruding from the isolation layer is the second fin structure.

[0031] In an exemplary embodiment, p-type well ions are implanted into the first device region, n-type well ions are implanted into the second device region, the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium.

[0032] In an exemplary embodiment, the concentration of germanium atoms in the silicon germanium is 20% to 40%.

[0033] On the other hand, a semiconductor structure is provided. The semiconductor structure is formed using any of the aforementioned methods for forming a semiconductor structure.

[0034] On the other hand, an electronic device is provided, comprising a semiconductor structure formed by any one of the aforementioned methods for forming a semiconductor structure.

[0035] The embodiment of the present application adopts a first wet etching process to remove a portion of the thickness of the second semiconductor material from the second fin structure, and forms a first oxide layer on the surface of the first fin structure. Then, the thickness of the first oxide layer on the surface of the first fin structure is adjusted, and a second wet etching process is adopted to remove a portion of the thickness of the second semiconductor material located under the first oxide layer from the adjusted first fin structure. Thus, the etching rate of the second fin structure can be regulated by the first wet etching process, and the etching rate of the first fin structure by the second wet etching process can be regulated by the change in the thickness of the first oxide layer, thereby achieving separate and controllable adjustment of the etching amount and etching selectivity of the first fin structure and the second fin structure, so that the first fin structure and the second fin structure on the substrate can simultaneously reach their respective target critical dimensions, thereby improving the process flexibility of the semiconductor structure, and also ensuring that the surface of the fin structure has good roughness, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 is a schematic diagram of a trimming process based on wet etching in the prior art;

[0038] Figures 2 to 7 This is a structural diagram of a process for forming a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 8 This is a comparative example of regulating the Si / SiGe etching selectivity ratio based on the formation method of the embodiment of the present application;

[0040] Figure 9 This is a schematic diagram of a semiconductor structure formed by a formation method according to an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. And when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part is present in the present application.

[0044] When a FinFET structure includes fins formed from two different semiconductor materials, due to the differences in the oxidation properties of the two semiconductor materials (such as silicon and silicon germanium), it is usually necessary to selectively etch the fins of the two different semiconductor materials to achieve fin trimming after etching to form the fins and forming shallow trench isolation (STI) to isolate adjacent fins.

[0045] During the development of the present invention, the inventors discovered that dry-etching-based trimming processes suffer from issues such as difficulty controlling the etch selectivity, complex and difficult-to-remove byproducts, and poor fin surface roughness at high etch volumes, leading to poor semiconductor structure performance. Furthermore, in wet-etching-based trimming processes, commonly used wet etchants are unable to control the etch selectivity and are unable to meet the requirements for simultaneously achieving the target critical dimensions for fins of two different semiconductor materials, resulting in limited process flexibility.

[0046] like Figure 1 The schematic diagram shows a conventional wet-etching trimming process, wherein a first fin 110 and a second fin 120 are formed on a substrate 100 to be processed. The first fin 110 is made of silicon, and the second fin 120 is made of silicon-germanium. Substrate 110 is treated with a weakly alkaline solution, and the first and second fins 110, 120 are simultaneously etched. This weakly alkaline solution has an unadjustable 3:1 etching selectivity for silicon and silicon-germanium. If the critical dimensions of the first and second fins 110, 120 on substrate 100 differ, selective etching of silicon and silicon-germanium to achieve the process requirement of simultaneously achieving their respective target critical dimensions will not be achieved.

[0047] Based on this, an embodiment of the present application provides a method for forming a semiconductor structure, which uses a first wet etching process to remove a portion of the thickness of the second semiconductor material from the second fin structure and form a first oxide layer on the surface of the first fin structure. Then, the thickness of the first oxide layer on the surface of the first fin structure is adjusted, and a second wet etching process is used to remove a portion of the thickness of the second semiconductor material located under the first oxide layer from the adjusted first fin structure, so that the first wet etching process can be used to regulate the etching rate of the second fin structure, and the change in the thickness of the first oxide layer can be used to regulate the etching rate of the first fin structure by the second wet etching process, thereby achieving separate and controllable adjustment of the etching amount and etching selectivity of the first fin structure and the second fin structure, so that the first fin structure and the second fin structure on the substrate can simultaneously reach their respective target critical dimensions, that is, the process flexibility of the semiconductor structure is improved, and the process characteristics of wet etching can be well utilized to ensure that the surface of the fin structure has good roughness, thereby improving the performance of the semiconductor structure.

[0048] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0049] Figures 2 to 7 This is a structural schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present application.

[0050] See also Figure 2 , providing a substrate 200, on which a first fin structure 210 and a second fin structure 220 are separately arranged, the forming material of the first fin structure 210 includes a first semiconductor material, the forming material of the second fin structure 220 includes a second semiconductor material, and the oxidation rate of the first semiconductor material is lower than the oxidation rate of the second semiconductor material.

[0051] Specifically, the first fin structure 210 can be disposed in the first device region 201 of the substrate 200, and the second fin structure 220 can be disposed in the second device region 202 of the substrate 200. Among them, the first device region 201 is used to form transistors of a first type, and the second device region 202 is used to form transistors of a second type, where the first type is different from the second type. The first semiconductor material is adapted to the transistors of the first type, and the second semiconductor material is adapted to the transistors of the second type.

[0052] In the embodiments of the present application, the transistors of the first type can be NMOS transistors, the transistors of the second type can be PMOS transistors, the first semiconductor material can include silicon, and the second semiconductor material can include silicon germanium Si

[0057] , Ge x , where the concentration of Ge atoms can be 20% to 40% (0.2 < x < 0.4). By introducing the silicon germanium material to form the second fin structure, a higher carrier (hole) mobility can be provided, which is beneficial to improving the performance of the semiconductor structure.

[0053] It can be understood that Figure 2 The numbers of the first fin structure 210 and the second fin structure 220 shown are only examples. In practical applications, there can be one or more first fin structures 210 spaced apart on the substrate 200, and there can also be one or more second fin structures 220 spaced apart on the substrate 200. Electrical insulation between adjacent fin structures can be achieved through the insulating material in the substrate 200.

[0054] Based on this, in some exemplary embodiments, the method of the embodiments of the present application can further include the process of forming the above-mentioned substrate 200. The following will be combined with [[ID=1​​​​​​​​​​​The semiconductor substrate 300 may be a bulk semiconductor or a silicon-on-insulator (SOI) substrate, etc., and may be doped (e.g., doped with a p-type dopant or an n-type dopant) or undoped. The SOI substrate is a semiconductor material layer formed on an insulator layer, which may be, for example, a buried oxide (BOX) layer or a silicon oxide layer, etc., and the insulator layer is disposed on a silicon substrate or a glass substrate. In a specific implementation, the semiconductor material of the semiconductor substrate 300 may include one or more of silicon, germanium, a compound semiconductor, and an alloy semiconductor, wherein the compound semiconductor may be one or more of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, and the alloy semiconductor may be one or more of silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and gallium indium arsenic phosphide.

[0058] Continue to see Figure 3a A first semiconductor material layer 310 is formed on the first device region 301 of the semiconductor substrate 300 , and a second semiconductor material layer 320 is formed on the second device region 302 of the semiconductor substrate 300 .

[0059] The thickness of the first semiconductor material layer 310 and the thickness of the second semiconductor material layer 320 may be the same or different. The first semiconductor material layer 310 may be formed first, and then the second semiconductor material layer 320, or the second semiconductor material layer 320 may be formed first, and then the first semiconductor material layer 310. The present embodiment does not limit the order of forming the first and second semiconductor material layers.

[0060] Taking the example of first forming the first semiconductor material layer 310 and then forming the second semiconductor material layer 320, an initial first semiconductor material layer (not shown in the figure) extending from the first device area 301 to the second device area 302 can be first deposited on the semiconductor substrate 300, and then a patterned photoresist layer (not shown in the figure) is formed on the initial first semiconductor material layer, and the patterned photoresist layer has an opening exposing the second device area 302. The initial first semiconductor material layer on the second device area 302 is then etched away using the patterned photoresist layer as a mask to expose the semiconductor substrate 300. Then, a second semiconductor material layer 320 can be formed on the second device area 302 of the semiconductor substrate 300, and then the remaining patterned photoresist layer is removed, where the remaining unetched initial first semiconductor material layer forms the first semiconductor material layer 310.

[0061] See also Figure 3bThe first semiconductor material layer 310 , the second semiconductor material layer 320 and a portion of the semiconductor substrate 300 are etched to form a first initial fin structure 330 in the first device region 301 and a second initial fin structure 340 in the second device region 302 .

[0062] The first initial fin structure 330 and the second initial fin structure 340 each include a bottom portion 303 formed by etching a portion of the semiconductor substrate 300 .

[0063] Continue to see Figure 3b , an isolation layer 350 is formed on the remaining semiconductor substrate, wherein the top surface of the isolation layer 350 is lower than the top surface of the first initial fin structure 330 and the second initial fin structure 340, wherein the portion of the first initial fin structure protruding from the isolation layer 350 is the first fin structure 210, and the portion of the second initial fin structure protruding from the isolation layer 350 is the second fin structure 220, thereby obtaining the aforementioned base 200.

[0064] Specifically, the isolation layer 350 is formed on the semiconductor substrate 300 between the adjacent first initial fin structure 330 and the second initial fin structure 340, and covers part of the sidewall surfaces of the first initial fin structure 330 and the second initial fin structure 340. The isolation layer 350 is formed of an insulating material such as silicon oxide or silicon nitride.

[0065] See also Figure 4 , a first wet etching process is used to remove a portion of the second semiconductor material ( Figure 4 A first oxide layer 410 is formed on the surface of the first fin structure 210 .

[0066] Among them, the first wet etching process is mainly used to etch the second fin structure 220 to remove part of the thickness of the second semiconductor material and form a first oxide layer 410 on the surface of the first fin structure 210. The first oxide layer 410 can provide a basis for subsequent regulation of the etching rate of the first fin structure 210.

[0067] In a specific implementation, the etching amount of the second semiconductor material of the second fin structure 220 in the first wet etching process can be controlled by adjusting the concentration of the wet etchant and the etching time in the first wet etching process.

[0068] In some exemplary embodiments, a first wet etching process is used to remove a portion of the second semiconductor material from the second fin structure 220 and form a first oxide layer 410 on the surface of the first fin structure 210. Figure 5a and Figure 5b shown.

[0069] See also Figure 5aThe substrate 200 is oxidized using an oxidizing solution, which oxidizes the second semiconductor material partially on the surface of the second fin structure 220 to form a second oxide layer 510, and oxidizes the first semiconductor material partially on the surface of the first fin structure 210 to form a first oxide layer 410.

[0070] The oxidation rate of the oxidizing solution on the second semiconductor material is greater than the oxidation rate on the first semiconductor material, so that the first wet etching process can be mainly used to etch the second semiconductor material.

[0071] Exemplarily, the ratio of the oxidation rate of the oxidizing solution on the second semiconductor material to the oxidation rate on the first semiconductor material is greater than 6, and the oxidation treatment time exceeds 30 seconds, thereby ensuring a high etching selectivity ratio between the second semiconductor material and the first semiconductor material in the first wet etching process.

[0072] For example, the oxidizing solution may be a hydrogen peroxide solution and / or an ozonated deionized water solution.

[0073] For example, the mass concentration of the oxidant in the oxidizing solution may be 30 ppm to 90 ppm. Taking the oxidizing solution as an ozonated deionized water solution as an example, the mass concentration of ozone in the ozonated deionized water solution may be 85 ppm.

[0074] See also Figure 5b The substrate after oxidation treatment is cleaned, and the cleaning process removes the second oxide layer 510 and retains the first oxide layer 410.

[0075] In a specific implementation, the cleaning agent used in the cleaning process can completely dissolve the oxide of the second oxide layer 510, but is difficult to dissolve the oxide of the first oxide layer 410. Therefore, the second oxide layer 510 can be removed by rinsing the substrate after oxidation treatment with the cleaning agent, while retaining the first oxide layer 410.

[0076] For example, the first semiconductor material is silicon and the second semiconductor material is silicon germanium Si. 1-x Ge x In this case, the first oxide layer 410 is Si-O oxide, and the second oxide layer 510 is high-valent Ge-O oxide. Considering that high-valent Ge-O oxide is easily soluble in water, while Si-O oxide is difficult to dissolve in water, deionized water can be used to rinse the oxidized substrate, thereby removing the second oxide layer 510 to remove the second semiconductor material of the partial thickness on the surface of the second fin structure 220, and retaining the first oxide layer 410 on the surface of the first fin structure 210.

[0077] It is understandable that the thickness of the second oxide layer 510 can be adjusted by changing the concentration of the oxidizing solution and the oxidation treatment time, thereby achieving the independent adjustment of the removal amount of the second semiconductor material, such as silicon germanium.

[0078] See also Figure 6 , the thickness of the first oxide layer 410 on the first fin structure 210 is adjusted to obtain an adjusted first oxide layer 610 .

[0079] Specifically, adjusting the thickness of the first oxide layer 410 may be controlling the amount of reduction in the thickness of the first oxide layer 410 according to the amount of etching of the first semiconductor material in the next step.

[0080] Exemplarily, adjusting the thickness of the first oxide layer 410 on the first fin structure 210 may include etching the first oxide layer 410 on the first fin structure 210 using an acidic solution. The duration of the etching process may be understood as the thickness adjustment duration.

[0081] The acidic solution does not cause damage to the exposed second semiconductor material during the etching process of the first oxide layer 410. Exemplarily, the acidic solution is a strong acid solution, such as dilute hydrofluoric acid, with a dilution ratio of 100:1 to 1000:1. Using dilute hydrofluoric acid can avoid the inability to effectively adjust the thickness of the first oxide layer 410 due to an excessively high etching rate.

[0082] The thickness adjustment time can be determined based on the etching rate requirement for the first semiconductor material of the first fin structure 210 in the subsequent second wet etching process. Generally, the greater the etching rate requirement for the first semiconductor material in the subsequent second wet etching process, the longer the thickness adjustment time can be, so that the thickness of the adjusted first oxide layer 610 is smaller. Conversely, the smaller the etching rate requirement for the first semiconductor material in the subsequent second wet etching process, the shorter the thickness adjustment time can be, so that the thickness of the first oxide layer 410 is reduced less. For example, the thickness adjustment time can range from 0 to 60 seconds.

[0083] See also Figure 7 , a second wet etching process is used to remove a portion of the first semiconductor material ( Figure 7 The part shown by the dotted box).

[0084] The etchant in the second wet etching process is suitable for etching the first semiconductor material and does not etch the adjusted first oxide layer 610 .

[0085] Specifically, if the etchant of the second wet etching process wants to etch the first semiconductor material in the adjusted first fin structure 210, it needs to first penetrate the first oxide layer 610 on the surface of the adjusted first fin structure 210, and then the thickness of the first oxide layer 610 will affect the etching rate of the etchant on the first semiconductor material. Then, by changing the thickness of the first oxide layer 610, the purpose of adjusting the etching rate of the first fin structure 210 can be achieved, and the etching amount of the first semiconductor material can be adjusted separately.

[0086] In some exemplary embodiments, removing a portion of the thickness of the first semiconductor material located below the first oxide layer 610 from the adjusted first fin structure 210 using the second wet etching process may include: etching the adjusted first fin structure using an alkaline solution, wherein the alkaline solution has an etching rate of the first semiconductor material of Furthermore, the etching rate of the alkaline solution on the first semiconductor material is greater than the etching rate on the second semiconductor material.

[0087] Among them, the etching rate of the alkaline solution on the first semiconductor material is The alkaline solution is weakly alkaline, thereby preventing the adverse effect on the roughness of the surface of the final first fin structure caused by excessively high etching rate of the first semiconductor material due to excessive alkalinity.

[0088] The alkaline solution has a higher etching rate for the first semiconductor material than for the second semiconductor material, thereby achieving a high selectivity for the first semiconductor material to the second semiconductor material in the second wet etching process. For example, the ratio of the etching rate of the alkaline solution for the first semiconductor material to the etching rate of the second semiconductor material, i.e., the etching selectivity, ranges from 1.5 to 3.2. A specific etching selectivity can be achieved based on actual needs by varying the duration of the acidic solution treatment of the substrate to adjust the remaining thickness of the first oxide layer.

[0089] Exemplarily, the alkaline solution may include tetramethylammonium hydroxide, for example, a mixed solution of tetramethylammonium hydroxide / water / additive. The mass concentration of tetramethylammonium hydroxide in the alkaline solution is 1% to 10%. It is understood that the etching rate can also be controlled by adjusting the concentration and temperature of the tetramethylammonium hydroxide in the alkaline solution.

[0090] In some exemplary embodiments, in order to make the surface of the fin structure of the semiconductor structure have better roughness, the first wet etching process and the second wet etching process can be performed multiple times, wherein the number of times the first wet etching process is performed can be determined based on the difference between the second target critical size of the second fin structure and its initial critical size and the amount of the second semiconductor material removed by a single execution of the first wet etching process; similarly, the number of times the second wet etching process is performed can be determined based on the difference between the first target critical size of the first fin structure and its initial critical size and the amount of the first semiconductor material removed by a single execution of the second wet etching process. Wherein, the initial critical size refers to Figure 2 The critical dimensions of the fin structure on the substrate 200 are shown in FIG.

[0091] The amount of the second semiconductor material removed during a single execution of the first wet etching process can be controlled by combining the concentration of the oxidizing solution and the oxidation time. For example, the mass concentration of the oxidizing solution is 85 ppm, and the oxidation time can be greater than or equal to 30 seconds. The amount of the first semiconductor material etched during a single execution of the second wet etching process can be controlled by adjusting the thickness of the first oxide layer, and the thickness of the first oxide layer can be adjusted by the duration of the dilute hydrofluoric acid etching treatment, i.e., the thickness adjustment time. For example, the thickness adjustment time can be 0 to 60 seconds. Of course, the concentration and temperature of the weakly alkaline solution can also be combined to assist in controlling the amount of etching of the first semiconductor material.

[0092] Based on this, the method of the embodiment of the present application may further include: alternatingly performing a first wet etching process and / or a second wet etching process until the critical dimension of the first fin structure reaches a first target critical dimension and the critical dimension of the second fin structure reaches a second target critical dimension. During the second wet etching process, since the first semiconductor material is removed from the adjusted first fin structure, the thickness of the first oxide layer on the first fin structure may be adjusted before the second wet etching process to control the amount of the first semiconductor material removed.

[0093] See also Figure 8 , which shows a comparative example of regulating the Si / SiGe etching selectivity ratio based on the formation method of an embodiment of the present application, wherein Si is an example of the first semiconductor material of the embodiment of the present application, and SiGe is an example of the second semiconductor material of the embodiment of the present application.

[0094] like Figure 8As shown in the figure, "w / o OZ / DHF" means that the first wet etching process and the dilute hydrofluoric acid treatment are not used, that is, in the absence of the first oxide layer (SiO2), the substrate is directly etched with a weak alkaline solution in the second wet etching process. At this time, the etching selectivity of the weak alkaline solution to Si / SiGe is 17.79 / 5.64=3.15; "OZ30s / DHF15s" means that in the first wet etching process, an ozonated deionized water solution is used for oxidation for 30 seconds, and dilute hydrofluoric acid is used to etch the first oxide layer on the first fin structure for 15 seconds, and then in the second wet etching process, the substrate is etched with a weak alkaline solution. In the wet etching process, a weak alkaline solution is used to etch the substrate. At this time, the etching selectivity of the weak alkaline solution to Si / SiGe is 15.97 / 6.06=2.64; "OZ30s / DHF10s" means that in the first wet etching process, an ozonated deionized water solution is used for oxidation for 30 seconds, and the first oxide layer on the first fin structure is etched for 10 seconds using dilute hydrofluoric acid. Then, in the second wet etching process, a weak alkaline solution is used to etch the substrate. At this time, the etching selectivity of the weak alkaline solution to Si / SiGe is 8.74 / 5.63=1.55. It can be seen that by changing the treatment time of the dilute hydrofluoric acid to change the thickness of the first oxide layer, the etching selectivity of the weak alkaline solution to Si / SiGe in the second wet etching process can be adjusted between 1.5 and 3.2.

[0095] In practical applications, after the critical dimension of the first fin structure reaches the first target critical dimension and the critical dimension of the second fin structure reaches the second target critical dimension, the first fin structure and the second fin structure can be post-cleaned based on the needs of the actual subsequent process to remove the remaining oxide layer on the first fin structure and the second fin structure, so as to obtain the following Figure 9 The semiconductor structure shown.

[0096] The above-mentioned technical scheme of the embodiment of the present application can realize the independent controllable adjustment of the etching amount and etching selectivity of germanium silicon and silicon. The etching amount control range for the critical size of the Si fin on the substrate is 1nm~5nm, and the etching amount control range for the critical size of the SiGe fin on the substrate is 1nm~5nm. Therefore, according to the different initial critical sizes of the fin structure on the substrate, the critical size of the Si fin corresponding to the NMOS transistor and the critical size of the SiGe fin corresponding to the PMOS transistor can simultaneously reach their respective target critical sizes, which improves the process flexibility of the semiconductor structure, and can also well ensure that the surface of the fin structure has good roughness, thereby improving the performance of the semiconductor structure.

[0097] Correspondingly, an embodiment of the present application further provides a semiconductor structure, which is formed based on any formation method of the embodiment of the present application.

[0098] Accordingly, an embodiment of the present application further provides an electronic device, which includes a semiconductor structure formed based on any formation method of the embodiment of the present application.

[0099] Because semiconductor structures have superior performance, the electronic device employing such a semiconductor structure correspondingly improves the performance of the electronic device. The electronic device may be any electronic product or device, such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigation system, camera, camcorder, voice recorder, MP3, MP4, PSP, or the like. It may also be an intermediate product incorporating the semiconductor structure, such as a device motherboard incorporating the semiconductor device.

[0100] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, on which a first fin structure and a second fin structure are separately disposed, wherein a material forming the first fin structure includes a first semiconductor material, a material forming the second fin structure includes a second semiconductor material, and an oxidation rate of the first semiconductor material is lower than an oxidation rate of the second semiconductor material; Using a first wet etching process to remove a portion of the second semiconductor material from the second fin structure, and forming a first oxide layer on the surface of the first fin structure; adjusting the thickness of the first oxide layer on the first fin structure; A second wet etching process is used to remove a portion of the first semiconductor material below the first oxide layer from the adjusted first fin structure.

2. The method according to claim 1, characterized in that The adjusting the thickness of the first oxide layer on the first fin structure includes: The first oxide layer on the first fin structure is etched using an acidic solution.

3. The method according to claim 2, characterized in that The acidic solution is dilute hydrofluoric acid, and the dilution ratio of the dilute hydrofluoric acid is 100:1 to 1000:

1.

4. The method according to claim 2, characterized in that The etching process lasts for 0 to 60 seconds.

5. The method according to claim 1, wherein The step of removing a portion of the second semiconductor material from the second fin structure by using a first wet etching process and forming a first oxide layer on the surface of the first fin structure includes: performing an oxidation treatment on the substrate using an oxidizing solution, wherein the oxidation treatment oxidizes a portion of the thickness of the second semiconductor material on the surface of the second fin structure to form a second oxide layer, and oxidizes a portion of the thickness of the first semiconductor material on the surface of the first fin structure to form the first oxide layer; the oxidation rate of the second semiconductor material by the oxidizing solution is greater than the oxidation rate of the first semiconductor material; The substrate after the oxidation treatment is cleaned, wherein the cleaning treatment removes the second oxide layer and retains the first oxide layer.

6. The method according to claim 5, characterized in that The ratio of the oxidation rate of the second semiconductor material by the oxidizing solution to the oxidation rate of the first semiconductor material by the oxidizing solution is greater than 6.

7. The method according to claim 6, characterized in that The oxidizing solution is a hydrogen peroxide solution and / or an ozonated deionized water solution.

8. The method according to claim 6, characterized in that The mass concentration of the oxidant in the oxidizing solution is 30 ppm to 90 ppm.

9. The method according to claim 1, characterized in that The step of removing the first semiconductor material having a second thickness located under the first oxide layer from the adjusted first fin structure by using a second wet etching process includes: The adjusted first fin structure is etched using an alkaline solution, and the etching rate of the alkaline solution on the first semiconductor material is Furthermore, the etching rate of the alkaline solution on the first semiconductor material is greater than the etching rate on the second semiconductor material.

10. The method according to claim 9, characterized in that The ratio of the etching rate of the alkaline solution on the first semiconductor material to the etching rate on the second semiconductor material is in a range of 1.5 to 3.

2.

11. The method according to claim 10, characterized in that The alkaline solution includes tetramethylammonium hydroxide; the mass concentration of the tetramethylammonium hydroxide in the alkaline solution is 1% to 10%.

12. The method according to claim 1, characterized in that The method further comprises: The first wet etching process and / or the second wet etching process are alternately performed until a critical dimension of the first fin structure reaches a first target critical dimension and a critical dimension of the second fin structure reaches a second target critical dimension.

13. The method according to claim 1, wherein The providing of a substrate comprises: Providing a semiconductor substrate, the semiconductor substrate comprising a first device region and a second device region, wherein the first device region and the second device region are implanted with different types of trapped ions; forming a first semiconductor material layer on the first device region of the semiconductor substrate, and forming a second semiconductor material layer on the second device region of the semiconductor substrate; Etching the first semiconductor material layer, the second semiconductor material layer and a portion of the semiconductor substrate to form a first initial fin structure in the first device region and a second initial fin structure in the second device region; An isolation layer is formed on the remaining semiconductor substrate, wherein a top surface of the isolation layer is lower than top surfaces of the first initial fin structure and the second initial fin structure; wherein a portion of the first initial fin structure protruding from the isolation layer is the first fin structure, and a portion of the second initial fin structure protruding from the isolation layer is the second fin structure.

14. The method according to claim 13, wherein: P-type well ions are implanted into the first device region, n-type well ions are implanted into the second device region, the first semiconductor material includes silicon, and the second semiconductor material includes silicon germanium.

15. The method according to claim 14, characterized in that The concentration of germanium atoms in the germanium silicon is 20% to 40%.

16. A semiconductor structure, characterized in that Formed by the method according to any one of claims 1 to 15.

17. An electronic device, characterized in that: The electronic device includes a semiconductor structure formed using the method of any one of claims 1 to 15 .

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