Multi-chip integrated photoelectric sensor, manufacturing method thereof and FT test method

Abstract

The invention discloses a multi-chip integrated photoelectric sensor, a manufacturing method thereof and an FT testing method, and belongs to the technical field of integrated circuits, the multi-chip integrated photoelectric sensor comprises an image sensor chip, the front surface of the image sensor chip is provided with a photosensitive area and an edge area, the photosensitive area is provided with a light-transmitting component used for filtering interference light, and the edge area is provided with a light-transmitting component used for filtering interference light. The edge area is provided with a plurality of front bonding pads for transmitting electric signals; a light-emitting area is arranged at the top of the light source chip, and a first bottom bonding pad and a second bottom bonding pad are arranged at the bottom of the light source chip and used for being communicated with the two front bonding pads of the image sensor chip respectively; and the RDL reconfiguration wiring layer penetrates through the image sensor chip so as to transmit an electric signal on the front surface of the image sensor chip to the back surface of the image sensor chip. The light source chip is directly bonded to the surface of the CMOS image sensor, so that the size of the product in the X, Y and Z directions is greatly reduced, and the requirement of a terminal product for the size is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a multi-chip integrated photoelectric sensor, a manufacturing method thereof, and an FT testing method. Background Art

[0002] Multi-chip integrated optical sensors, in addition to CIS (CMOS Image Sensor) image sensors, also integrate light source chips. Generally, this multi-chip integrated optical sensor uses a PCB substrate as a carrier board. The CIS chip and the light source chip are mounted on the PCB substrate through Die Bond (chip bonding). The pads of the CIS chip and the pads of the light source chip are connected to the pads of the PCB substrate through the Wire Bond process. Figure 1 The limitations of the conventional photoelectric sensor 100 are as follows: Since the PCB substrate 102 is used as a carrier with a certain thickness in the Z direction, and the carrier requires a metal plate and a protective layer, and the warping of the carrier needs to be considered to facilitate high yield and stability of mass production of the packaging process, the carrier must have a certain thickness support.

[0003] The Y direction is perpendicular to the paper surface. The PCB substrate 102 needs to consider the size of the light source chip 108, the size of the CIS chip 106, the wire bonding space of the Wire Bond 104, and the support of the optical packaging cover 103 in the X and Y directions.

[0004] Furthermore, the light source chip 108 and the CIS chip 106 are mostly standardized products and can only be packaged and integrated using the PCB substrate 102 as a carrier, and cannot be further miniaturized.

[0005] Figure 1 The provided packaging solution uses a PCB substrate 102 as a carrier board. After the packaging is completed, due to the varying degrees of warping of the entire board, the FT (Final Test) test usually involves first cutting the entire board into individual products, and then placing the individual products into a test socket for testing, resulting in relatively low test efficiency.

[0006] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0007] The object of the present invention is to provide a multi-chip integrated photoelectric sensor and a manufacturing method and an FT testing method thereof, so as to solve the problem that the multi-chip integrated optical sensor is difficult to meet the miniaturization requirements.

[0008] To solve the above technical problems, the present invention provides a multi-chip integrated photoelectric sensor, comprising: An image sensor chip, wherein the front surface of the image sensor chip has a photosensitive area and an edge area, the photosensitive area is provided with a light-transmitting member for filtering out interfering light, and the edge area is provided with a plurality of front pads, including a first front pad and a second front pad, for connecting to the bottom pad of the light source chip; a light source chip, wherein a light emitting area is provided on the top of the light source chip, and a first bottom solder pad and a second bottom solder pad are provided on the bottom of the light source chip, for respectively communicating with the first front solder pad and the second front solder pad of the image sensor; An RDL reconstruction wiring layer passes through the image sensor chip to transmit electrical signals from the front pad of the image sensor chip to the back pad; A cover structure is provided on the edge region and is used to protect the front surface of the image sensor chip.

[0009] Preferably, the first bottom pad surface is connected to the first front pad surface of the image sensor chip, the second bottom pad surface is connected to the second front pad surface of the image sensor chip, and the second front pad exports the electrical signal to the back side of the image sensor chip through a TSV (Through Silicon Via) process, and a BGA / LGA pad is formed on the back side of the image sensor chip.

[0010] Preferably, the end of the RDL reconstruction wiring layer located on the back side of the image sensor chip is connected to the BGA / LGA pad, and an internal insulation layer is also provided between the RDL reconstruction wiring layer and the image sensor chip, and the end of the RDL reconstruction wiring layer located on the back side of the image sensor chip is also covered with a surface insulation layer.

[0011] Preferably, the light-transmitting component is a filter or a lens, and the cover structure is a plurality of columns arranged on the edge area.

[0012] Preferably, an organic film is attached to the BGA / LGA pad.

[0013] A method for manufacturing a multi-chip integrated photoelectric sensor comprises the following steps: An image sensor chip and a light source chip are provided. The front surface of the image sensor chip has a photosensitive area and an edge area. The edge area is provided with a plurality of front pads, including a first front pad, a second front pad, and other front pads for connecting electrical signals. The top of the light source chip is provided with a light-emitting area, and the bottom has a first bottom pad and a second bottom pad. Connecting the first front pad and the second front pad of the image sensor chip to the first bottom pad and the second bottom pad of the light source chip to form an electrical signal connection between the two chips; A light-transmitting component is provided on the light-sensitive area for filtering out interfering light; Providing a carrier sheet, etching the carrier sheet to form an opening adapted to the photosensitive area and the light source chip, and pressing the side of the carrier sheet with the opening onto the front surface of the image sensor chip to form a cover structure; Thinning the back side of the image sensor chip to a desired thickness; A TSV process is used to form an RDL reconstruction wiring layer in the image sensor chip to transmit electrical signals from the front side of the image sensor chip to the back side.

[0014] Preferably, a first front pad, a second front pad and other metal layer pads are provided in the edge area, and Ag Paste (silver glue), ACA / ACP (anisotropic conductive adhesive) or ACF (anisotropic conductive film) is used through a chip bonding process, or SMT patch, and then a reflow process is performed to connect the first bottom pad, the second bottom pad and the first front pad, the second front pad of the image sensor chip to the corresponding connection.

[0015] Preferably, arranging a light-transmitting component on the photosensitive area includes: arranging a filter on the photosensitive area through a chip bonding process, or manufacturing a lens on the photosensitive area.

[0016] Preferably, forming an RDL reconstruction wiring layer in the image sensor chip using a TSV process includes: forming through-silicon vias (TSVs) on the image sensor chip using photolithography and etching processes; forming an internal insulating layer within the through silicon via and on the back side of the image sensor chip; forming an RDL reconstruction wiring layer in the through silicon via by adopting a physical vapor deposition process; Continuing to cover the back side of the image sensor chip with a surface insulating layer; A plurality of BGA / LGA pads are formed on the back side of the image sensor chip by adopting a BGA / LGA process.

[0017] A FT test method for a multi-chip integrated photoelectric sensor is used to perform FT testing on the multi-chip integrated photoelectric sensor as described above, comprising the following steps: Providing a wafer containing a packaged image sensor chip, and peeling the wafer from the organic film; The wafer is transferred to the carrier of the FT test platform, and the BGA / LGA pads of the packaged image sensor chip are brought into contact with the test probes on the FT test platform. A multi-chip simultaneous measurement method can be adopted to connect the front surface of the packaged image sensor chip to the optical test calibration to test the communication, power consumption and performance parameters of the photoelectric sensor.

[0018] The multi-chip integrated photoelectric sensor provided by the present invention significantly reduces the product's dimensions in the X and Y directions by directly bonding the light source chip to the surface of the CMOS image sensor, thereby reducing the required planar area of ​​the product. Furthermore, because the use of a PCB substrate is eliminated, the dimension in the Z direction is also reduced accordingly, thereby reducing the thickness of the entire product and meeting the size requirements of the end product.

[0019] The manufacturing method of the multi-chip integrated photoelectric sensor provided by the present invention and the multi-chip integrated photoelectric sensor provided by the present invention belong to the same inventive concept. Therefore, the manufacturing method of the multi-chip integrated photoelectric sensor provided by the present invention has at least all the advantages of the multi-chip integrated photoelectric sensor provided by the present invention, and will not be repeated here.

[0020] The FT testing method for a multi-chip integrated photoelectric sensor provided herein is based on the same inventive concept as the multi-chip integrated photoelectric sensor provided herein. Therefore, the FT testing method for a multi-chip integrated photoelectric sensor provided herein possesses at least all the advantages of the multi-chip integrated photoelectric sensor provided herein and is not further elaborated herein. For the integrated structure of the aforementioned image sensor chips, FT testing can be performed using a wafer-level testing method similar to chip probing (CP) testing after wafer fabrication, which avoids PCB substrate warping and greatly improves testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Figure 1 It is a structural diagram of a photoelectric sensor in the prior art; Figure 2 1 is a schematic structural diagram of a photoelectric sensor according to a first embodiment of the present invention; Figure 3 is a structural diagram of embodiment 2 of the present invention; Figure 4 is a structural diagram of embodiment 3 of the present invention; Figure 5 is a structural diagram of a fourth embodiment of the present invention; Figure 6 is a structural diagram of a fifth embodiment of the present invention; Figure 7 This is a schematic structural diagram of a wafer undergoing FT testing according to an embodiment of the present invention; Figure 8 This is a process flow chart of Example 1 of the present invention.

[0022] Attachment Figure 1 middle: 100. Existing photoelectric sensor; 101. PCB substrate backside solder pad; 102. PCB substrate; 103. Package cover; 104. Wire bond; 105. CIS chip solder pad; 106. CIS chip; 107. PCB substrate frontside solder pad; 108. Light source chip.

[0023] Attachment Figures 2 to 8 middle: 200, wafer; 300, carrier plate; 400, packaged image sensor chip; 500, test probe; 600, optical test calibration.

[0024] 1. Image sensor chip; 2. Cover structure; 3. Light source chip; 4. Photosensitive area; 5. Other metal layer pads; 6. Light-emitting area; 7. First bottom pad; 8. Second bottom pad; 9. Conductive adhesive; 10. Filter or lens; 11. Internal insulation layer; 12. RDL reconstruction wiring layer; 13. Surface insulation layer; 14. BGA / LGA pad; 15. First front pad; 16. Second front pad; 17. Carrier; 18. Closed cavity; 19. Glass cover; 20. Retaining wall; 21. Lens; 22. Graphic glass; 23. First light-transmitting film; 24. Second light-transmitting film; 25. Light-transmitting glass. DETAILED DESCRIPTION

[0025] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0026] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] Research has found that the iteration and upgrading of terminal products has accelerated, including mobile phones, smart watches, smart bracelets, smart furniture, IOT (Internet of Things) products, etc. The size of the products is pursuing extreme miniaturization. The packaging process using PCB substrate as the carrier board can no longer meet the product's demand for extreme miniaturization in space.

[0028] To meet the needs of end customers, this invention directly Die-Bonds the light source chip to the surface of the CMOS image sensor chip. This, combined with wafer-level packaging, significantly reduces the product's dimensions in the X and Y directions. By eliminating the PCB substrate, the Z dimension is also reduced. Furthermore, wafer-level testing methods, similar to post-wafer Chip Probing (CP) testing, are used for FT testing, significantly improving test efficiency.

[0029] In addition, based on this packaging form of directly bonding the light source chip to the surface of the CMOS image sensor chip, the present invention provides photoelectric sensors with a variety of cover structures. Different cover structures can be selected according to the usage scenario of the terminal product, so that the photoelectric sensor has better performance and usage effect.

[0030] [Example 1] For details, please refer to Figure 2-Figure 8 , which is a schematic diagram of an embodiment of the present invention. Figure 2 As shown, a multi-chip integrated photoelectric sensor includes: An image sensor chip 1 includes a photosensitive region 4 and an edge region (not labeled) on its front surface. A light-transmitting member is disposed on the photosensitive region 4 to filter out interfering light. The edge region includes a plurality of front pads, including a first front pad 15 and a second front pad 16, as well as other metal layer pads 5 for transmitting electrical signals. A light source chip 3, wherein the top of the light source chip 3 is provided with a light emitting area 6, and the bottom is provided with a first bottom pad 7 and a second bottom pad 8, which are respectively connected to the two front pads of the image sensor chip 1. More preferably, the first bottom pad 7 and the second bottom pad 8 are respectively connected to the first front pad 15 and the second front pad 16; The RDL reconstruction wiring layer 12 passes through the image sensor chip 1 to transmit the electrical signal of the front pad of the image sensor chip 1 to the back side; The cover structure 2 is provided on the edge region and is used to protect the front surface of the image sensor chip 1 .

[0031] The light source chip 3 is integrated onto the surface of the CMOS image sensor chip 1. To enable DieBonding of the light source chip 3 to the surface of the CMOS image sensor chip 1, a customized design is implemented for the CMOS image sensor chip 1, with corresponding DieBond locations reserved for the light source chip 3. More specifically, a first front-side solder pad 15 and a second front-side solder pad 16 are provided on the image sensor chip 1 for bonding to the light source chip 3. An RDL reconstruction wiring layer 12 is also provided for signal transmission. A light-transmitting member is provided to protect and cover the photosensitive area 4 of the image sensor chip 1. A cover plate structure 2 protects the entire front surface of the image sensor chip 1 and also serves as a carrier for implementing back-side processing of the image sensor chip 1.

[0032] Correspondingly, a first bottom pad 7 and a second bottom pad 8 are provided at the bottom of the light source chip 3. The surface of the first bottom pad 7 is connected to the surface of the first front pad 15 of the image sensor chip 1, and the surface of the second bottom pad 8 is connected to the surface of the second front pad 16 of the image sensor chip 1. The second front pad 16 exports the electrical signal to the back of the image sensor chip 1 through the TSV (Through Silicon Via) process, and a BGA / LGA pad 14 is formed on the back of the image sensor chip 1.

[0033] The light source chip 3 adopts a design where the positive and negative electrode pads are on the same side, and the light-emitting area 6 is on the other side. The first bottom pad 7 and the second bottom pad 8 serve as the positive and negative pads of the light source chip 3. The edge area around the photosensitive area 4 of the image sensor chip 1 is reserved for the support of the cover structure 2. An area is reserved on one side of the photosensitive area 4 for placing the light source chip 3, and a first front pad 15 and a second front pad 16 are provided in this area to connect the first bottom pad 7 and the second bottom pad 8. More preferably, conductive glue 9 is provided between the first bottom pad 7 and the first front pad 15, and the second bottom pad 8 and the second front pad 16. Ag paste (silver paste) / ACA / ACP (anisotropic conductive adhesive) or ACF (anisotropic conductive film) material is used as the conductive glue 9.

[0034] The RDL reconfigured wiring layer 12, located on the back side of the image sensor chip 1, is connected to a BGA / LGA pad 14. An internal insulation layer 11 is provided between the RDL reconfigured wiring layer 12 and the image sensor chip 1. The RDL reconfigured wiring layer 12, located on the back side of the image sensor chip 1, is also covered with a surface insulation layer 13. The BGA / LGA pad 14 is manufactured using a BGA or LGA process and is coated with an organic film. The RDL reconfigured wiring layer 12 redistributes the chip's input / output (I / O) pad contact locations, shortening critical signal paths.

[0035] Through the TSV (Through Silicon Via) process, the pads connected to the positive (or negative) electrode of the light source chip 3 and other required pads of the image sensor chip 1 are connected to the back of the wafer of the image sensor chip 1. Figure 2 The other metal layer pads 5 on the front of the image sensor chip 1 are connected to the BGA / LGA pads 14 through the RDL reconstruction wiring layer 12. Similarly, the chip front pads connected to the pads at the bottom of the light source chip 3 can also be connected to the BGA / LGA pads 14 through the RDL reconstruction wiring layer 12.

[0036] When forming the RDL reconstruction wiring layer 12, a TSV process is first used to form a deep silicon via that penetrates the image sensor chip 1. The internal insulation layer 11 is then covered in the hole and on the back of the image sensor chip 1. Metal material is then arranged to form the RDL reconstruction wiring layer 12. Subsequently, a surface insulation layer 13 is formed on the back of the image sensor chip 1. A BGA (Ball Grid Array) or LGA (Land Grid Array) package is used to make BGA / LGA pads 14 similar to PCB substrate packaging. An organic film, such as a blue film or UV film, is then attached to the BGA / LGA pads 14 for performing front-side processing on the image sensor chip 1, such as etching to form the cover structure 2.

[0037] In one embodiment, the light-transmitting component is a filter or lens 10, which is made of resin, for example, and the cover structure 2 is a plurality of columns arranged on the edge area, which are also commonly used DAM (Dam and Fill) retaining walls.

[0038] It is understood that the light-transmitting member can also be other forms of light-transmitting structures to filter out interfering light of wavelengths other than the light source, such as light-transmitting dry film, glass, or other highly transparent materials. The cover structure 2 can be arranged in conjunction with the structure of the light-transmitting member and can be a pillar structure or other structure. This packaging method, in which the light source chip 3 is directly bonded to the surface of the CMOS image sensor chip, provides a variety of photoelectric sensors with cover structures. Different cover structures can be selected according to the use scenario of the end product, thereby achieving better performance and usage results for the photoelectric sensor.

[0039] Based on the same technical concept, this embodiment also provides a method for manufacturing a multi-chip integrated photoelectric sensor. By using a wafer-level packaging process, the image sensor chip 1 is customized and the light source chip 3 is integrated onto the surface of the CIS image sensor chip 1, leaving a DIE Bond position for the light source chip 3. This reduces the size of the planar area required for the product. Furthermore, by eliminating the use of a PCB substrate, the thickness of the entire product is reduced, meeting the size requirements of the terminal product. Figure 8 , specifically including the following steps: S1, provide an image sensor chip 1 and a light source chip 3, the front of the image sensor chip 1 has a photosensitive area 4 and an edge area, a plurality of front pads are arranged in the edge area, including a first front pad 15 and a second front pad 16, and other metal layer pads 5, the top of the light source chip 3 is provided with a light-emitting area 6, and the bottom is provided with a first bottom pad 7 and a second bottom pad 8.

[0040] Determine the position of the photosensitive area 4 of the image sensor chip 1, reserve the edge area for making the support of the package cover structure 2, reserve an area on the other side of the horizontal position of the photosensitive area 4 to place the light source chip 3, and design two pads on the surface of the image sensor chip 1, the first front pad 15 and the second front pad 16, corresponding to the positive and negative pads of the light source chip 3. The light source chip 3 adopts the form of positive and negative poles on the same side, that is, the first bottom pad 7 and the second bottom pad 8 are on the same side, and the light-emitting area 6 is designed on the other side.

[0041] S2: Connect the two front solder pads of the image sensor chip 1 to the first bottom solder pad 7 and the second bottom solder pad 8 at the bottom of the light source chip 3, thereby establishing an electrical signal connection between the two chips. Preferably, the bottom of the light source chip 3 is connected to the front of the image sensor chip 1 via the first front solder pad 15 and the second front solder pad 16.

[0042] On the wafer of image sensor chip 1 (typically an 8-inch or 12-inch wafer), the die bond process for light source chip 3 is first performed. Preferably, Ag paste, ACA / ACP (anisotropic conductive adhesive), or ACF (anisotropic conductive film) is used to die bond light source chip 3 to the wafer of image sensor chip 1, ensuring that each good chip (DIE) has a light source chip 3 attached. Alternatively, SMT (Surface Mount Technology) placement and reflow soldering processes are used to attach light source chip 3. During the die bond process, adhesive, such as silver paste, ACA / ACP, or ACF, is first applied to image sensor chip 1. Then, light source chip 3 is placed on top, or assembled using SMT placement technology. After assembly, reflow soldering is performed through a temperature reflow tunnel, which adjusts the temperature over time to melt the adhesive or solder balls. Then, it is cooled to fix the light source chip 3 on the image sensor chip 1 .

[0043] Specifically, a first front pad 15, a second front pad 16 and other metal layer pads 5 are provided in the edge area. Through a chip bonding process or an SMT patch, and then a reflow process, the first bottom pad 7, the second bottom pad 8 and the first front pad 15 and the second front pad 16 of the image sensor chip 1 are connected correspondingly, wherein a conductive glue 9 is also provided between the first bottom pad 7 and the first front pad 15, and the second bottom pad 8 and the second front pad 16.

[0044] S3, providing a light-transmitting component on the light-sensitive area 4 to filter out interfering light.

[0045] More preferably, arranging a light-transmitting component on the photosensitive area 4 includes: arranging a filter on the photosensitive area 4 through a chip bonding process, or manufacturing a lens on the photosensitive area 4.

[0046] For example, a Die Bond filter or lens 10 is formed in the photosensitive area 4 of the image sensor chip 1 to filter out interference light of wavelengths other than the light source, or to make a lens made of resin or other materials. The lens made of resin material is usually made by molding. This step can be used or not according to product requirements.

[0047] S4, providing a carrier sheet 17, etching the carrier sheet 17 to form an opening adapted to the photosensitive area 4 and the light source chip 3, and pressing the side of the carrier sheet 17 with the opening onto the front surface of the image sensor chip 1 to form a cover structure 2.

[0048] Use a second silicon wafer of the same size as the image sensor chip 1 wafer, and make a DAM retaining wall design through dry etching to expose the light source chip 3 area and the photosensitive area 4. Reserve a certain process space to ensure that each image sensor chip 1 (DIE) on the wafer has the same DAM (Dam and Fill) retaining wall design, similar to Figure 2 Middle cover structure 2: In this step, alignment marks need to be designed to ensure alignment of the following Bonding process.

[0049] The second silicon wafer and the wafer of the image sensor chip 1 are bonded together using the alignment marks reserved in the previous step, so that the cavity of the second silicon wafer overlaps with the photosensitive area 4 of the image sensor chip 1 and the light source chip 3 Die Bond.

[0050] S5, thinning the back surface of the image sensor chip 1 to a desired thickness. The second silicon wafer is used as a carrier to grind the back surface of the image sensor chip 1 to a desired thickness.

[0051] S6, using the TSV process, forming an RDL reconstruction wiring layer 12 in the image sensor chip 1 to transmit the electrical signal from the front to the back of the image sensor chip 1. Through the TSV (Through Silicon Via) process, the pads connected to the positive (or negative) electrode of the light source chip 3 and other required pads of the image sensor chip 1 are connected to the back of the wafer of the image sensor chip 1.

[0052] Specifically, using the TSV process, forming the RDL reconstruction wiring layer 12 in the image sensor chip 1 includes: A through-silicon via (TSV) is formed on the image sensor chip 1 by using a photolithography and etching process. More preferably, a photolithography and dry etching process is used to form the TSV. An internal insulating layer 11 is formed in the through silicon via and on the back side of the image sensor chip 1. More preferably, a photolithography and curing process is used to form the through silicon via inner insulating layer and the surface insulating layer 13. A physical vapor deposition process is used to form an RDL reconstruction wiring layer 12 in the silicon through-hole via. PVD (physical vapor deposition), photolithography, etching and electroplating processes are used (specific process requirements are determined according to product characteristics) to make an RDL (Re-Distribution Layer) reconstruction wiring layer 12. The RDL reconstruction wiring layer 12 is used to redistribute the input / output (I / O) pad contact positions of the chip, thereby shortening the critical signal path.

[0053] The back side of the image sensor chip 1 is further covered with a surface insulating layer 13. More preferably, the surface insulating layer 13 is formed by photolithography and curing processes. A plurality of BGA / LGA pads 14 are formed on the back side of the image sensor chip 1 using a BGA / LGA process. It is understood that the BGA (Ball Grid Array) or LGA (Land Grid Array) process can be used to create BGA / LGA pads 14 similar to a PCB substrate package.

[0054] Then, an organic film, such as a blue film / UV film, is attached to the surface of the BGA / LGA pad 14, and the second silicon wafer is ground and dry-etched to form a DAM cover structure 2, exposing the light source chip 3 and the photosensitive area 4 of the image sensor chip 1.

[0055] By adopting wafer-level packaging, the light source chip is directly bonded to the surface of the CMOS image sensor chip, which greatly reduces the size of the product in the X and Y directions and the size of the plane area required for the product. In addition, because the use of the PCB substrate is eliminated, the size in the Z direction is also reduced accordingly, reducing the thickness of the entire product and meeting the size requirements of the terminal product.

[0056] Based on the same technical concept, this embodiment also provides a FT test method for a multi-chip integrated photoelectric sensor, such as Figure 7 As shown, the method for performing FT testing on the multi-chip integrated photoelectric sensor as described above includes the following steps: Providing a wafer 200 containing a packaged image sensor chip 400, and peeling the wafer 200 from the organic film; The wafer 200 is transferred to the carrier 300 of the FT test platform, the BGA / LGA pad 14 of the packaged image sensor chip 400 is brought into contact with the test probe 500 on the FT test platform, and the front surface of the packaged image sensor chip 400 is connected to the optical test calibration 600 to test the communication, power consumption and performance parameters of the photoelectric sensor.

[0057] Specifically, the packaged wafer 200 is peeled off from the organic film, the blue film is peeled off, the UV film is first de-UVed and then peeled off, and the wafer 200 is transferred to the FT test platform. The wafer 200 is fixed by a ring contact method. Specifically, a retaining ring (Ring) is used to fix the carrier 300 of the FT test equipment and the wafer 200. The BGA / LGA pad 14 at the bottom of the packaged image sensor chip 400 contacts the test probe 500 on the test platform. The test probe 500 is a Pogo pin, which is a spring-type probe formed by pre-pressing the three basic components of the needle shaft, spring, and needle tube through a precision instrument. The surface of the packaged image sensor chip 400 (DIE) is connected to the optical test calibration 600, see Figure 7 , testing the product's communication, power consumption, and performance parameters. This step uses a wafer-level FT solution, similar to wafer-level CP (Chip Probing) testing, which greatly improves test efficiency. After the test is completed, a Bin Mapping diagram of the different bins of the wafer is generated. At the same time, ink dotting can be used to mark defective products. This step can also use a traditional testing solution, performing FT testing after dicing into individual pieces, but the efficiency is much lower than wafer-level FT.

[0058] After the FT test is complete, wafer 200 is coated with an organic film (blue film / UV film), then diced and binned according to the BinMapping diagram, resulting in a tested, ultra-compact optical sensor product. The integrated structure of the image sensor chip can be tested using wafer-level FT testing methods, similar to the Chip Probing (CP) test performed after wafer fabrication. This method avoids PCB substrate warping and significantly improves testing efficiency.

[0059] [Example 2] Please refer to Figure 3The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor, which adopts a cover structure 2 different from that of the first embodiment, adopts a wafer-level packaging multi-chip integrated packaging structure, and retains a closed cavity 18. The structure still uses silicon material as a carrier 17, and retains the closed cavity 18. During manufacturing, the same process as the manufacturing steps of the first embodiment is adopted, and an opening for accommodating a light-transmitting component and a light source chip 3 is made on another silicon wafer. The other silicon wafer is aligned and pressed onto the image sensor chip 1, and then the front processing of the image sensor chip 1 is performed. When the carrier 17 is subsequently thinned, the carrier 17 on the top of the light-transmitting component and the light source chip 3 is retained to form a closed cavity 18.

[0060] It should be noted that the wavelength of the light source needs to be greater than 1000 nm, which is sufficient to penetrate the silicon carrier 17 of a certain thickness. The test plan and other manufacturing processes and FT test methods are the same as those in Example 1 and will not be repeated here.

[0061] [Example 3] Please refer to Figure 4 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor, which adopts a cover structure 2 similar to that of the second embodiment, and still adopts a closed cavity 18. During manufacturing, a columnar DAM structure, i.e., a retaining wall 20, is formed, but a glass cover 19 is used. The glass cover 19 is made of glass with high light transmittance, and the glass does not need to be ground. The DAM structure, i.e., the retaining wall 20, is made on the glass cover 19. The retaining wall 20 can be made of PCB, glass or silicon wafer. PCB, glass or silicon wafer have low transmittance to light source and play the role of blocking the light source. The test scheme and other manufacturing processes and FT test methods of this embodiment are the same as those of the first embodiment and will not be repeated here.

[0062] [Example 4] Please refer to Figure 5 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor. Compared to the structure of the first embodiment, this embodiment uses high-transmittance glass instead of silicon wafers and does not utilize a DAM structure. The light-transmitting component utilizes a composite structure of patterned glass 22, a first light-transmitting film 23, and a lens 21. The patterned glass 22 and first light-transmitting film 23 have a certain thickness. After cutting, the light source chip 3 is exposed, thereby protecting the image sensor chip 1.

[0063] The first light-transmitting film 23 is made of DAF (Die Attach Film) or dry film, the lens 21 is made of resin or glass, and the patterned glass 22 is made of patterned high-transmittance glass.

[0064] Among them, after the light source chip 3 is Die Bonded to the image sensor chip 1 on the wafer, a glass wafer of the same size as the wafer of the image sensor chip 1 is used. First, a high-transmittance DAF (Die Attach Film) film or dry film is attached to one side of the glass wafer. Then, the position of the light source chip 3 is processed (mostly using a laser method), and the glass and DAF film / dry film at this position are cut through. After the glass wafer is bonded to the wafer of the image sensor chip 1, the light source chip 3 can be fully exposed. Considering the bonding accuracy and laser cutting accuracy, a certain process space is reserved.

[0065] Similarly, a glass wafer is bonded to the wafer of the image sensor chip 1 , and then a UV film is applied to the glass wafer. The glass wafer is used as a carrier to make a TSV structure and LGA or BGA package. The process is the same as in the first embodiment.

[0066] If necessary, a lens 21 (made of glass or resin) is attached to the photosensitive area 4 of the image sensor chip 1, and a high-transmittance DAF film or dry film is attached to the lens 21, and then wafer-level FT testing and wafer cutting are performed. The testing scheme and other manufacturing processes and FT testing methods of this embodiment are the same as those of Example 1.

[0067] [Example 5] Please refer to Figure 6 The present invention also provides another embodiment of a multi-chip integrated photoelectric sensor. Compared to the structure of the fourth embodiment, this embodiment does not use a lens 21. Instead, a layer of high-transmittance transparent glass 25 of the same size as the wafer is bonded to the pattern glass 22 of the fourth embodiment, serving as a cover to ensure product sealing and high reliability. The testing scheme, other manufacturing processes, and FT testing methods of this embodiment are the same as those of the first embodiment and are not further described here.

[0068] Similarly, the first light-transmitting film 23 is made of DAF (Die Attach Film) film or dry film, the pattern glass 22 is made of patterned high-transmittance glass, and a second light-transmitting film 24 is arranged above the pattern glass 22. The second light-transmitting film 24 is made of DAF film or dry film. The top of the second light-transmitting film 24 is light-transmitting glass 25, which is also made of high-transmittance glass.

[0069] In the multi-chip integrated photoelectric sensor and its manufacturing method and FT testing method provided by the present invention, a wafer-level packaging form is adopted to directly bond the light source chip to the surface of the CMOS image sensor chip, greatly reducing the size of the product in the X and Y directions and the size of the plane area required for the product. Moreover, because the use of the PCB substrate is eliminated, the size in the Z direction is also reduced accordingly, reducing the thickness of the entire product and meeting the size requirements of the terminal product. In addition, this packaging form of directly bonding the light source chip to the surface of the CMOS image sensor chip provides photoelectric sensors with a variety of cover plate structures, and different cover plate structures can be selected according to the use scenario of the terminal product, so that the photoelectric sensor has better performance and use effect. In addition, for the integrated structure of the above-mentioned image sensor chip, a wafer-level testing method can be used for FT testing. The testing method is similar to the Chip Probing (CP) test after wafer production, which avoids warping of the PCB substrate and greatly improves the testing efficiency.

[0070] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A multi-chip integrated photoelectric sensor, characterized in that: include: An image sensor chip, wherein the front surface of the image sensor chip has a photosensitive area and an edge area, the photosensitive area is provided with a light-transmitting member for filtering out interfering light, and the edge area is provided with a plurality of front solder pads for transmitting electrical signals; A light source chip, wherein the top of the light source chip is provided with a light emitting area, and the bottom of the light source chip is provided with a first bottom pad and a second bottom pad, which are respectively connected to the two front pads of the image sensor chip; An RDL reconstruction wiring layer passes through the image sensor chip to transmit electrical signals from the front pad of the image sensor chip to the back pad; A cover structure is provided on the edge region and is used to protect the front surface of the image sensor chip.

2. The multi-chip integrated photoelectric sensor according to claim 1, characterized in that: The first bottom pad surface is connected to the first front pad surface of the image sensor chip, the second bottom pad surface is connected to the second front pad surface of the image sensor chip, and the second front pad exports the electrical signal to the back side of the image sensor chip through the TSV process, and a BGA / LGA pad is formed on the back side of the image sensor chip.

3. The multi-chip integrated photoelectric sensor according to claim 2, characterized in that: The RDL reconstruction wiring layer is located at one end on the back side of the image sensor chip and is connected to the BGA / LGA pad, and an internal insulation layer is provided between the RDL reconstruction wiring layer and the image sensor chip. The RDL reconstruction wiring layer is also covered with a surface insulation layer at one end on the back side of the image sensor chip.

4. The multi-chip integrated photoelectric sensor according to claim 1, characterized in that: The light-transmitting component is a filter or a lens, and the cover structure is a plurality of columns arranged on the edge area.

5. The multi-chip integrated photoelectric sensor according to claim 3, characterized in that: An organic film is attached to the BGA / LGA pad.

6. A method for manufacturing a multi-chip integrated photoelectric sensor, characterized in that: The following steps are involved: An image sensor chip and a light source chip are provided. The front surface of the image sensor chip has a photosensitive area and an edge area. A plurality of front pads are provided in the edge area. The top of the light source chip is provided with a light emitting area, and the bottom is provided with a first bottom pad and a second bottom pad. Connecting the two front pads of the image sensor chip to the first bottom pad and the second bottom pad at the bottom of the light source chip to form an electrical signal connection between the two chips; A light-transmitting component is provided on the light-sensitive area for filtering out interfering light; Providing a carrier sheet, etching the carrier sheet to form an opening adapted to the photosensitive area and the light source chip, and pressing the side of the carrier sheet with the opening onto the front surface of the image sensor chip to form a cover structure; Thinning the back side of the image sensor chip to a desired thickness; A TSV process is used to form an RDL reconstruction wiring layer in the image sensor chip to transmit electrical signals from the front side of the image sensor chip to the back side.

7. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, wherein: A first front pad, a second front pad and other metal layer pads are provided in the edge area. The first bottom pad, the second bottom pad and the first front pad and the second front pad of the image sensor chip are connected correspondingly through a chip bonding process or an SMT patch and then a reflow process.

8. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, wherein: Providing a light-transmitting component on the photosensitive area includes: providing a filter on the photosensitive area through a chip bonding process, or manufacturing a lens on the photosensitive area.

9. The method for manufacturing a multi-chip integrated photoelectric sensor according to claim 6, wherein: Forming an RDL reconstruction wiring layer in the image sensor chip using a TSV process includes: forming through-silicon vias (TSVs) on the image sensor chip using photolithography and etching processes; forming an internal insulating layer within the through silicon via and on the back side of the image sensor chip; forming an RDL reconstruction wiring layer in the through silicon via by adopting a physical vapor deposition process; Continuing to cover the back side of the image sensor chip with a surface insulating layer; A plurality of BGA / LGA pads are formed on the back side of the image sensor chip by adopting a BGA / LGA process.

10. A FT test method for a multi-chip integrated photoelectric sensor, characterized in that: The method for performing FT testing on the multi-chip integrated photoelectric sensor according to any one of claims 1 to 5 comprises the following steps: Providing a wafer containing a packaged image sensor chip, and peeling the wafer from the organic film; The wafer is transferred to the carrier of the FT test platform, the BGA / LGA pads of the packaged image sensor chip are contacted with the test probes on the FT test platform, the front side of the packaged image sensor chip is connected to the optical test calibration, and the communication, power consumption and performance parameters of the photoelectric sensor are tested.

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