Image sensor and preparation method thereof

Abstract

The invention provides an image sensor and a preparation method thereof, and the method comprises the steps: providing a device substrate, and forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate; forming a support column penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer and extending into the device substrate; forming a release groove; removing the first sacrificial layer to form a first cavity, and removing the second sacrificial layer to form a second cavity; forming a first isolation layer in the first cavity, and forming a first shading structure in the second cavity; removing the support column to form a second shading structure; forming a transistor on the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the transistor; and bonding the support substrate and the interlayer dielectric layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to an image sensor and a method for manufacturing the same. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) technology has been widely used in applications such as digital still cameras, digital video cameras, medical cameras, and automotive cameras. CMOS image sensors are primarily classified into two types: front-side illumination (FSI) and back-side illumination (BSI). Compared to FSI image sensors, BSI image sensors place the photosensitive area containing the photodiode above the circuitry, reducing light losses such as metal line reflection and dielectric absorption. This significantly increases the photoelectric conversion efficiency and improves image quality.

[0003] However, with the development of advanced manufacturing processes, BSI image sensors have increasingly stringent requirements for stored charge. Traditional BSI image sensors experience a latch-up effect between the source and drain of transistors. This causes crosstalk when light passes through the photodiode (PD) region and enters the floating diffusion (FD) region within the same pixel during operation. This also causes crosstalk between different pixels. Furthermore, the ion implantation process during photodiode fabrication can damage the photodiode, impacting product quality. Therefore, improving image sensor quality, preventing latch-up between the source and drain of transistors, and avoiding crosstalk between pixels are pressing technical challenges. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In response to the current problems, the present application provides, on one hand, a method for preparing an image sensor, comprising: providing a device substrate, and sequentially forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer on the device substrate; forming a plurality of support pillars penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate; forming at least one release groove penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer; using the release groove as a release channel, etching and removing the first sacrificial layer to form a plurality of support pillars; A first cavity is formed between the first epitaxial layer and the photodiode layer, and the second sacrificial layer is etched and removed to form a second cavity between the first epitaxial layer and the second epitaxial layer; a first isolation layer is formed in the first cavity, and a first light-shielding structure is formed in the second cavity; the support column is removed to form an isolation trench, and a second light-shielding structure is formed in the isolation trench; a plurality of transistors are formed on the second epitaxial layer, each of the transistors including a drain region formed in the second epitaxial layer; an interlayer dielectric layer is formed covering the second epitaxial layer and the plurality of transistors; a supporting substrate is provided, and the supporting substrate and the interlayer dielectric layer are bonded together.

[0006] Exemplarily, the image sensor includes a plurality of pixel units, each of the pixel units includes at least one photodiode region and at least two transistors, and the second light shielding structure is further provided between any two adjacent transistors in each of the pixel units.

[0007] Exemplarily, the forming of a first isolation layer in the first cavity and the forming of a first light-shielding structure in the second cavity include: depositing an isolation material layer to form a first isolation layer in the first cavity, the first isolation layer filling the first cavity, and the isolation material layer is also deposited on the surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering the surface of the second epitaxial layer facing the first epitaxial layer, and the isolation material layer is also deposited on the surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering the surface of the first epitaxial layer facing the second epitaxial layer; depositing a first light-shielding layer to fill the portion of the second cavity located between the second isolation layer and the third isolation layer, and the first light-shielding structure includes the first isolation layer, the second isolation layer and the first light-shielding layer.

[0008] Illustratively, after forming the second light-shielding structure and before forming the multiple transistors, the preparation method further includes: forming a plurality of first conductive plugs that sequentially penetrate the second epitaxial layer, the first light-shielding structure, the first epitaxial layer and the first isolation layer, the plurality of first conductive plugs being arranged at intervals, and each of the first conductive plugs being electrically connected to a photodiode region in the photodiode layer; and the preparation method further includes: the step of forming a plurality of conductive interconnect structures in the interlayer dielectric layer, wherein each of the conductive interconnect structures is electrically connected to at least one of the first conductive plugs and the drain region of at least one of the transistors.

[0009] Exemplarily, the isolation material layer is also deposited on the sidewalls of the release groove, and the first light shielding layer completely fills the release groove.

[0010] Exemplarily, the first conductive plug is also extended along the first direction, wherein the image sensor includes a plurality of pixel units, each of the pixel units includes at least one photodiode region and at least two transistors, and the second shading structure is arranged between two adjacent pixel units in the second direction, and the second shading structure is also extended along the first direction, and the first direction is perpendicular to the thickness direction of the device substrate; each of the release grooves is arranged between two adjacent pixel units in the first direction, and the release grooves also extend along the second direction; wherein the first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other, the drain region of at least one transistor of each pixel unit is used as a floating diffusion region, and the floating diffusion region and the photodiode region of each pixel unit are spaced apart in the thickness direction of the device substrate.

[0011] Illustratively, after bonding the support substrate and the interlayer dielectric layer, the method further includes: thinning a side of the device substrate away from the first epitaxial layer to expose an end of the second light-shielding structure away from the interlayer dielectric layer.

[0012] Exemplarily, forming a second light-shielding structure in the isolation trench includes: forming a fourth isolation layer on the sidewall and bottom of the isolation trench; depositing a second light-shielding layer to fill the isolation trench, and the second light-shielding structure includes the fourth isolation layer and the second light-shielding layer.

[0013] Exemplarily, it also includes: forming a passivation layer on the side of the device substrate facing away from the first isolation layer; forming multiple grid structures on the passivation layer, wherein a grid structure is arranged between adjacent pixel units, and grid openings are formed between adjacent grid structures, and the grid openings expose the surface of the passivation layer; embedding a color filter film layer in the grid opening; and forming multiple microlenses on the color filter film layer, wherein the multiple microlenses correspond to the multiple pixel units.

[0014] On the other hand, the present application provides an image sensor, which is prepared by the above-mentioned preparation method. The image sensor and preparation method provided in the present application can effectively prevent the latch-up effect between the source and drain of the transistor and avoid crosstalk between the photodiode region and the floating diffusion region by setting a first isolation layer and a shading structure between the photodiode region and the floating diffusion region. At the same time, the second shading structure can effectively avoid crosstalk between different pixels, thereby improving the quality of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The following drawings of the present invention are incorporated herein as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and the description thereof is used to explain the principle of the present invention.

[0016] In the attached figure

[0017] Figure 1 A flow chart showing a method for preparing an image sensor according to a specific embodiment of the present application is shown; Figure 2 A schematic diagram showing a device obtained by sequentially implementing an image sensor manufacturing method in the related art; Figures 3 to 22 A schematic diagram of a device obtained by sequentially implementing a method for preparing an image sensor according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] Next, the present invention will be described more fully with reference to the accompanying drawings, which illustrate embodiments of the present invention. However, the present invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0019] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there can be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part without departing from the teachings of the present invention.

[0020] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0021] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present invention. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] In order to fully understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0023] With the rapid development of semiconductor technology, BSI image sensors have increasingly higher requirements for stored charge. Figure 2 As shown, there is a latch-up effect between the source 110 and the drain 120 of the transistor in the conventional BSI image sensor (ie, there is a latch-up effect between the photodiode and the floating diffusion region, as shown in FIG. Figure 2 The problem is that photons from the same pixel pass through the photodiode (PD) region and enter the floating diffusion (FD) region during operation, causing crosstalk. This also occurs between different pixels. Furthermore, ion implantation (also known as ion injection) during photodiode fabrication can damage the photodiode, affecting product quality. Therefore, improving image sensor quality, mitigating the latch-up effect between the transistor source and drain, and avoiding crosstalk between pixels are pressing technical challenges.

[0024] Therefore, in view of the existence of the above technical problems, the present application proposes a method for preparing an image sensor, such as Figure 1 As shown, it mainly includes the following steps: Step S1, providing a device substrate, and sequentially forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer on the device substrate; Step S2, forming a plurality of support pillars penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate; Step S3, forming at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer; Step S4, using the release groove as a release channel, etching and removing the first sacrificial layer to form a first cavity between the first epitaxial layer and the photodiode layer, and etching and removing the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer; Step S5, forming a first isolation layer in the first cavity and forming a first light shielding structure in the second cavity; Step S6, removing the support pillars to form an isolation trench, and forming a second light shielding structure in the isolation trench; Step S7, forming a plurality of transistors on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer; Step S8, forming an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors; Step S9: providing a supporting substrate, and bonding the supporting substrate and the interlayer dielectric layer.

[0025] The method for preparing the image sensor of the embodiment of the present application can effectively prevent the latch-up effect between the source and drain of the transistor and avoid crosstalk between the photodiode region and the floating diffusion region by forming a first isolation layer and a shading structure between the photodiode region and the floating diffusion region, respectively. At the same time, the second shading structure can effectively avoid crosstalk between different pixels, thereby improving the quality of the image sensor.

[0026] Example 1 Below, reference Figure 1 as well as Figures 3 to 22 The preparation method of the image sensor of the present application is described in detail, wherein: Figure 1 A flow chart showing a method for preparing an image sensor according to a specific embodiment of the present application is shown. Figures 3 to 22 A schematic diagram of a device obtained by sequentially implementing a method for preparing an image sensor according to a specific embodiment of the present application is shown, wherein (a) in the accompanying drawing is a top view schematic diagram of a device obtained by sequentially implementing a method for preparing an image sensor according to a specific embodiment of the present application, and (b) in the accompanying drawing is a cross-sectional schematic diagram of a device obtained by sequentially implementing a method for preparing an image sensor according to a specific embodiment of the present application.

[0027] Illustratively, the method for preparing the image sensor of the present application includes the following steps: First, step S1 is performed to provide a device substrate, and a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer are sequentially formed on the device substrate.

[0028] In one example, if Figure 3 As shown, a device substrate 201 is provided. The material of device substrate 201 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI); or may be double-side polished silicon wafers (DSPs), ceramic substrates such as alumina, quartz, or glass substrates. Although several examples of materials that can form the device substrate are described herein, any material that can be used as a device substrate falls within the spirit and scope of the present invention. In this embodiment, device substrate 201 is a silicon substrate.

[0029] In one example, if Figure 4As shown, a photodiode layer 230 is formed on the device substrate 201. Exemplarily, the material of the photodiode layer 230 includes, but is not limited to, silicon, gallium arsenide, or other suitable materials, and is epitaxially grown on the device substrate 201 using an epitaxial process. Producing the photodiode layer using an epitaxial process effectively avoids damage caused by traditional ion implantation, thereby improving the quality of the image sensor.

[0030] In one example, if Figure 4 As shown, a first sacrificial layer 202 is formed on the photodiode layer 230. Exemplarily, the material of the first sacrificial layer 202 includes, but is not limited to, amorphous silicon, polycrystalline silicon, silicon germanium (SiGe), or other suitable materials. The process for forming the first sacrificial layer 202 can be selected as needed, such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial techniques, which are not specifically limited. In this embodiment, the material of the first sacrificial layer 202 is silicon germanium. The first sacrificial layer 202 facilitates the subsequent formation of a first cavity between the photodiode layer 230 and the first epitaxial layer 203.

[0031] In one example, if Figure 4 As shown, a first epitaxial layer 203 is continuously formed on the first sacrificial layer 202. Exemplarily, the material of the first epitaxial layer 203 includes, but is not limited to, silicon, silicon germanium, silicon carbide, or other suitable epitaxial materials. The process method for forming the first epitaxial layer 203 can be selected as needed, for example, metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), or other suitable techniques, which are not specifically limited. In this embodiment, the material of the first epitaxial layer 203 is silicon, which is the same material as the device substrate 201. Therefore, the silicon formed by epitaxial growth can have the same crystal structure and orientation as the device substrate, which helps maintain high-quality electronic properties.

[0032] In one example, if Figure 4As shown, a second sacrificial layer 204 is formed on the first epitaxial layer 203. The material of the second sacrificial layer 204 may be the same as or different from the material of the first sacrificial layer 202. The process for forming the second sacrificial layer 204 is the same as that for the first sacrificial layer, and is not described in detail here. Next, a second epitaxial layer 205 is formed on the second sacrificial layer 204. The material of the second epitaxial layer 205 is the same as that for the first epitaxial layer 203. The process for forming the second sacrificial layer 204 is the same as that for the first epitaxial layer, and is not described in detail here. Alternatively, in some examples, the first epitaxial layer and the second epitaxial layer may be made of different semiconductor materials. In this embodiment, the material of the second sacrificial layer 204 is silicon germanium, and the material of the second epitaxial layer 205 is silicon. The second sacrificial layer 204 facilitates the subsequent formation of a second cavity between the first epitaxial layer 203 and the second epitaxial layer 205.

[0033] Next, step S2 is performed to form a plurality of support pillars penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate.

[0034] In one example, if Figure 5 and Figure 6 As shown, the steps of forming a plurality of support pillars 207 penetrating the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and extending into the device substrate 201 include: First, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 are etched to form a supporting groove 206 that penetrates the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and extends to the device substrate 201, and the supporting groove 206 extends along a first direction, which is a thickness direction perpendicular to the device substrate 201. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, and the photoresist layer exposes the area and position corresponding to the support groove 206. The second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 are etched using the photoresist layer as a mask to form a plurality of support grooves 206. Each support groove 206 penetrates the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and extends into the device substrate 201, and then the photoresist layer is removed. The etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, the photodiode layer 230 and the device substrate 201 can be carried out by conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching. Optionally, the plurality of support grooves 206 may be spaced apart in the second direction. Optionally, the plurality of support grooves 206 divide the photodiode layer 230 into a plurality of photodiode regions, which respectively serve as photosensitive regions of a plurality of pixel units of the image sensor.

[0035] Next, support pillars 207 are formed in support grooves 206. Specifically, support grooves 206 are filled with a support material, where the support material includes, but is not limited to, silicon oxide, silicon nitride, polysilicon, or other suitable materials. The process methods for forming support pillars 207 include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or physical vapor deposition (PVD), and are not specifically limited thereto. The formed support pillars 207 extend along a first direction perpendicular to the thickness of the device substrate 201. The positions of the support pillars are used for the subsequent formation of the second light shielding structure. After forming the support pillars 207, the support material can be planarized, for example, by using chemical mechanical polishing (CMP) to remove excess support material on the second epitaxial layer 205, thereby ensuring a flat surface for the second epitaxial layer 205. The number of support pillars can be appropriately set based on the number of subsequent pixel units. One support pillar is provided between adjacent pixel units, and the number of support pillars, for example, can be one, two, three, or more.

[0036] Continuing, step S3 is performed to form at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and the photodiode layer.

[0037] In one example, if Figure 7 As shown, the second epitaxial layer 205 , the second sacrificial layer 204 , the first epitaxial layer 203 , the first sacrificial layer 202 and the photodiode layer 230 are etched to form at least one release trench 240 , which further extends along the second direction. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, exposing the region and position corresponding to the release groove 240 to be formed. Using the photoresist layer as a mask, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the photodiode layer 230 are etched to form at least one release groove 240 extending along the second direction. The photoresist layer is then removed. The etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the photodiode layer 230 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited. The release groove 240 is also provided between two adjacent pixel units to be subsequently formed in the first direction. The first direction is perpendicular to the thickness direction of the device substrate 201, and the second direction is perpendicular to the first direction. The second direction is also perpendicular to the thickness direction of the device substrate 201.

[0038] Next, step S4 is performed to etch away the first sacrificial layer using the release groove as a release channel to form a first cavity between the first epitaxial layer and the photodiode layer, and to etch away the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer.

[0039] In one example, if Figure 8As shown, with the release groove 240 as a release channel, the first sacrificial layer 202 is etched away to form a first cavity 208 between the first epitaxial layer 203 and the photodiode layer 230 , and the second sacrificial layer 204 is etched away to form a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205 . Specifically, conventional etching processes such as, but not limited to, dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the first sacrificial layer 202 between the first epitaxial layer 203 and the photodiode layer 230, and to remove the second sacrificial layer 204 between the first epitaxial layer 203 and the second epitaxial layer 205. For example, a gaseous hydrofluoric acid (Vapor HF, VHF) etching process can be used to release the sacrificial layer, that is, gaseous hydrofluoric acid is introduced into the release groove, and the first sacrificial layer 202 and the second sacrificial layer 204 are etched away through the release groove, thereby forming a first cavity 208 between the first epitaxial layer 203 and the photodiode layer 230 and a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205.

[0040] Then, step S5 is performed to form a first isolation layer in the first cavity and a first light shielding structure in the second cavity.

[0041] In one example, if Figure 9 and Figure 10 As shown, the steps of forming the first isolation layer 210 in the first cavity 208 and forming the first light shielding structure 211 in the second cavity 209 include: First, an isolation material layer 20 is deposited, filling the first cavity 210 to form a first isolation layer 210. Second, the isolation material layer 20 is deposited on the surface of the second epitaxial layer 205 facing the first epitaxial layer 203 to form a second isolation layer 2110 covering the surface of the second epitaxial layer 205 facing the first epitaxial layer 203. The isolation material layer 20 is also deposited on the surface of the first epitaxial layer 203 facing the second epitaxial layer 205 to form a third isolation layer 2111 covering the surface of the first epitaxial layer 203 facing the second epitaxial layer 205. The isolation material layer 20 is also deposited on part of the sidewalls of the support pillar 207 and the sidewalls of the release trench 240. By way of example, the material of the isolation material layer 20 includes, but is not limited to, oxides, such as silicon oxide, and is not specifically limited thereto. The process methods for forming the first isolation layer 210, the second isolation layer 2110, and the third isolation layer 2111 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), and are not specifically limited thereto. The isolation layers can provide a physical barrier to prevent damage from subsequent processing, thereby improving device reliability and stability, and can also serve as an insulator.

[0042] Next, a first light shielding layer 2112 is deposited to fill the portion of the second cavity 209 between the second isolation layer 2110 and the third isolation layer 2111. The first light shielding layer 2112 also completely fills the release trench 240. Exemplarily, the material of the first light shielding layer 2112 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable light shielding materials. The first light shielding layer 2112 is an opaque or reflective material. The process for forming the first light shielding layer 2112 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). Forming the first isolation layer and light shielding structure between the subsequently formed photodiode region and the floating diffusion region prevents light from entering the floating diffusion region, effectively preventing latch-up between the transistor's source and drain (i.e., latch-up between the photodiode region and the floating diffusion region). This reduces crosstalk between the photodiode region and the floating diffusion region, thereby improving the quality of the image sensor.

[0043] In one example, if Figures 11 to 12 As shown, after forming the first light-shielding structure 211, the isolation material layer and the first light-shielding layer on the second epitaxial layer 205 are removed. Specifically, the isolation material layer and the first light-shielding layer on the second epitaxial layer 205 can be removed by, but not limited to, chemical mechanical polishing. Then, wet cleaning can be performed to remove residual materials from the chemical mechanical polishing process to avoid affecting device performance.

[0044] Next, step S6 is performed to remove the support pillars to form an isolation trench, and a second light shielding structure is formed in the isolation trench.

[0045] In one example, if Figure 13 As shown, the support pillars 207 are removed to form isolation trenches 2071. Specifically, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the support pillars 207, thereby forming isolation trenches 2071.

[0046] In one example, if Figure 14As shown, a second light-shielding structure 250 is formed in the isolation trench 2071. Specifically, first, an isolation material is deposited to cover the bottom and sidewalls of the isolation trench 2071 to form a fourth isolation layer 251. Exemplarily, the isolation material includes, but is not limited to, oxides such as silicon oxide, and is not specifically limited thereto. The process for forming the fourth isolation layer 251 includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The isolation layer can provide a physical barrier to prevent damage from subsequent processing, thereby improving device reliability and stability, and can also serve as an insulator. Next, a second light-shielding layer 252 is deposited to completely fill the isolation trench 2071. Exemplarily, the material of the second light-shielding layer 252 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable light-shielding materials. The process method for forming the second light-shielding layer 252 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD) methods, and is not specifically limited thereto. The fourth isolation layer 251 and the second light-shielding layer 252 constitute a second light-shielding structure 250, and the second light-shielding structure 250 also extends along a first direction, which is perpendicular to the thickness direction of the device substrate 201. The second light-shielding structure 250 is provided between two adjacent pixel units in the second direction. By providing the second light-shielding structure, crosstalk between different pixels can be effectively avoided. In some examples, the second light-shielding structure 250 is also provided between at least two adjacent transistors in each pixel unit formed subsequently, which can reduce electric field coupling between transistors and avoid signal interference between each other.

[0047] In one example, if Figure 15 As shown, the preparation method of the present application further includes: after forming the aforementioned second light-shielding structure and before forming the plurality of transistors, forming a plurality of first conductive plugs 213 sequentially penetrating the second epitaxial layer 205, the first light-shielding structure 211, the first epitaxial layer 203 and the first isolation layer 210, the step specifically including: First, the second epitaxial layer 205, the first light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 are etched to form a plurality of contact holes, wherein the bottoms of the contact holes partially expose the surface of the photodiode layer 230. Specifically, a patterned photoresist layer is formed on the second epitaxial layer 205, the photoresist layer exposing the regions and positions corresponding to the contact holes. Using the photoresist layer as a mask, the second epitaxial layer 205, the first light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 are etched to form a plurality of contact holes, wherein the formed contact holes 212 extend along a first direction. The photoresist layer is then removed. The etching of the second epitaxial layer 205, the first light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited thereto. The first direction is perpendicular to the thickness direction of the device substrate 201, and the first direction and the second direction are perpendicular to each other. The formed contact hole is used to subsequently form the first conductive plug 213. Optionally, the top view shape of the contact hole is a strip, square, circle, or other suitable shape.

[0048] Then, before forming the first conductive plug 213, the method of the present application further includes filling the contact hole with an insulating material, with the insulating material covering the sidewalls of the contact hole to form an insulating isolation layer 214. The insulating material includes, but is not limited to, oxides such as silicon oxide, and is not specifically limited thereto. The insulating isolation layer 214 may be formed by, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The insulating isolation layer 214 can be used to electrically isolate the first conductive plug 213 from the epitaxial layer outside it.

[0049] Finally, the contact holes are filled with a conductive material to form a plurality of first conductive plugs 213. Exemplarily, the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable conductive materials. The process for forming the first conductive plugs 213 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and is not specifically limited thereto. The conductive material completely fills the contact holes 212 to form a plurality of first conductive plugs 213. The first conductive plugs 213 penetrate the second epitaxial layer 205, the first light shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 along the thickness direction of the substrate. The bottom of the first conductive plugs 213 contacts the surface of the photodiode layer 230. Each first conductive plug 213 is subsequently used to electrically connect to a photodiode region 231 of the photodiode layer 230. After forming the first conductive plug 213 , a planarization process may be performed to remove excess insulating material and conductive material on the second epitaxial layer 205 . For example, chemical mechanical polishing (CMP) may be used to remove excess insulating material and conductive material on the second epitaxial layer 205 , so that the second epitaxial layer 205 has a flat surface, thereby improving device reliability.

[0050] Next, step S7 is performed to form a plurality of transistors on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer.

[0051] In one example, if Figure 16 As shown, the steps of forming transistor 215 may include: First, an active area is defined by shallow trench isolation (STI) or local oxidation (LOCOS) to isolate adjacent pixels. The shallow trench isolation structure can be located between adjacent transistors. Then, a gate structure 2150 is formed on the second epitaxial layer 205. Specifically, first, a gate dielectric layer is formed on the second epitaxial layer 205. The material of the gate dielectric layer includes but is not limited to silicon dioxide, and the method of forming the gate dielectric layer includes but is not limited to chemical vapor deposition (CVD) or thermal oxidation. Secondly, a gate layer is formed on the gate dielectric layer. The material of the gate layer includes but is not limited to polysilicon, and the gate layer is formed. The method includes but is not limited to chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods; finally, a patterned photoresist layer is formed on the gate layer, the patterned photoresist layer defines the area and position of the gate structure, and the gate layer and the gate dielectric layer are etched using the patterned photoresist layer as a mask to form a gate structure 2150 on the second epitaxial layer 205, and then the photoresist layer is removed; wherein, the etching of the gate layer and the gate dielectric layer can be carried out by conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, etc., which are not specifically limited. After the gate structure is formed, sidewalls (not shown) can also be formed on both sides of the gate structure. The sidewalls are used to protect the edges of the gate structure from damage in subsequent processes. The material of the sidewalls is not limited to insulating materials such as silicon nitride. The gate structure is used to control the transfer of charge accumulated in the photodiode to the floating diffusion region, thereby realizing an efficient signal readout mechanism.

[0052] It is worth mentioning that the number of gate structures can be determined according to the number of transistors in the image sensor.

[0053] Next, low-concentration impurities are introduced into the second epitaxial layer 205 below both sides of the gate structure 2150 through ion implantation to form lightly doped regions. The lightly doped regions improve the short channel effect and enhance device reliability. Next, highly doped source regions 2151 and drain regions 2152 are formed outside the lightly doped regions to provide low-resistance paths and enhance current driving capability. The ion implantation concentration of the highly doped source regions 2151 and drain regions 2152 is greater than that of the lightly doped regions. After the ion implantation, an annealing treatment is performed. Since the ion implantation process can cause damage to the silicon wafer lattice, annealing can repair this damage. In addition, annealing can activate the implanted ions, thereby improving the performance of the image sensor. Optionally, at least part of the drain region of the transistor can be used as a floating diffusion region. Optionally, the drain region 2152 of at least one transistor can be electrically connected to the corresponding photodiode region.

[0054] Then, step S8 is performed to form an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors.

[0055] In one example, if Figure 17As shown, before forming the interlayer dielectric layer 218, the process further includes forming a dielectric layer 216 covering the transistor 215 and the second epitaxial layer 205. Exemplarily, the material of the dielectric layer 216 includes, but is not limited to, silicon dioxide, a low-k material, or other suitable dielectric materials. The method for forming the dielectric layer 216 includes, but is not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), which are not specifically limited.

[0056] Next, a plurality of second conductive plugs 217 are formed in the dielectric layer 216, each second conductive plug 217 being electrically connected to the drain region 2152 of the transistor 215. Specifically, a patterned photoresist layer is formed on the dielectric layer 216, the photoresist layer exposing the regions and positions corresponding to the second conductive plugs 217. The dielectric layer 216 is etched using the photoresist layer as a mask to form a plurality of etched holes penetrating the dielectric layer 216, the formed etched holes extending along a first direction, and then the photoresist layer is removed. The etching of the dielectric layer 216 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited. Next, an insulating material is filled into the etched holes, covering the sidewalls of the etched holes to form an insulating layer. The insulating material includes, but is not limited to, oxides such as silicon oxide, and is not specifically limited thereto. Methods for forming the insulating layer include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Finally, a conductive material is filled into the etched holes to form second conductive plugs 217. Exemplarily, the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable conductive materials. Methods for forming the second conductive plugs 217 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD). The second conductive plugs 217 extend along the first direction, and each second conductive plug 217 is electrically connected to the drain region 2152 of the transistor 215. After forming the second conductive plug 217, a planarization process may be performed to remove excess insulating and conductive material from the dielectric layer 216. For example, chemical mechanical polishing (CMP) may be used to remove excess insulating and conductive material from the dielectric layer 216, thereby providing a flat surface for the dielectric layer 216 and improving device reliability. In one example, a conductive plug may be formed that penetrates the dielectric layer 216 and is in electrical contact with the first conductive plug 213, thereby serving as a portion of the first conductive plug 213 to lead out the corresponding photodiode region.

[0057] Then, an interlayer dielectric layer 218 is formed on dielectric layer 216. Interlayer dielectric layer 218 may include multiple layers of interlayer dielectric material. Methods for forming interlayer dielectric layer 218 include, but are not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), which are not specifically limited. Next, multiple conductive interconnect structures 219 are formed in interlayer dielectric layer 218. Each conductive interconnect structure 219 electrically connects at least one first conductive plug 213 and the drain region of at least one transistor. Specifically, each conductive interconnect structure 219 is also electrically connected to at least one second conductive plug 217. First conductive plug 213 is electrically connected to photodiode region 231, and second conductive plug 217 is electrically connected to drain region 2152 of transistor 215. Exemplarily, the material of conductive interconnect structure 219 includes, but is not limited to, copper or aluminum. Methods for depositing the conductive interconnect structure material include, but are not limited to, chemical vapor deposition (CVD) and other processes, which are not specifically limited.

[0058] It is worth mentioning that the conductive interconnect structure 219 may include multiple metal layers stacked in sequence and plugs disposed between adjacent metal layers, thereby forming a stacked conductive interconnect structure 219. Specifically, the conductive interconnect structure may be formed by any suitable method, which will not be elaborated in detail here.

[0059] Finally, step S9 is performed to provide a supporting substrate and bond the supporting substrate to the interlayer dielectric layer.

[0060] In one example, if Figure 18 As shown, a support substrate 301 is provided. The material of the support substrate 301 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors, or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon germanium-on-insulator (S-SiGeOI), silicon germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). It can also be a ceramic substrate such as double-side polished silicon wafers (DSPs), alumina, quartz, or glass substrate. Although several examples of materials that can form the support substrate are described here, any material that can be used as the support substrate falls within the spirit and scope of the present invention. In this embodiment, the support substrate 301 is a silicon substrate. The support substrate 301 and the interlayer dielectric layer 218 are bonded together. The bonding method includes, but is not limited to, silicon-oxygen bonding or hybrid bonding, which is not specifically limited.

[0061] In one example, if Figure 19 As shown, after bonding the support substrate 301 and the interlayer dielectric layer 218, the following further comprises: thinning the side of the device substrate 201 opposite to the first epitaxial layer 203 to expose the end of the second light-shielding structure 250 away from the interlayer dielectric layer 218. Specifically, after bonding, the bonded structure is flipped over, and the back side of the device substrate 201 (i.e., the side of the device substrate 201 opposite to the first epitaxial layer 203) is thinned to expose the end of the second light-shielding structure 250 away from the interlayer dielectric layer 218. The thinning method includes, but is not limited to, chemical mechanical polishing, which is not specifically limited.

[0062] In one example, an image sensor includes multiple pixel units, each of which includes at least one photodiode region 231 and at least two transistors 215. The drain region 2152 of at least one transistor 215 in each pixel unit serves as a floating diffusion (FD), and each photodiode region 231 and floating diffusion are spaced apart in the thickness direction of the device substrate 201. By vertically arranging the photodiode region and floating diffusion region, the photodiode region area can be increased, thereby improving photoelectric conversion efficiency. The floating diffusion region is used to collect charge transferred from the photodiode region and convert it into a voltage signal for readout circuit processing, which is a key part of the process.

[0063] In one example, if Figure 20 As shown, a passivation layer 221 is formed on the side of the device substrate 201 facing away from the first isolation layer 210. Passivation layer 221 covers the surface of the device substrate 201. Exemplary materials for passivation layer 221 include, but are not limited to, silicon dioxide or silicon oxynitride. Methods for forming passivation layer 221 include, but are not limited to, PECVD (plasma-enhanced chemical vapor deposition) or ALD (atomic layer deposition). The passivation layer helps reduce electrical crosstalk between adjacent pixels and reduces parasitic capacitance by optimizing the electrical properties of the metal layer, thereby improving signal transmission efficiency and image clarity.

[0064] In one example, if Figure 20As shown, a plurality of grid structures 222 are formed on the passivation layer 221 , grid openings 223 are formed between each grid structure 222 , and a grid structure 222 is disposed between adjacent pixel units. Specifically, a grid material layer is first formed on the passivation layer 221. The grid material layer may be made of, but is not limited to, tungsten (W), nickel (Ni), or titanium (Ti). Methods for forming the grid material layer include, but are not limited to, molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), and laser ablation deposition (LAD). Next, a patterned photoresist layer is formed on the grid material layer. The patterned photoresist layer defines the region and position of the grid structure 222. The grid material layer is etched using the patterned photoresist layer as a mask to form a grid structure 222 between adjacent pixel units. A grid opening 223 is formed between each grid structure 222, exposing the surface of the passivation layer 221. The photoresist layer is then removed. Etching the grid material layer may be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, which are not specifically limited. The grid structure can enhance image performance by suppressing optical crosstalk.

[0065] In one example, if Figure 21 As shown, a color filter layer 224 is embedded in each grille opening 223. The primary function of the color filter layer 224 is to separate incident light by color (i.e., wavelength), ensuring that each pixel receives only light of a specific color (typically one of red, green, and blue). This is the foundation for a color image sensor to generate color images. Specifically, the color filter layer material can be deposited in each grille opening 223 using methods such as spin coating or inkjet printing. After a baking process to ensure stability and optical performance, the color filter layer 224 embedded in the grille opening 223 is formed. Materials for the color filter layer 224 include, but are not limited to, dye-based resins, pigment-based resins, or inorganic materials.

[0066] In one example, if Figure 22As shown, multiple microlenses 226 are formed on the color filter layer 224. Each microlens 226 corresponds to a plurality of pixel units, for example, one pixel unit corresponds to one or more microlenses 226. Before forming the microlenses 226, an anti-reflection layer 225 is also formed on the color filter layer 224. Exemplarily, the anti-reflection layer 225 comprises, but is not limited to, silicon dioxide or silicon nitride. Processes for forming the anti-reflection layer 225 include, but are not limited to, PECVD (plasma-enhanced chemical vapor deposition) and atomic layer deposition (ALD). When light enters from one medium into another (for example, from a microlens into a color filter layer), if the refractive indices differ significantly, reflection loss occurs. By optimizing the refractive index and thickness of the anti-reflection layer, this interface reflection loss can be effectively reduced, thereby increasing the amount of effective light reaching the photodiode. By reducing reflection loss, more incident light can be effectively utilized by the image sensor, directly improving the image sensor's quantum efficiency and low-light performance. The anti-reflection layer also acts as a transition layer, providing a smooth surface for the microlenses and facilitating fabrication. In other examples, the anti-reflection layer may not be formed, which is not particularly limited.

[0067] Finally, a plurality of microlenses 226 are formed on the color filter layer 224. Specifically, first, a layer of photosensitive material suitable for forming microlenses (typically a positive photoresist or high-temperature resin, etc.) is coated on the anti-reflective layer 225. A patterned photoresist layer is formed on the photosensitive material layer. The patterned photoresist layer defines the area and position of the microlenses 226. The photosensitive material layer is etched using the patterned photoresist layer as a mask to form the basic structure of the microlenses. Second, the photoresist is heated to a specific temperature so that the remaining photoresist melts and, due to surface tension, naturally forms the desired hemispherical or nearly spherical microlens structure. Finally, the formed microlens structure is further cured, such as with UV curing or annealing, to form the final microlenses 226. Microlenses focus incident light, allowing more light to directly enter the photodiode, thereby compensating for this loss, improving light utilization, enhancing signal quality, and improving image quality.

[0068] It is worth mentioning that the above steps are only examples, and the order of the above steps can be adjusted without conflict.

[0069] At this point, the process steps of the method for preparing an image sensor according to an embodiment of the present application have been completed. It can be understood that the method for preparing an image sensor in this embodiment not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the preparation method of this embodiment.

[0070] In summary, the preparation method of the image sensor of the present application can effectively prevent the latch-up effect between the source and drain of the transistor and avoid crosstalk between the photodiode region and the floating diffusion region by forming a first isolation layer and a shading structure between the photodiode region and the floating diffusion region respectively. At the same time, through the second shading structure, crosstalk between different pixels is effectively avoided, thereby improving the quality of the image sensor.

[0071] The present application also provides an image sensor, which can be prepared by the method of the aforementioned embodiment 1, or can also be prepared by other suitable preparation methods.

[0072] The image sensor provided by the present application can effectively prevent the latch-up effect between the source and drain of the transistor and avoid crosstalk between the photodiode region and the floating diffusion region by forming a first isolation layer and a shading structure between the photodiode region and the floating diffusion region respectively. At the same time, through the second shading structure, crosstalk between different pixels is effectively avoided, thereby improving the quality of the image sensor.

[0073] Although a number of embodiments have been described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts disclosed herein. More particularly, various modifications and changes may be made to the arrangements and / or component parts of the subject matter within the scope of the present disclosure, the accompanying drawings, and the appended claims. In addition to modifications and changes to the component parts and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A method for preparing an image sensor, characterized in that: include: Providing a device substrate, and sequentially forming a photodiode layer, a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer on the device substrate; forming a plurality of support pillars penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, the photodiode layer and extending into the device substrate; forming at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer, and the photodiode layer; Using the release groove as a release channel, etching and removing the first sacrificial layer to form a first cavity between the first epitaxial layer and the photodiode layer, and etching and removing the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer; forming a first isolation layer in the first cavity, and forming a first light shielding structure in the second cavity; removing the support pillar to form an isolation trench, and forming a second light shielding structure in the isolation trench; forming a plurality of transistors on the second epitaxial layer, each of the transistors comprising a drain region formed in the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors; A supporting substrate is provided, and the supporting substrate and the interlayer dielectric layer are bonded together.

2. The preparation method according to claim 1, wherein The image sensor includes a plurality of pixel units, each of the pixel units includes at least one photodiode region and at least two transistors, and the second light shielding structure is further provided between any two adjacent transistors in each of the pixel units.

3. The preparation method according to claim 1, wherein The forming of the first isolation layer in the first cavity and the forming of the first light shielding structure in the second cavity comprises: Depositing an isolation material layer to form a first isolation layer in the first cavity, wherein the first isolation layer completely fills the first cavity, and further depositing the isolation material layer on a surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering a surface of the second epitaxial layer facing the first epitaxial layer, and further depositing the isolation material layer on a surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering a surface of the first epitaxial layer facing the second epitaxial layer; A first light shielding layer is deposited to fill a portion of the second cavity between the second isolation layer and the third isolation layer. The first light shielding structure includes the first isolation layer, the second isolation layer and the first light shielding layer.

4. The preparation method according to claim 3, wherein The isolation material layer is also deposited on the sidewalls of the release groove, and the first light shielding layer completely fills the release groove.

5. The preparation method according to claim 1, wherein After forming the second light shielding structure and before forming the plurality of transistors, the manufacturing method further includes: forming a plurality of first conductive plugs sequentially penetrating the second epitaxial layer, the first light-shielding structure, the first epitaxial layer, and the first isolation layer, wherein the plurality of first conductive plugs are arranged at intervals, and each of the first conductive plugs is electrically connected to a photodiode region in the photodiode layer; and The preparation method further includes the step of forming a plurality of conductive interconnect structures in the interlayer dielectric layer, wherein each of the conductive interconnect structures is electrically connected to at least one of the first conductive plugs and a drain region of at least one of the transistors.

6. The preparation method according to claim 5, wherein The first conductive plug is further extended along the first direction, wherein the image sensor includes a plurality of pixel units, each of the pixel units includes at least one photodiode region and at least two transistors, The second light shielding structure is provided between two adjacent pixel units in the second direction, and the second light shielding structure is also extended along the first direction, and the first direction is perpendicular to the thickness direction of the device substrate; Each of the release grooves is disposed between two adjacent pixel units in the first direction, and the release groove further extends along the second direction; The first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other, the drain region of at least one transistor of each pixel unit is used as a floating diffusion region, and the floating diffusion region and the photodiode region of each pixel unit are spaced apart in the thickness direction of the device substrate.

7. The preparation method according to claim 1, wherein After bonding the support substrate and the interlayer dielectric layer, the method further includes: The side of the device substrate opposite to the first epitaxial layer is thinned to expose an end of the second light-shielding structure away from the interlayer dielectric layer.

8. The preparation method according to claim 1, wherein The forming of a second light shielding structure in the isolation trench comprises: forming a fourth isolation layer on the sidewalls and bottom of the isolation trench; A second light shielding layer is deposited to fill the isolation trench, and the second light shielding structure includes the fourth isolation layer and the second light shielding layer.

9. The preparation method according to claim 8, wherein Also includes: forming a passivation layer on a side of the device substrate facing away from the first isolation layer; A plurality of grid structures are formed on the passivation layer, wherein a grid structure is provided between adjacent pixel units, and grid openings are formed between adjacent grid structures, wherein the grid openings expose the surface of the passivation layer; embedding a color filter layer in the grille opening; A plurality of micro lenses are formed on the color filter layer, and the plurality of micro lenses correspond to the plurality of pixel units.

10. An image sensor, characterized in that: The method is prepared according to any one of claims 1 to 9.

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