Large-size n-type silicon wafer for bc battery and method of manufacturing the same and bc battery

Abstract

The present application relates to the technical field of photovoltaic cells, in particular to a large-size N-type silicon wafer for BC cells, a preparation method of the large-size N-type silicon wafer and a BC cell. The size of the large-size N-type silicon wafer is greater than or equal to 230mm*230mm, and the thickness is 90-130μm. The edge of the large-size N-type silicon wafer is circularly chamfered, and the edge is wrapped with a SiN x layer; the large-size N-type silicon wafer comprises a central region and an edge region surrounding the central region. The content of the doping element antimony in the edge region is less than or equal to 1*10 15 atoms / cm 3 ; the content of the doping element antimony in the central region is 1*10 16 -5*10 16 atoms / cm 3 . By setting the edge circular chamfer and wrapping the SiN x layer and the low-doped edge, the mechanical strength can be ensured, the fragment rate can be reduced, the edge carrier recombination can be reduced, the open-circuit voltage can be improved, and the cell power output can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic cells, in particular to a large-size N-type silicon wafer for BC cells and a preparation method thereof and a BC cell. BACKGROUND

[0002] Back Contact (BC) solar cells, referred to as BC cells, are a kind of high-efficiency solar cells that reduce the loss of light blocking on the front surface by placing all electrodes on the back surface. At present, the mainstream technologies of BC cells include Interdigitated Back Contact (IBC) and Heterojunction Back Contact (HBC), and the core material is usually an N-type silicon wafer.

[0003] Conventional N-type silicon wafers are one of the core materials of photovoltaic cells, which form an N-type semiconductor by doping elements such as phosphorus (P) or arsenic (As), and have advantages such as high minority carrier lifetime and low light-induced degradation (LID). In the prior art, the typical characteristics of N-type silicon wafers are as follows:

[0004] Structural design: single crystal silicon or polycrystalline silicon substrate is used, which is prepared by the Czochralski method (CZ) or the zone melting method (FZ), and the thickness is usually 150-200 μm, and the size is mainly M2 (156.75 mm x 156.75 mm) or G1 (158.75 mm x 158.75 mm).

[0005] Doping process: N-type layer is formed by phosphorus diffusion or ion implantation, and the surface is covered with a passivation layer.

[0006] Cell application: mainly used for TOPCon, HJT and other high-efficiency cell structures, and the highest conversion efficiency in the laboratory is about 24%-25%.

[0007] However, the N-type silicon wafer used in the current BC cell has the following limitations: the mainstream silicon wafer size is 182 mm x 182 mm or 210 mm x 210 mm, and the thickness is about 160-180 μm, and increasing the size will face the problem of insufficient mechanical strength. After increasing the size of the silicon wafer (such as G12, 210 mm x 210 mm), thinning (<150 μm) easily leads to an increase in the chip rate, making it difficult to increase the size.

[0008] Therefore, the present application is proposed. SUMMARY

[0009] The first object of the present application is to provide a large-size N-type silicon wafer for BC cells, and the present application develops an N-type silicon wafer with a thickness of 90-130 μm and a size of ≥230 mm x 230 mm, which is characterized by setting an edge circular arc chamfer and wrapping SiN xThe layer and the edge low-doping (the edge region antimony doping content is less than the center region antimony doping content) can reduce the edge carrier recombination, improve the open circuit voltage (Voc) and improve the battery power output while ensuring the mechanical strength and reducing the fragment rate. The problem that the mechanical strength is insufficient to cause the fragment rate to rise when the size of the existing N-type silicon wafer for the BC battery is increased is solved.

[0010] The second object of the present application is to provide a preparation method of a large-size N-type silicon wafer for a BC battery.

[0011] The third object of the present application is to provide a BC battery.

[0012] In order to achieve the above objects of the present application, the following technical solutions are adopted:

[0013] The present application first provides a large-size N-type silicon wafer for a BC battery, the size of the large-size N-type silicon wafer is ≥ 230mm×230mm, the thickness of the large-size N-type silicon wafer is 90-130μm, the edge of the large-size N-type silicon wafer is a circular arc chamfer, and the edge of the large-size N-type silicon wafer is wrapped with a SiN x layer; the large-size N-type silicon wafer comprises a center region and an edge region surrounding the center region, the content of the doping element antimony in the edge region is ≤1×10 15 atoms / cm 3 ; the content of the doping element antimony in the center region is 1×10 16 -5×10 16 atoms / cm 3 .

[0014] Further, the radius of the circular arc chamfer is 0.3-1.5mm.

[0015] Further, the width of the edge region is 2-4mm.

[0016] Further, the thickness of the SiN x layer is 80-200nm.

[0017] Further, the resistivity of the edge region is ≥10Ω·cm, and the resistivity of the center region is 0.5-3Ω·cm.

[0018] Further, the radial resistivity fluctuation of the large-size N-type silicon wafer is <5%.

[0019] Further, the front surface of the large-size N-type silicon wafer has a front surface passivation layer, the front surface passivation layer comprises an Al2O3 / SiN x stack; the Al2O3 / SiN xThe thickness of the Al2O3 layer in the stack is 8-10 nm, and the thickness of the SiN layer in the stack is 60-80 nm. x The thickness of the SiN layer in the stack is 60-80 nm. x The thickness of the SiN layer in the stack is 60-80 nm.

[0020] Further, the back surface of the large-size N-type silicon wafer has a back surface passivation layer, and the back surface passivation layer comprises SiO2 / polysilicon / SiN x The thickness of the SiO2 layer in the stack is 1.9-2.1 nm, and the thickness of the polysilicon layer in the stack is 149-151 nm. x The thickness of the SiO2 layer in the stack is 1.9-2.1 nm, and the thickness of the polysilicon layer in the stack is 149-151 nm. x The thickness of the SiO2 layer in the stack is 1.9-2.1 nm, and the thickness of the polysilicon layer in the stack is 149-151 nm. x The thickness of the SiN layer in the stack is 99-101 nm. x The thickness of the SiN layer in the stack is 99-101 nm. 20 The thickness of the SiN layer in the stack is 99-101 nm. 3 The thickness of the SiN layer in the stack is 99-101 nm.

[0021] The application further provides a preparation method of the large-size N-type silicon wafer for the BC battery, and the preparation method comprises the following steps: (a) preparing a single crystal silicon by a Czochralski method, wherein a doping element comprises antimony, and a single crystal silicon rod is obtained; (b) cutting the single crystal silicon rod into a wafer, and then performing surface treatment to obtain a silicon wafer; (c) forming a front surface passivation layer and a back surface passivation layer on the front surface and the back surface of the silicon wafer respectively; (d) performing selective laser doping on the back surface passivation layer to form a selective emitter; and (e) forming a circular arc chamfer on the edge of the silicon wafer by laser, and then wrapping a SiN x layer on the edge by plasma enhanced chemical vapor deposition.

[0022] Further, in step (a), the Czochralski method comprises a magnetic field assisted Czochralski method, and the axial temperature gradient of the magnetic field assisted Czochralski method is 10-15 ℃ / cm.

[0023] Further, in step (a), during the preparation of the single crystal silicon by the Czochralski method, the growth rate of the single crystal silicon is 1.2-1.5 mm / min.

[0024] Further, in step (a), during the preparation of the single crystal silicon by the Czochralski method, the pulling speed of the crystal is 1.3-1.8 mm / min.

[0025] Further, in step (a), the flow rate of argon is 80-100 L / min during the preparation of the single crystal silicon by the Czochralski method.

[0026] Further, in step (a), the doping gas mask technology is used during the preparation of the single crystal silicon by the Czochralski method, SbH3 is used as the dopant, the antimony doping concentrations of the edge region and the center region are controlled respectively, and the gas flow rate of the SbH3 is adjusted through resistivity monitoring and / or photoluminescence detection; wherein the method of resistivity monitoring comprises: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%; the method of photoluminescence detection comprises: identifying the low-lifetime region caused by antimony aggregation through online PL imaging, and controlling the threshold value to be less than 500 μs.

[0027] Further, in step (a), the He+ is further implanted by low-temperature ion implantation during the preparation of the single crystal silicon by the Czochralski method. + to form a nanocavity layer; wherein the dose of He+ is 1×1011 ions / cm2, and the energy is 50-60 keV. + 14 14 2

[0028] Further, in step (b), the diamond wire used for cutting comprises a resin binder diamond wire, and the diameter of the diamond wire is 50-80 μm.

[0029] Further, in step (b), the cutting speed is 1.2-1.5 m / s.

[0030] Further, in step (b), the cooling liquid used for cutting comprises polyethylene glycol, and the cooling liquid further contains silicon carbide abrasive and / or nano-SiO2 particles, wherein the median particle size of the silicon carbide abrasive is 3-5 μm, and the median particle size of the nano-SiO2 particles is 80-100 nm.

[0031] Further, in step (b), the surface treatment method comprises: polishing, chemical thinning and texturing in sequence; wherein the polishing method comprises: double-sided chemical mechanical polishing, and the polishing is performed to a surface roughness Ra of less than 0.5 nm; the chemical thinning method comprises: using a mixed acid solution of HF and HNO3 to perform isotropic etching on both sides to remove the cutting damage layer; and the texturing method comprises: using laser etching to form an inverted pyramid texturing structure on the front side, wherein the height of the inverted pyramid texturing structure is 23-25 μm.

[0032] Further, in step (c), the front passivation layer comprises Al2O3 / SiN x ​​​​Stack, the back passivation layer comprises SiO2 / polysilicon / SiN x Stack.

[0033] Further, in step (d), the method of selective laser doping comprises: selectively ablating part of the back passivation layer by pulsed laser and doping phosphorus to form N + doped region; wherein the wavelength of the pulsed laser is 530-540 nm, the energy density of the pulsed laser is 2.8-3 J / cm 2 , and the scanning speed of the pulsed laser is 5-6 m / s.

[0034] Further, in step (e), during the process of plasma enhanced chemical vapor deposition, the partition pressure is controlled to be 0.1-0.3 bar.

[0035] Further, after step (e), there is further step (f) of preparing staggered point contact back electrode: using ultraviolet laser to open a plurality of staggered grooves on the back of the silicon wafer, and then sequentially performing copper electroplating and silver covering to form copper-plated silver electrode material. Wherein the wavelength of the ultraviolet laser is 350-360 nm, the pulse width is 8-10 ps, and the energy is 0.8-1 μJ. The width of each groove is 20-32 μm, the length-width ratio of each groove is 2:1, and the distance between adjacent two grooves is 1.4-1.6 mm. The electroplating solution used for copper electroplating is a mixed solution of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixed solution of CuSO4, H2SO4 and additives is 150-250 g / L, and the concentration of H2SO4 in the mixed solution of CuSO4, H2SO4 and additives is 50-100 g / L; the additives include PEG and a chlorine source, the chlorine source includes HCl and / or NaCl, the concentration of PEG in the mixed solution of CuSO4, H2SO4 and additives is 0.05-0.5 g / L, and the concentration of Cl - in the mixed solution of CuSO4, H2SO4 and additives is 0.03-0.1 g / L. The current density of copper electroplating is 1.9-2.1 A / dm 2 , and the time of copper electroplating is 15-15.5 min. The silver covering method comprises: using immersion plating method to immerse the silicon wafer in a mixed solution of AgNO3 and complexing agent to perform displacement reaction; the complexing agent includes ammonia, the concentration of AgNO3 in the mixed solution of AgNO3 and complexing agent is 0.3-0.35 mol / L, and the molar ratio of NH3 to Ag + in the mixed solution of AgNO3 and complexing agent is ≥2:1.

[0036] The application further provides a BC battery comprising the large-size N-type silicon wafer for the BC battery.

[0037] Compared with the prior art, the application has the following beneficial effects:

[0038] (1) The application develops an N-type silicon wafer with a thickness of 90-130 mu m and a size of greater than or equal to 230 mm*230 mm, which is wrapped with SiN x by setting an edge circular arc chamfer, and the edge is lowly doped (the antimony doping content of the edge region is less than that of the central region), so that the mechanical strength is ensured, the fragment rate is reduced, the edge carrier recombination is reduced, the open-circuit voltage (Voc) is improved, and the battery power output is improved.

[0039] (2) The application reduces the production cost of the N-type silicon wafer, the silicon wafer size is increased by about 12%, the silicon wafer area is increased by about 80%, the silicon material cost per unit power is reduced, the module power is increased by 10%-15%, the single-cell battery power is increased to 8.5 W (the traditional 210 mm silicon wafer is 7.2 W), and the unit power cost is reduced by 18%-22%.

[0040] (3) The application sets the front passivation layer as Al2O3 / SiN x , and the surface recombination rate can be reduced to less than 20 cm / s, wherein the Al2O3 / SiN x is set on the front surface, the fixed negative charge density is greater than 1*10 12 cm -2 -2, and the SiO2 / polysilicon / SiN x is set on the back surface to realize tunnel passivation contact (TOPCon). In addition, the application sets the front passivation layer with a specific composition and thickness and the back passivation layer with a specific composition and thickness, and the surface recombination rate can be reduced to less than 10 cm / s.

[0041] (4) The application designs the staggered point contact electrode on the back surface, and the contact area ratio is less than or equal to 5%, so that the metal recombination can be reduced.

[0042] (5) The application uses the transverse magnetic field to suppress the melt convection, so that the stripe defects caused by antimony doping can be reduced; the axial temperature gradient of the magnetic field assisted Czochralski method and the growth rate of the single crystal silicon are controlled, so that the longitudinal resistivity uniformity can be ±1.8%; the pulling speed is reduced, so that the radial segregation of antimony can be reduced; the argon flow rate is increased, so that the doping fluctuation caused by the volatilization of antimony can be suppressed; the resistivity monitoring can improve the resistivity uniformity; and the photoluminescence detection can improve the antimony doping uniformity.

[0043] (6) the present application can reduce the saw mark depth (<8 μm) by controlling the material, diameter and cutting speed of the diamond wire; by controlling the diameter of the diamond wire and the composition of the cooling liquid, the cutting loss can be controlled to be ≤90 μm, the cutting loss is reduced by 20%, and the comprehensive production cost is reduced by 15%; the low-cost cutting and polishing (surface treatment) process is adopted, and the silicon wafer yield is improved to more than 98%. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0045] Figure 1 A top view of a large-size N-type silicon wafer provided by the present application is provided.

[0046] Figure 2 A schematic diagram of the layer structure of the large-size N-type silicon wafer provided by the present application is provided. DETAILED DESCRIPTION

[0047] The technical solutions of the present application will be described clearly and completely in combination with the drawings and specific embodiments below, but those skilled in the art will understand that the following described embodiments are part of the embodiments of the present application, not all the embodiments, and should not be regarded as limiting the scope of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. The specific conditions are not specified in the embodiments, and the conventional conditions or the conditions recommended by the manufacturer are used. The reagents or instruments used are not specified by the manufacturer, and are conventional products that can be purchased on the market.

[0048] In a first aspect, the present application provides a large-size N-type silicon wafer for a BC battery (Back Contact (BC) solar cell), which aims to improve the battery conversion efficiency, reduce the production cost, and enhance the mechanical properties of the silicon wafer. Among them, the size of the large-size N-type silicon wafer is ≥230 mm x 230 mm (i.e. length x width), the thickness of the large-size N-type silicon wafer is 90-130 μm, the edge of the large-size N-type silicon wafer is a circular arc chamfer, and the edge of the large-size N-type silicon wafer is wrapped with SiN x layer.

[0049] The large-size N-type silicon wafer has a size of, for example, 230 mm x 230 mm (length x width), and a thickness of, for example, 90 μm, 100 μm, 110 μm, 120 μm or 130 μm.

[0050] The large-size N-type silicon wafer comprises a center region and an edge region surrounding the center region, wherein the content of the doped element antimony in the edge region is less than the content of the doped element antimony in the center region, in particular, the content of the doped element antimony in the edge region is ≤ 1 x 10 15 atoms / cm 3 , and the content of the doped element antimony in the center region is 1 x 10 16 ~ 5 x 10 16 atoms / cm 3 .

[0051] The content of the doped element antimony in the edge region may, for example, be 1 x 10 15 atoms / cm 3 , 9 x 10 14 atoms / cm 3 , 7 x 10 14 atoms / cm 3 , 5 x 10 14 atoms / cm 3 , 3 x 10 14 atoms / cm 3 or 1 x 10 14 atoms / cm 3 .

[0052] The content of the doped element antimony in the center region may also be 2 x 10 16 atoms / cm 3 , 3 x 10 16 atoms / cm 3 or 4 x 10 16 atoms / cm 3 .

[0053] The top view of the large-size N-type silicon wafer provided by the present application is shown in Figure 1 . As shown in Figure 1 , the edge region of the large-size N-type silicon wafer is provided with a SiN x layer, and the four inner corners of the edge region are circular arc corners.

[0054] The present application develops an N-type silicon wafer with a thickness of 90-130 μm and a size of ≥ 230 mm x 230 mm, by setting an edge circular arc chamfer and wrapping a SiN xThe layer and the edge low-doping (the edge region antimony doping content is less than the center region antimony doping content) can reduce the edge carrier recombination, improve the open circuit voltage (Voc) and improve the battery power output while ensuring the mechanical strength and reducing the fragment rate.

[0055] The present application reduces the production cost of N-type silicon wafer, the silicon wafer size increases by about 12%, the silicon wafer area increases by about 80%, the unit power silicon material cost is diluted, the component power is increased by 10%~15%, and the single cell power is increased to 8.5W (traditional 210mm silicon wafer is 7.2W).

[0056] In some specific embodiments, the fragment rate of the large-size N-type silicon wafer provided by the present application is less than 0.5% (230mm 2 <0.5%, preferably less than 0.05% (automatic line transmission), wherein the test method is vibration test (5~50Hz, 2h).

[0057] In some specific embodiments, the mechanical strength of the large-size N-type silicon wafer provided by the present application meets the four-point bending strength ≥550MPa (test method: ISO 14704 standard).

[0058] In some specific embodiments, the radius of the circular arc chamfer is 0.3~1.5mm, for example 0.5mm, 0.8mm, 1.0mm, 1.2mm or 1.4mm. This is conducive to reducing the edge fragment rate (less than 2%), improving the passivation film uniformity (deviation less than 10%), improving the laser grooving yield (95%~98%), reducing the component DH1000 attenuation (1.5%~2.0%), and reducing the battery Isc loss (0.2%~0.5%).

[0059] In some specific embodiments, the width of the edge region is 2~4mm, for example 2.3mm, 2.5mm, 2.8mm, 3.0mm, 3.3mm, 3.5mm or 3.8mm. This is conducive to improving the laser grooving yield (95%~98%), reducing the edge recombination current density (<5nA / cm 2 ), improving the passivation film uniformity (deviation less than 10%), reducing the component hidden crack rate (EL test) (<1.5%), and reducing the wafer (130μm) fragment rate (4%~6%).

[0060] In some specific embodiments, the thickness of the SiN x layer is 80~200nm, for example 100nm, 120nm, 150nm, 160nm or 180nm. This is conducive to reducing the average reflectivity (400~1100nm) (<3%), improving the minority carrier lifetime (1.2~1.5ms), improving the Voc, reducing the PID attenuation (96h) (<2%), and avoiding the wafer warping.

[0061] In some embodiments, the edge region has a resistivity ≥ 10 Ω·cm, such as 11 Ω·cm, 12 Ω·cm, 13 Ω·cm, 14 Ω·cm, 15 Ω·cm, 16 Ω·cm, 18 Ω·cm, or 20 Ω·cm; and the center region has a resistivity of 0.5-3 Ω·cm, such as 0.6 Ω·cm, 0.8 Ω·cm, 1 Ω·cm, 1.3 Ω·cm, 1.5 Ω·cm, 1.8 Ω·cm, 2 Ω·cm, 2.3 Ω·cm, or 2.6 Ω·cm. This is advantageous for reducing edge leakage current density (< 2 nA / cm 2 ), reducing Voc loss (< 5 mV), reducing laser contact resistance fluctuation (± 5%), reducing the rate of component hidden cracks (EL test) (< 1.5%), and reducing the rate of wafer (130 μm) chipping (2%-4%).

[0062] In some embodiments, the large-size N-type silicon wafer has a radial resistivity fluctuation < 5%. A low radial resistivity fluctuation, i.e., an improved resistivity uniformity.

[0063] In some embodiments, the large-size N-type silicon wafer has a front surface with a front passivation layer, the front passivation layer comprising an Al2O3 / SiN x stack (with the Al2O3 closer to the front surface of the large-size N-type silicon wafer). By providing the front passivation layer as an Al2O3 / SiN x stack, the surface recombination rate can be reduced to below 20 cm / s.

[0064] Further, the Al2O3 layer in the Al2O3 / SiN x stack has a thickness of 8-10 nm, such as 9 nm; and the SiN x layer in the Al2O3 / SiN x stack has a thickness of 60-80 nm, such as 65 nm, 70 nm, or 75 nm.

[0065] In some embodiments, the large-size N-type silicon wafer has a back surface with a back passivation layer, the back passivation layer comprising a SiO2 / polysilicon / SiN x stack (from the back surface of the large-size N-type silicon wafer outward, in order: SiO2 layer, polysilicon layer, and SiN x layer).

[0066] Further, the SiO2 layer in the SiO2 / polysilicon / SiN x stack has a thickness of 1.9-2.1 nm (ultra-thin, tunneling layer (allowing selective tunneling of carriers to the polysilicon layer), chemical passivation: saturating dangling bonds on the silicon surface, reducing interface state density), such as 2 nm.

[0067] The SiO2 / polysilicon / SiN x The thickness of the polysilicon layer in the stack (field effect passivation: high-doped polysilicon provides fixed charges, forms a back surface field (BSF), reduces recombination; carrier collection: as a contact layer, forms an ohmic contact with the metal electrode) is 149-151 nm, for example 150 nm.

[0068] The SiO2 / polysilicon / SiN x The SiN x The thickness of the layer (hydrogen atom (H) replenishment: H atoms are released during annealing, repairing the SiO2 / silicon interface defects; protective layer: prevents polysilicon from being oxidized or contaminated in subsequent processes (such as laser grooving)) is 99-101 nm, for example 100 nm.

[0069] The present application adopts a double-sided passivation structure: an Al2O3 / SiN x stack is arranged on the front side, and a fixed negative charge density >1×10 12 cm -2 ; and a SiO2 / polysilicon / SiN x stack is arranged on the back side, so that a tunnel passivation contact (TOPCon) can be achieved.

[0070] Furthermore, by arranging a front passivation layer with a specific composition and thickness and a back passivation layer with a specific composition and thickness, the surface recombination velocity can be reduced to below 10 cm / s (preferably 8 cm / s). The problem of limited passivation effect of the existing passivation layer on N-type silicon wafers, resulting in high surface recombination velocity (SRV) (higher than 100 cm / s) and carrier recombination loss is solved.

[0071] Further, the back passivation layer also has a selective emitter, and the concentration of phosphorus elements in the selective emitter is ≥1×10 20 atoms / cm 3 , for example 2×10 20 atoms / cm 3 , 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 , or 5×10 20 atoms / cm 3 . This is conducive to reducing the contact resistance (<1 mΩ·cm 2 ), reducing the surface recombination velocity (<1×10 3 cm / s), reducing the Voc loss (5-10 mV), obtaining a wide laser process window (high energy tolerance), and adapting to battery types BC / TOPCon-IBC.

[0072] Further, the selective emitter on the back passivation layer is further provided with an interlaced point contact back electrode, the material of the interlaced point contact back electrode is copper plated with silver, the copper plated with silver includes a copper layer and a silver layer covering the copper layer. The thickness of the copper layer is 19-21 μm, for example, 20 μm; the thickness of the silver layer is 0.8-1 μm, for example, 0.9 μm; the total area of the copper plated with silver accounts for ≤5%, for example, 4%, 3%, 2% or 1% of the area of the back passivation layer.

[0073] The use of copper plated with silver and the control of the thickness of the copper layer and the silver layer are conducive to the control of the material cost, the reduction of the contact resistance, the improvement of the anti-PID performance (decay <2%), the reduction of the silicon wafer warpage, the adaptation to large size, the reduction of the fragment rate and the good process compatibility (electroplating / laser transfer).

[0074] The present application moves all the electrodes to the back surface, and the front surface is not shielded by the gate lines, so that the light absorption efficiency can be improved by 6%-8% (light absorption loss ≤2%). The problem of low light absorption efficiency caused by the loss of incident light (about 5%-8%) due to the front surface metal gate line shielding is solved.

[0075] In addition, the back surface of the present application is designed with an interlaced point contact electrode, and the contact area accounts for ≤5%, which can reduce metal compounding.

[0076] The layer structure diagram of the large-size N-type silicon wafer provided by the present application is shown in Figure 2 As can be seen from the figure, the large-size N-type silicon wafer includes a front passivation layer, an N-type silicon wafer body, a back passivation layer, a selective emitter and an interlaced point contact back electrode which are sequentially stacked.

[0077] In some specific embodiments, the cell efficiency of the large-size N-type silicon wafer provided by the present application is ≥24.8% (IBC structure, AM1.5G), wherein the test method is IV test+EL imaging.

[0078] In some specific embodiments, the minority carrier lifetime of the large-size N-type silicon wafer provided by the present application satisfies: bulk lifetime >2ms, surface SRV <5cm / s, wherein the test method is QSSPC+microwave photoconductance decay.

[0079] In a second aspect, the present application provides a preparation method of the above-mentioned large-size N-type silicon wafer for BC cells, which includes the following steps:

[0080] (a) preparing a single crystal silicon by a Czochralski method, wherein the doping element includes antimony, to obtain a single crystal silicon rod.

[0081] (b) after the single crystal silicon rod is cut into a wafer, performing surface treatment to obtain a silicon wafer.

[0082] (c) forming a front passivation layer and a back passivation layer on the front side and the back side of the silicon wafer respectively.

[0083] (d) performing selective laser doping on the back passivation layer to form a selective emitter for selective contact.

[0084] In the step (d), the laser doping is low-temperature doping, which can reduce the wafer warpage, enhance the thermal stability, and improve the yield to more than 98%. The problems of wafer warpage, insufficient thermal stability, and influence on the reliability of subsequent battery components caused by high-temperature processes (such as diffusion and annealing) are solved.

[0085] In some specific embodiments, the wafer warpage of the large-size N-type silicon wafer prepared by the method is less than 0.1 mm / m.

[0086] (e) forming a circular chamfer on the edge of the silicon wafer by laser, and then wrapping SiN layer on the edge by plasma enhanced chemical vapor deposition (PECVD) to prevent electric leakage. x

[0087] The above method can prepare a large-size N-type silicon wafer, which can reduce the edge carrier recombination, improve the open-circuit voltage (Voc), and improve the battery power output while ensuring the mechanical strength and reducing the wafer breakage rate.

[0088] In the step (a), the Czochralski method includes a magnetic field assisted Czochralski method (MCZ method), and the axial temperature gradient of the magnetic field assisted Czochralski method is 10-15℃ / cm, for example, 11℃ / cm, 12℃ / cm, 13℃ / cm, or 14℃ / cm.

[0089] The present application adopts a transverse magnetic field (MCZ) to suppress melt convection, which can reduce the stripe defects caused by antimony doping.

[0090] In the step (a), the growth rate of the single crystal silicon is 1.2-1.5 mm / min, for example, 1.3 mm / min or 1.4 mm / min, during the process of preparing the single crystal silicon by the Czochralski method.

[0091] The present application can realize longitudinal resistivity uniformity ±1.8% by controlling the axial temperature gradient of the magnetic field assisted Czochralski method and the growth rate of the single crystal silicon.

[0092] In the step (a), the pulling speed of the single crystal silicon is 1.3-1.8 mm / min, for example, 1.4 mm / min, 1.5 mm / min, 1.6 mm / min, or 1.7 mm / min, during the process of preparing the single crystal silicon by the Czochralski method. The present application can reduce the radial segregation of antimony by reducing the pulling speed. ​

[0093] In some specific embodiments, in step (a), the flow rate of argon gas during the process of preparing the single crystal silicon by the Czochralski method is 80-100 L / min, for example, 85 L / min, 90 L / min or 95 L / min. By increasing the flow rate of argon gas, the present application can inhibit the fluctuation of doping caused by the volatilization of antimony.

[0094] In some specific embodiments, in step (a), the process of preparing the single crystal silicon by the Czochralski method adopts a doping gas mask technology, and SbH3 is used as the dopant to control the antimony doping concentration of the edge region and the center region, respectively, and the flow rate of the SbH3 gas is adjusted through resistivity monitoring and / or photoluminescence (PL) detection.

[0095] The method of resistivity monitoring comprises: using a four-point probe scanner (resolution 1 mm) to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%, preferably less than 2%. In this way, the resistivity uniformity can be improved, and the problem of poor resistivity uniformity and radial resistivity fluctuation exceeding 5% in the prior art can be solved.

[0096] Further, the method of photoluminescence detection comprises: identifying the low lifetime region caused by the aggregation of antimony through online PL imaging, and controlling the threshold value to be less than 500 μs. In this way, the uniformity of antimony doping can be improved, and the problem of poor doping uniformity and uneven efficiency distribution in the edge region of the large-size silicon wafer in the prior art can be solved.

[0097] In some specific embodiments, in step (a), during the process of preparing the single crystal silicon by the Czochralski method, He + is further implanted by low-temperature ion implantation to form a nanocavity layer to inhibit the crack propagation through the pinning effect. The dose of He + is 1×10 14 ~1.01×10 14 ions / cm 2 , and the energy is 50-60 keV.

[0098] In some specific embodiments, in step (b), the diamond wire used for cutting comprises a resin binder diamond wire, and the diameter of the diamond wire is 50-80 μm, for example, 55 μm, 60 μm, 65 μm, 70 μm or 75 μm.

[0099] In some specific embodiments, in step (b), the cutting speed is 1.2-1.5 m / s, for example, 1.3 m / s or 1.4 m / s.

[0100] By controlling the material, diameter and cutting speed of the diamond wire, the present application can reduce the saw mark depth (<8 μm).

[0101] In some specific embodiments, in step (b), the cooling liquid used for cutting comprises polyethylene glycol, and the cooling liquid further comprises silicon carbide abrasive and / or nano-SiO2 particles. The use of nano-SiO2 particles can reduce the brittle edge collapse of antimony-doped silicon.

[0102] The median particle size of the silicon carbide abrasive is 3-5 μm, for example 4 μm, and the median particle size of the nano-SiO2 particles is 80-100 nm, for example 85 nm, 90 nm or 95 nm.

[0103] The present application can control the cutting loss to be ≤90 μm by controlling the wire diameter of the diamond wire and the composition of the cooling liquid, reduce the cutting loss by 20%, and reduce the overall production cost by 15%, thereby further reducing the production cost of N-type silicon wafers, and directly interfacing with the existing BC battery production line without the need for equipment modification. The problem of high production cost caused by high cutting loss rate of large-size silicon wafers is solved.

[0104] In some specific embodiments, in step (b), the surface treatment method comprises polishing, chemical thinning and texturing in sequence. The polishing method comprises double-sided chemical mechanical polishing (CMP), and the polishing is performed to a surface roughness Ra<0.5 nm. The chemical thinning method comprises isotropic etching of both sides using a mixed acid solution of HF and HNO3 (the molar ratio of HF to HNO3 in the mixed acid solution is preferably 1:3), to remove the cutting damage layer, wherein the thickness uniformity is ±1.5 μm. The texturing method comprises forming a reverse pyramid texturing structure on the front side by laser etching, wherein the height of the reverse pyramid texturing structure is 23-25 μm, for example 24 μm.

[0105] The present application uses a low-cost cutting and polishing (surface treatment) process to improve the silicon wafer yield to more than 98%. The problem of low yield of large-size silicon wafers in the prior art and the need for high-precision equipment with high cost is solved.

[0106] In some specific embodiments, in step (c), the front side passivation layer can improve the surface passivation effect, and comprises an Al2O3 / SiN x stack.

[0107] In some specific embodiments, in step (c), the back side passivation layer comprises a SiO2 / polysilicon / SiN x stack, which can realize tunnel passivation contact (TOPCon).

[0108] In some embodiments, in step (d), the method of selective laser doping comprises: selectively ablating a local portion of the back passivation layer by a pulsed laser, and doping phosphorus (for example, using a laser to open micron-level contact holes (laser grooving) on the back passivation layer, and then achieving local high-concentration doping (N + ) through a gas or liquid source (such as phosphine) to form a local heavily doped region (N + back surface field (BSF)).

[0109] The wavelength of the pulsed laser is 530-540 nm (use 530-540 nm pulsed laser to locally activate the antimony-doped region (n + ), and the contact resistance is <1 mΩ·cm 2 , while the minority carrier lifetime of the lightly doped bulk region is >1 ms, forming a selective emitter).

[0110] The energy density of the pulsed laser is 2.8-3 J / cm 2 , for example, 2.9 J / cm 2 .

[0111] The scanning speed of the pulsed laser is 5-6 m / s, for example, 5.5 m / s.

[0112] In some embodiments, in step (e), during the process of plasma-enhanced chemical vapor deposition, the partition pressure is controlled to be 0.1-0.3 bar, for example, 0.2 bar, to avoid local stress exceeding the limit.

[0113] In some embodiments, after step (e), the following step (f) is further included: preparing an interleaved point contact back electrode: using ultraviolet laser to open a plurality of grooves arranged in an interleaved manner on the back surface of the silicon wafer (to expose the N + region), and then sequentially performing copper electroplating and silver covering to form a copper-plated silver electrode material.

[0114] The wavelength of the ultraviolet laser is 350-360 nm, for example, 355 mm; the pulse width is 8-10 ps, for example, 9 ps; and the energy is 0.8-1 μJ, for example, 0.9 μJ.

[0115] Further, the width of each groove is 20-32 μm, for example, 23 μm, 25 μm, 28 μm, or 30 μm; the length to width ratio of each groove is 2:1; and the distance between adjacent two grooves is 1.4-1.6 mm, for example, 1.5 mm.

[0116] Further, the plating solution used for the copper electroplating is a mixture of CuSO4, H2SO4 and additives. The concentration of CuSO4 in the mixture of CuSO4, H2SO4 and additives is 150-250 g / L, for example, 160 g / L, 180 g / L, 200 g / L or 230 g / L. The concentration of H2SO4 in the mixture of CuSO4, H2SO4 and additives is 50-100 g / L, for example, 60 g / L, 70 g / L or 90 g / L. Further, the additives include PEG and a chlorine source, the chlorine source includes HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and additives is 0.05-0.5 g / L, for example, 0.1 g / L, 0.2 g / L, 0.3 g / L or 0.4 g / L; the concentration of Cl in the mixture of CuSO4, H2SO4 and additives is 0.03-0.1 g / L, for example, 0.05 g / L, 0.06 g / L or 0.08 g / L. The PEG includes PEG-8000, but is not limited thereto. -

[0117] The PEG (polyethylene glycol) as an inhibitor can form an adsorption layer with Cl - to slow down the deposition rate of Cu 2+ and improve the uniformity of the plating layer.

[0118] The Cl - forms a complex with PEG to enhance the inhibitory effect. If the concentration of Cl - is too low, PEG will be ineffective, and if the concentration of Cl - is too high, it may cause the plating layer to be rough.

[0119] Further, the current density of the copper electroplating is 1.9-2.1 A / dm 2 , for example, 2.0 A / dm 2 ; the time of the copper electroplating is 15-15.5 min.

[0120] Further, the method for covering silver includes: using the immersion plating method, immersing the silicon wafer in a mixed solution of AgNO3 and a complexing agent to perform a displacement reaction. The complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3-0.35 mol / L, for example, 0.31 mol / L, 0.32 mol / L or 0.34 mol / L; the molar ratio of NH3 to Ag + in the mixed solution of AgNO3 and the complexing agent is ≥ 2:1.

[0121] In some specific embodiments, the complexing agent can also use sodium thiosulfate, sodium citrate or EDTA (ethylenediaminetetraacetic acid).​

[0122] In a third aspect, the present application provides a BC battery comprising the large-size N-type silicon wafer for BC battery as described above.

[0123] The present application can achieve a laboratory conversion rate of more than 26.5% (the laboratory conversion rate of existing N-type silicon wafer such as G1 (158.75mm x 158.75mm) is less than or equal to 24.5%) and a mass production efficiency of more than 25% by optimizing the structure of large-size N-type silicon wafer and the preparation method thereof.

[0124] Embodiments of the present application will be described in detail below with reference to examples, but those skilled in the art will understand that the following examples are only used to illustrate the present application and should not be regarded as limiting the scope of the present application. If the specific conditions are not specified in the examples, the conventional conditions or the conditions recommended by the manufacturer are used. If the manufacturers of the reagents or instruments are not specified, they are all conventional products that can be obtained by purchase in the market.

[0125] Example 1

[0126] The preparation method of the large-size N-type silicon wafer for BC battery provided in this example comprises the following steps:

[0127] (1) A single crystal silicon rod is prepared by a magnetic field assisted Czochralski method, wherein the doping element comprises antimony, and the axial temperature gradient of the magnetic field assisted Czochralski method is 13℃ / cm, the growth rate of the single crystal silicon is 1.3mm / min, the crystal pulling speed is 1.5mm / min, and the flow rate of argon is 90L / min. Specifically, a doping gas mask technology is used, SbH3 is used as a dopant, the antimony doping concentration of the edge region and the center region is controlled respectively, and the gas flow rate of SbH3 is adjusted by resistivity monitoring and photoluminescence detection. The method of resistivity monitoring comprises: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%. The method of photoluminescence detection comprises: identifying the low lifetime area caused by antimony aggregation by online PL imaging, and controlling the threshold value to be less than 500μs. In addition, during the preparation of the single crystal silicon, He + is implanted by low temperature ion implantation to form a nanocavity layer, wherein the dose of He + is 1×10 14 ions / cm 2 , and the energy is 55keV.

[0128] (2) The monocrystalline silicon rod is cut into a wafer by using resin-bonded diamond wire with a wire diameter of 60 μm, and then the wafer is subjected to surface treatment to obtain a silicon wafer. The cutting speed is 1.2 m / s. The cooling liquid used in the cutting process comprises polyethylene glycol and further comprises silicon carbide abrasive, and the median particle size of the silicon carbide abrasive is 5 μm. The surface treatment method comprises polishing, chemical thinning and texturing in sequence. The polishing method comprises double-sided chemical mechanical polishing to a surface roughness Ra<0.5 nm. The chemical thinning method comprises isotropic etching of both sides by using a mixed acid solution of HF and HNO3 (the molar ratio of HF to HNO3 is 1:3) to remove the cutting damage layer. The texturing method comprises forming a reverse pyramid texturing structure on the front side by laser etching, and the height of the reverse pyramid texturing structure is 23 μm.

[0129] (3) A front passivation layer and a back passivation layer are formed on the front side and the back side of the silicon wafer, respectively. The front passivation layer is an Al2O3 / SiN x stack, and the back passivation layer is a SiO2 / polysilicon / SiN x stack.

[0130] (4) The back passivation layer is selectively doped by laser, specifically, the local back passivation layer is selectively ablated by pulsed laser and doped with phosphorus to form an N + local heavily doped region to obtain a selective emitter. The wavelength of the pulsed laser is 532 nm, the energy density of the pulsed laser is 3 J / cm 2 , and the scanning speed of the pulsed laser is 5 m / s.

[0131] (5) The edge of the silicon wafer is formed into a circular arc chamfer by laser, and then a SiN x layer is wrapped around the edge by plasma-enhanced chemical vapor deposition. During the plasma-enhanced chemical vapor deposition process, the partition pressure is controlled to be 0.2 bar.

[0132] (6) An interlaced point contact back electrode is prepared: a plurality of grooves arranged in an interlaced manner are formed on the back side of the silicon wafer by using ultraviolet laser, wherein the wavelength of the ultraviolet laser is 355 nm, the pulse width is 10 ps, and the energy is 0.8 μJ; the width of each groove is 25 μm, the length-width ratio of each groove is 2:1, and the distance between adjacent two grooves is 1.5 mm. Then, copper electroplating and silver covering are performed in sequence to form a copper-plated silver electrode material. The electroplating solution used in the copper electroplating process comprises a mixture of CuSO4, H2SO4 and an additive; the concentration of CuSO4 in the mixture is 200 g / L, the concentration of H2SO4 is 50 g / L; the additive comprises PEG and a chlorine source, the chlorine source comprises HCl, the concentration of PEG in the mixture is 0.3 g / L, and the concentration of Cl -The concentration of AgNO3 in the mixed solution of AgNO3 and complexing agent is 0.05 g / L. The current density of copper electroplating is 2 A / dm 2 , and the time of copper electroplating is 15 min. The silver covering method comprises: using a dipping plating method, immersing the silicon wafer into a mixed solution of AgNO3 and complexing agent to perform a displacement reaction; the complexing agent comprises ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and complexing agent is 0.33 mol / L, and the molar ratio of NH3 to Ag + in the mixed solution of AgNO3 and complexing agent is ≥ 2:1.

[0133] The size of the large-size N-type silicon wafer prepared in the embodiment is 230 mm x 230 mm, and the thickness is 100 μm. The edge of the large-size N-type silicon wafer is circularly chamfered, the radius of the circular chamfer is 1 mm, and the edge of the large-size N-type silicon wafer is wrapped with a SiN x layer, and the thickness of the SiN x layer is 100 nm. The large-size N-type silicon wafer comprises a central region and an edge region surrounding the central region, the width of the edge region is 3 mm, the resistivity of the edge region is 10 Ω·cm, and the resistivity of the central region is 1.5 Ω·cm; the content of the doping element antimony in the edge region is 1 x 10 15 atoms / cm 3 ; and the content of the doping element antimony in the central region is 3 x 10 16 atoms / cm 3 . The radial resistivity fluctuation of the large-size N-type silicon wafer is < 5%. The front surface of the large-size N-type silicon wafer has a front surface passivation layer, and the front surface passivation layer is an Al2O3 / SiN x stack, the thickness of the Al2O3 layer in the Al2O3 / SiN x stack is 10 nm, and the thickness of the SiN x layer is 80 nm. The back surface of the large-size N-type silicon wafer has a back surface passivation layer, and the back surface passivation layer comprises a SiO2 / polysilicon / SiN x stack, the thickness of the SiO2 layer in the SiO2 / polysilicon / SiN x stack is 2 nm, the thickness of the polysilicon layer is 150 nm, and the thickness of the SiN x layer is 100 nm; the back surface passivation layer further has a selective emitter, and the concentration of phosphorus in the selective emitter is 1 x 10 20 atoms / cm 3 ; and the back surface passivation layer further has an interleaved point contact back electrode, and the material of the interleaved point contact back electrode is copper-plated silver, the copper-plated silver comprises a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 20 μm, and the thickness of the silver layer is 1 μm; the total area of the copper-plated silver accounts for 5% of the area of the back surface passivation layer.

[0134] Example 2

[0135] The method for preparing a large-size N-type silicon wafer for a BC battery comprises the following steps:

[0136] (1) A single crystal silicon rod is prepared by a magnetic field assisted Czochralski method, wherein the doping element comprises antimony, and the axial temperature gradient of the magnetic field assisted Czochralski method is 10 ℃ / cm, the growth rate of the single crystal silicon is 1.5 mm / min, the pulling rate is 1.3 mm / min, and the flow rate of argon is 80 L / min. Specifically, a doping gas mask technique is used, SbH3 is used as a dopant, the antimony doping concentrations of the edge region and the center region are controlled respectively, and the resistivity is monitored. The method for monitoring the resistivity comprises: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%. + He + is implanted into the single crystal silicon rod by low-temperature ion implantation during the preparation of the single crystal silicon to form a nano-cavity layer, wherein the dose of He 14 is 1.01×10 2 ions / cm 2 , and the energy is 50 keV.

[0137] (2) After the single crystal silicon rod is cut into a wafer by a resin binder diamond wire with a wire diameter of 50 μm, surface treatment is performed to obtain a silicon wafer. The cutting speed is 1.3 m / s. The cooling liquid used for cutting comprises polyethylene glycol, and further comprises nano-SiO2 particles, and the median particle size of the nano-SiO2 particles is 100 nm. The surface treatment method comprises: polishing, chemical thinning and texturing in sequence. The polishing method comprises: double-sided chemical mechanical polishing to a surface roughness Ra<0.5 nm. The chemical thinning method comprises: isotropic etching of both sides by using a mixed acid solution of HF and HNO3 (the molar ratio of HF to HNO3 is 1:3) to remove the cutting damage layer. The texturing method comprises: forming a reverse pyramid texturing structure on the front surface by laser etching, wherein the height of the reverse pyramid texturing structure is 24 μm.

[0138] (3) A front passivation layer and a back passivation layer are formed on the front surface and the back surface of the silicon wafer respectively. The front passivation layer is an Al2O3 / SiN x stack, and the back passivation layer is a SiO2 / polysilicon / SiN x stack.

[0139] (4) The back passivation layer is selectively doped by laser, specifically, a local back passivation layer is selectively ablated by a pulsed laser, and phosphorus is doped to form an N + local heavily doped region to obtain a selective emitter. The wavelength of the pulsed laser is 540 nm, the energy density of the pulsed laser is 2.8 J / cm 2 , and the scanning speed of the pulsed laser is 6 m / s.

[0140] (5) The edges of the silicon wafer are rounded off by laser, and then SiN is deposited on the edges by plasma-enhanced chemical vapor deposition. x Layer. During plasma-enhanced chemical vapor deposition, the partition pressure is controlled at 0.1 bar.

[0141] (6) Preparation of staggered point contact back electrode: Several staggered grooves are opened on the back of the silicon wafer using an ultraviolet laser. The wavelength of the ultraviolet laser is 350 nm, the pulse width is 8 ps, and the energy is 1 μJ. The width of each groove is 20 μm, the length-to-width ratio of each groove is 2:1, and the distance between two adjacent grooves is 1.4 mm. Then, copper electroplating and silver coating are performed sequentially to form a copper-plated silver electrode material. The electroplating solution used for copper electroplating is a mixture of CuSO4, H2SO4, and additives. The concentration of CuSO4 in the mixture is 150 g / L, and the concentration of H2SO4 is 100 g / L. The additives include PEG and a chlorine source. The chlorine source includes NaCl. The concentration of PEG in the mixture is 0.1 g / L, and the concentration of NaCl is 0.1 g / L. - The concentration was 0.03 g / L. The current density for copper electroplating was 1.9 A / dm³. 2 The copper electroplating time was 15.5 minutes. The silver coating method included: immersion plating, in which the silicon wafer was immersed in a mixed solution of AgNO3 and a complexing agent to undergo a displacement reaction; the complexing agent included ammonia water, and the concentration of AgNO3 in the mixed solution was 0.3 mol / L. The NH3 and Ag... + The molar ratio is 3:1.

[0142] The large-size N-type silicon wafer fabricated in this embodiment has dimensions of 230mm × 230mm and a thickness of 90μm. The edges of the large-size N-type silicon wafer are rounded with a radius of 0.3mm, and the edges of the large-size N-type silicon wafer are coated with SiN. x Layer, SiN x The layer thickness is 80 nm. The large-size N-type silicon wafer includes a central region and an edge region surrounding the central region. The edge region is 2 mm wide and has a resistivity of 15 Ω·cm, while the central region has a resistivity of 0.5 Ω·cm. The antimony dopant content in the edge region is 5 × 10⁻⁶. 14 atoms / cm 3 The antimony content in the central region is 1×10⁻⁶. 16 atoms / cm 3 The radial resistivity fluctuation of this large-size N-type silicon wafer is <5%. The front side of this large-size N-type silicon wafer has a front passivation layer, which is Al2O3 / SiN. xstack, the thickness of the Al2O3 layer in the stack is 9 nm, the thickness of the SiN layer is 70 nm, and the thickness of the SiO2 layer is 1.9 nm x stack, the thickness of the Al2O3 layer in the stack is 9 nm, the thickness of the SiN layer is 70 nm, and the thickness of the SiO2 layer is 1.9 nm x nm. The back surface of the large-size N-type silicon wafer has a back surface passivation layer, and the back surface passivation layer comprises SiO2 / polysilicon / SiN x stack, the thickness of the Al2O3 layer in the stack is 9 nm, the thickness of the SiN layer is 70 nm, and the thickness of the SiO2 layer is 1.9 nm x stack, the thickness of the Al2O3 layer in the stack is 9 nm, the thickness of the SiN layer is 70 nm, and the thickness of the SiO2 layer is 1.9 nm x nm; and the back surface passivation layer further has a selective emitter, and the concentration of phosphorus in the selective emitter is 3×10 20 atoms / cm 3 ; the back surface passivation layer further has an interlaced point contact back electrode, and the material of the interlaced point contact back electrode is copper-plated silver, the copper-plated silver comprises a copper layer and a silver layer covering the copper layer, the thickness of the copper layer is 21 μm, and the thickness of the silver layer is 0.9 μm; and the total area of the copper-plated silver accounts for 4% of the area of the back surface passivation layer.

[0143] Embodiment 3

[0144] The preparation method of the large-size N-type silicon wafer for a BC battery provided in this embodiment comprises the following steps:

[0145] (1) a single crystal silicon is prepared by a magnetic field assisted Czochralski method, wherein the doping element comprises antimony, and a single crystal silicon rod is obtained, wherein the axial temperature gradient of the magnetic field assisted Czochralski method is 15 ℃ / cm, the growth rate of the single crystal silicon is 1.2 mm / min, the pulling speed is 1.8 mm / min, and the flow rate of argon is 100 L / min. Specifically, a doping gas mask technology is used, SbH3 is used as a dopant, the antimony doping concentrations of the edge region and the center region are controlled respectively, and the gas flow rate of SbH3 is adjusted through photoluminescence detection; wherein the photoluminescence detection method comprises: on-line PL imaging identifies low lifetime regions caused by antimony aggregation, and the threshold value is controlled to be <500 μs. In addition, in the process of preparing the single crystal silicon, He + is implanted at a low temperature to form a nanocavity layer, wherein the dose of He + is 1×10 14 ions / cm 2 , and the energy is 60 keV.

[0146] (2) The monocrystalline silicon rod is cut into a wafer by using a resin-bonded diamond wire with a wire diameter of 80 μm, and the wafer is subjected to surface treatment. The cutting speed is 1.5 m / s. The cooling liquid used in the cutting includes polyethylene glycol, and further includes silicon carbide abrasive and nano-SiO2 particles at a mass ratio of 1:1. The median particle size of the silicon carbide abrasive is 3 μm, and the median particle size of the nano-SiO2 particles is 80 nm. The surface treatment method includes polishing, chemical thinning and texturing in sequence. The polishing method includes double-sided chemical mechanical polishing to a surface roughness Ra<0.5 nm. The chemical thinning method includes isotropic etching of both sides by using a mixed acid solution of HF and HNO3 (the molar ratio of HF to HNO3 is 1:3) to remove the cutting damage layer. The texturing method includes forming a reverse pyramid texturing structure on the front side by laser etching, wherein the height of the reverse pyramid texturing structure is 25 μm.

[0147] (3) A front passivation layer and a back passivation layer are formed on the front side and the back side of the wafer, respectively. The front passivation layer is an Al2O3 / SiN x stack, and the back passivation layer is a SiO2 / polysilicon / SiN x stack.

[0148] (4) The back passivation layer is selectively doped by laser. Specifically, the local back passivation layer is selectively ablated by a pulsed laser, and doped with phosphorus to form an N + local heavily doped region, thereby obtaining a selective emitter. The wavelength of the pulsed laser is 530 nm, the energy density of the pulsed laser is 2.9 J / cm 2 , and the scanning speed of the pulsed laser is 5.5 m / s.

[0149] (5) The edge of the wafer is formed into a circular arc chamfer by laser, and then a SiN x layer is wrapped around the edge by plasma enhanced chemical vapor deposition. During the plasma enhanced chemical vapor deposition, the partition pressure is controlled to be 0.3 bar.

[0150] (6) Preparation of staggered point contact back electrode: Several staggered grooves are opened on the back of the silicon wafer using an ultraviolet laser. The wavelength of the ultraviolet laser is 360 nm, the pulse width is 9 ps, and the energy is 0.9 μJ. The width of each groove is 32 μm, the length-to-width ratio of each groove is 2:1, and the distance between two adjacent grooves is 1.6 mm. Then, copper electroplating and silver coating are performed sequentially to form a copper-plated silver electrode material. The electroplating solution used for copper electroplating is a mixture of CuSO4, H2SO4, and additives. The concentration of CuSO4 in the mixture is 230 g / L, and the concentration of H2SO4 is 80 g / L. The additives include PEG and a chlorine source. The chlorine source includes NaCl. The concentration of PEG in the mixture is 0.5 g / L, and the concentration of NaCl is 0.5 g / L. - The concentration was 0.1 g / L. The current density for copper electroplating was 2.1 A / dm³. 2 The copper electroplating time is 15 minutes. The silver coating method includes: immersion plating, in which the silicon wafer is immersed in a mixed solution of AgNO3 and a complexing agent to carry out a displacement reaction; the complexing agent includes ammonia water, and the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.35 mol / L. The NH3 and Ag... + The molar ratio is 4:1.

[0151] The large-size N-type silicon wafer fabricated in this embodiment has dimensions of 230mm × 230mm and a thickness of 130μm. The edges of the large-size N-type silicon wafer are rounded with a radius of 1.5mm, and the edges of the large-size N-type silicon wafer are wrapped with SiN. x Layer, SiN x The layer thickness is 200 nm. The large-size N-type silicon wafer includes a central region and an edge region surrounding the central region. The edge region is 4 mm wide and has a resistivity of 13 Ω·cm, while the central region has a resistivity of 3 Ω·cm. The antimony dopant content in the edge region is 5 × 10⁻⁶. 14 atoms / cm 3 The antimony content in the central region is 5 × 10⁻⁶. 16 atoms / cm 3 The radial resistivity fluctuation of this large-size N-type silicon wafer is <5%. The front side of this large-size N-type silicon wafer has a front passivation layer, which is Al2O3 / SiN. x Stacked Al2O3 / SiN x The thickness of the Al2O3 layer in the stack is 8 nm, and the SiN layer is... x The layer thickness is 60 nm. This large-size N-type silicon wafer has a back passivation layer on its back side, which comprises SiO2 / polysilicon / SiN. x The stacked structure of SiO2 / polysilicon / SiN xThe thickness of the SiO2 layer in the stack is 2.1 nm, the thickness of the polysilicon layer is 151 nm, the thickness of the SiN x layer is 101 nm; the back passivation layer further has a selective emitter, the concentration of phosphorus in the selective emitter is 3×10 20 atoms / cm 3 ; the back passivation layer further has an interlaced point contact back electrode, the material of the interlaced point contact back electrode is copper plated with silver, the copper plated with silver includes a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 19 μm, and the thickness of the silver layer is 0.8 μm; the total area of the copper plated with silver accounts for 2% of the area of the back passivation layer.

[0152] Comparative Example 1

[0153] The existing N-type silicon wafer G1 (158.75 mm×158.75 mm).

[0154] Comparative Example 2

[0155] The large-size N-type silicon wafer for BC battery and the preparation method thereof provided in the embodiment are basically the same as those in Embodiment 1, except that the edge of the silicon wafer is not formed with a circular arc chamfer, and the edge is not wrapped with a SiN x layer, in addition, the content of the doping element antimony in the edge region is equal to the content of the doping element antimony in the center region, and both are 1×10 15 atoms / cm 3 .

[0156] Comparative Example 3

[0157] The large-size N-type silicon wafer for BC battery and the preparation method thereof provided in the embodiment are basically the same as those in Embodiment 1, except that the front surface of the large-size N-type silicon wafer does not have a front passivation layer, and the back surface of the large-size N-type silicon wafer does not have a back passivation layer.

[0158] Comparative Example 4

[0159] The large-size N-type silicon wafer for BC battery and the preparation method thereof provided in the embodiment are basically the same as those in Embodiment 1, except that in step (1), the axial temperature gradient of the magnetic field assisted Czochralski method is 5 ℃ / cm, the growth rate of the single crystal silicon is 0.5 mm / min, the pulling rate is 2.5 mm / min, and the flow rate of argon is 50 L / min.

[0160] Comparative Example 5

[0161] The large-size N-type silicon wafer for BC battery and the preparation method thereof provided in the embodiment are basically the same as those in Embodiment 1, except that in step (2), the cooling liquid does not contain silicon carbide abrasive, no surface treatment is performed, and the diameter of the diamond wire is 100 μm, and the cutting speed is 0.5 m / s.

[0162] Experimental Example

[0163] The performance of the large-size N-type silicon wafer prepared in each example and each comparative example was tested, and the results are shown in Table 1.

[0164] Table 1 Performance test results of each N-type silicon wafer

[0165]

[0166] As can be seen from Table 1, the large-size N-type silicon wafer prepared in each example has the advantages of high mechanical strength, low fragment rate, high battery efficiency, low light absorption loss, high open-circuit voltage (Voc), and high fill factor (FF).

[0167] Specifically, in Example 1-Example 3: the circular arc chamfer (0.3-1.5 mm) + SiN x edge wrapping was used, which significantly improved the mechanical strength (>550 MPa) and the fragment rate was <1.5%. In Comparative Example 2 (no chamfer / no SiN x edge stress concentration, resulting in a fragment rate of up to 4.5%. In Comparative Example 5 (rough cutting / no surface treatment), cutting damage resulted in the lowest mechanical strength (400 MPa) and a fragment rate of up to 12%.

[0168] At the same time, in Example 1-Example 3: a combined passivation layer (front passivation layer Al2O3 / SiN x laminated + back passivation layer SiO2 / polysilicon / SiN x laminated) + selective emitter (phosphorus element concentration ≥1×10 20 atoms / cm 3 ) was used, and the battery efficiency reached 26.3%-26.7%. In Comparative Example 3 (no passivation layer), the recombination loss increased dramatically, and the battery efficiency was only 22.5%. In Comparative Example 1 (G1 size), the small size limited the optical design, and the battery efficiency was only 24.0%.

[0169] In addition, in Example 1-Example 3: inverted pyramid texturing (height 23-25 μm) + optimization of SiN x thickness (60-80 nm) in the Al2O3 / SiN x laminated layer was used to control the light absorption loss to be less than 3%. In Comparative Example 5 (not textured), the surface reflection loss reached 9%.

[0170] Furthermore, in Example 1-Example 3: high resistance edges (resistivity of edge region ≥10 Ω·cm) + SiN xEncapsulation, PID (high voltage difference between battery piece and frame / ground, leading to ion migration (such as Na+) to destroy the passivation layer, resulting in power degradation) attenuation <2%, high reliability. And the comparative example 3 (no passivation layer), metal diffusion, leading to PID failure (>10%).

[0171] As can be seen, the embodiments have the following advantages: (1) circular arc chamfer + SiN x Edge wrapping: reduce the fragment rate to <1.5%, adapt to thinning (90~130μm). (2) Combined passivation layer + selective emitter: efficiency breakthrough 26.5%, Voc>730mV. (3) Copper silver plated electrode (20μm Cu+1μm Ag): balance cost and performance, FF>83%. And the traditional G1 silicon wafer (comparative example 1) is low in efficiency due to size limitation; Comparative Example 4 and Comparative Example 5 are not suitable for the parameters of preparing single crystal silicon and the parameters of cutting, resulting in comprehensive deterioration of mechanical, optical and electrical properties. Therefore, the technical route of each embodiment provides a high reliability and high efficiency solution for mass production of large-size N-type BC battery.

[0172] In summary, the present application sets the edge circular arc chamfer and wraps SiN x layer, edge low-doped, which can reduce edge carrier recombination, improve open circuit voltage and improve battery power output while ensuring mechanical strength and reducing fragment rate. Moreover, by optimizing the structure of large-size N-type silicon wafer and its preparation method, the comprehensive performance of large-size N-type silicon wafer and the BC battery prepared therefrom can be further improved.

[0173] Although the present application has been illustrated and described with specific embodiments, it should be understood that the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit it; those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced equivalently without departing from the spirit and scope of the present application; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application; therefore, this means that all these replacements and modifications within the scope of the present application are included in the appended claims.

Claims

1. A large size N-type silicon wafer for BC battery characterized in that, The size of the large-size N-type silicon wafer is greater than or equal to 230 mm*230 mm, the thickness of the large-size N-type silicon wafer is 90-130 μm, the edge of the large-size N-type silicon wafer is a circular arc chamfer, and the edge of the large-size N-type silicon wafer is wrapped with a SiNx layer; The large-size N-type silicon wafer includes a center region and an edge region surrounding the center region, a content of a doping element antimony in the edge region is ≤1×10 15 atoms / cm 3 ; a content of the doping element antimony in the center region is 1×10 16 ~5×10 16 atoms / cm 3 .

2. The large size N-type silicon wafer for BC battery of claim 1, wherein, At least one of the following conditions is met: (1) the radius of the circular arc chamfer is 0.3-1.5 mm; (2) the width of the edge region is 2-4 mm; (3) the SiN x layer has a thickness of 80-200 nm.

3. The large size N-type silicon wafer for BC battery of claim 1, wherein, At least one of the following conditions is met: (1) the resistivity of the edge region is greater than or equal to 10 Ω*cm, and the resistivity of the center region is 0.5-3 Ω*cm; (2) the radial resistivity fluctuation of the large-size N-type silicon wafer is less than 5%.

4. The large size N-type silicon wafer for BC battery of claim 1, wherein, At least one of the following conditions is met: (1) the front surface of the large-size N-type silicon wafer has a front surface passivation layer, the front surface passivation layer comprises Al2O3 / SiN x stack; the thickness of the Al2O3 layer in the Al2O3 / SiN x stack is 8-10 nm, the thickness of the SiN x layer in the Al2O3 / SiN x stack is 60-80 nm; (2) The back surface of the large-size N-type silicon wafer has a back surface passivation layer, the back surface passivation layer comprises SiO2 / polysilicon / SiN x , the thickness of the SiO2 layer in the SiO2 / polysilicon / SiN x stack is 1.9-2.1 nm, the thickness of the polysilicon layer in the SiO2 / polysilicon / SiN x stack is 149-151 nm, and the thickness of the SiN x layer in the SiO2 / polysilicon / SiN x stack is 99-101 nm; the back surface passivation layer further has a selective emitter, the concentration of phosphorus in the selective emitter is ≥1×10 20 atoms / cm 3 ; the back surface passivation layer further has an interleaved point-contact back electrode, the material of the interleaved point-contact back electrode is copper-plated silver, the copper-plated silver comprises a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 19-21 μm, the thickness of the silver layer is 0.8-1 μm, and the total area of the copper-plated silver accounts for ≤5% of the area of the back surface passivation layer.

5. The method of producing large size N-type silicon wafers for BC batteries according to any one of claims 1 to 4, wherein The method comprises the following steps: (a) preparing a single crystal silicon rod by a Czochralski method, wherein the doping element comprises antimony, to obtain a single crystal silicon rod; (b) after the single crystal silicon rod is cut into a wafer, surface treatment is performed to obtain a silicon wafer; (c) forming a front passivation layer and a back passivation layer on the front side and the back side of the silicon wafer, respectively; (d) performing selective laser doping on the back passivation layer to form a selective emitter; (e) forming a rounded chamfer on the edge of the silicon wafer by laser and then wrapping SiN by plasma enhanced chemical vapor deposition at the edge x layer.

6. The method of claim 5, wherein the large size N-type silicon wafer for BC battery is prepared by the steps of: At least one of the following conditions is met: ​ (1) in step (a), the Czochralski method comprises a magnetic field assisted Czochralski method, and the axial temperature gradient of the magnetic field assisted Czochralski method is 10-15 ℃ / cm; (2) in step (a), during the preparation of the single crystal silicon by the Czochralski method, the growth rate of the single crystal silicon is 1.2-1.5 mm / min; (3) in step (a), during the preparation of the single crystal silicon by the Czochralski method, the crystal pulling speed is 1.3-1.8 mm / min; (4) in step (a), during the preparation of the single crystal silicon by the Czochralski method, the flow rate of argon is 80-100 L / min; (5) in step (a), during the preparation of the single crystal silicon by the Czochralski method, a doping gas mask technology is used, SbH3 is used as a dopant, the antimony doping concentration of the edge region and the center region is controlled, respectively, and the gas flow rate of the SbH3 is adjusted through resistivity monitoring and / or photoluminescence detection; wherein the method of resistivity monitoring comprises: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%; the method of photoluminescence detection comprises: online PL imaging identifies the low lifetime area caused by antimony aggregation, and the threshold value is controlled to be less than 500 μs; (6) In step (a), the process of preparing single crystal silicon by the Czochralski method further comprises low-temperature ion implantation of He + to form a nanocavity layer; wherein the dosage of He + is 1×10 14 ~1.01×10 14 ions / cm 2 , and the energy is 50~60keV.

7. The method of claim 5, wherein the large size N-type silicon wafer for BC battery is prepared by the steps of: At least one of the following conditions is met: ​ (1) in step (b), the diamond wire used for cutting comprises a resin binder diamond wire, and the wire diameter of the diamond wire is 50-80 μm; (2) in step (b), the cutting speed is 1.2-1.5 m / s; (3) in step (b), the cooling liquid used for cutting comprises polyethylene glycol, and the cooling liquid further contains silicon carbide abrasive and / or nano SiO2 particles, wherein the median particle size of the silicon carbide abrasive is 3-5 μm, and the median particle size of the nano SiO2 particles is 80-100 nm; In step (b), the surface treatment method comprises: polishing, chemical thinning and texturing in sequence; wherein the polishing method comprises: double-sided chemical mechanical polishing, and the polishing is to a surface roughness Ra<0.5nm; the chemical thinning method comprises: using a mixed acid solution of HF and HNO3 to perform isotropic etching on both sides respectively to remove a cutting damage layer; and the texturing method comprises: using laser etching to form an inverted pyramid texturing structure on the front side, wherein the height of the inverted pyramid texturing structure is 23-25μm.

8. The method for preparing large size N-type silicon wafer for BC battery as claimed in claim 5 wherein, At least one of the following conditions is met: (1) In step (c), the front passivation layer comprises Al2O3 / SiN x stack, the back passivation layer comprises SiO2 / polysilicon / SiN x stack; (2) In step (d), the method of selective laser doping comprises: selectively ablating and doping phosphorus locally on the back passivation layer by a pulsed laser to form an N + doped region 2 ; wherein the wavelength of the pulsed laser is 530-540 nm, the energy density of the pulsed laser is 2.8-3 J / cm 2 , and the scanning speed of the pulsed laser is 5-6 m / s. (3) In step (e), during the plasma enhanced chemical vapor deposition process, the partition pressure is controlled to be 0.1-0.3bar.

9. The method of claim 5, wherein the large size N-type silicon wafer for BC battery is prepared by the steps of: After step (e), a step (f) of preparing an interlaced point contact back electrode is further included: using ultraviolet laser to open a plurality of interlaced grooves on the back surface of the silicon wafer, and then performing copper electroplating and silver covering in sequence to form a copper-plated silver electrode material; ​ wherein the wavelength of the ultraviolet laser is 350-360nm, the pulse width is 8-10ps, and the energy is 0.8-1μJ; the width of each groove is 20-32μm, the length-width ratio of each groove is 2:1, and the distance between adjacent two grooves is 1.4-1.6mm; The plating solution used for the copper electroplating is a mixture of CuSO4, H2SO4 and an additive; the concentration of CuSO4 in the mixture of CuSO4, H2SO4 and the additive is 150-250 g / L, the concentration of H2SO4 in the mixture of CuSO4, H2SO4 and the additive is 50-100 g / L; the additive comprises PEG and a chlorine source, the chlorine source comprises HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and the additive is 0.05-0.5 g / L, and the concentration of Cl in the mixture of CuSO4, H2SO4 and the additive is 0.03-0.1 g / L. - The plating solution used for the copper electroplating is a mixture of CuSO4, H2SO4 and an additive; the concentration of CuSO4 in the mixture of CuSO4, H2SO4 and the additive is 150-250 g / L, the concentration of H2SO4 in the mixture of CuSO4, H2SO4 and the additive is 50-100 g / L; the additive comprises PEG and a chlorine source, the chlorine source comprises HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and the additive is 0.05-0.5 g / L, and the concentration of Cl in the mixture of CuSO4, H2SO4 and the additive is 0.03-0.1 g / L. - The plating solution used for the copper electroplating is a mixture of CuSO4, H2SO4 and an additive; the The current density of the copper electroplating is 1.9-2.1 A / dm 2 The time of the copper electroplating is 15-15.5 min. The method for covering silver includes: using a dipping method, immersing the silicon wafer into a mixed solution of AgNO3 and a complexing agent to perform a displacement reaction; the complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3-0.35 mol / L, and the molar ratio of NH3 to Ag + in the mixed solution of AgNO3 and the complexing agent is ≥2:

1.

10. A BC battery characterized by, a large-size N-type silicon wafer for BC battery as claimed in any one of claims 1-4.

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