Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell comprises a cell body which comprises a first surface and a second surface which are oppositely arranged; the conductive barrier layer is at least arranged on the first surface; the plurality of first grid lines are arranged on the conductive barrier layer, extend along the first direction and are arranged along the second direction; the first grid lines are formed by non-burn-through slurry, the resistivity of the first grid lines is 6-60 mu omega.cm, and the area of the cross section of each first grid line is larger than or equal to 250 mu m < 2 >; the height of the first grid line is h along the thickness direction of the battery body; the width of the first grid line is w, h / w is 0.1-0.5, and w is greater than or equal to 30 microns; the distance between every two adjacent first grid lines ranges from 0.6 mm to 1.3 mm. The manufacturing cost of the solar cell is reduced while the power generation performance of the solar cell is ensured, and conductive metal with relatively low price, such as copper paste, can be added into the non-burn-through paste so as to reduce the manufacturing cost of the grid line.

Description

[0001] This application claims priority of the Chinese patent application number 202510214993.0 filed with the State Intellectual Property Office of China on February 25, 2025, entitled “A Solar Cell and Photovoltaic Module”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0003] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells are devices that convert sunlight into electricity. Specifically, they use the principle of photovoltaics to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0004] As the photovoltaic industry's market and production capacity continue to expand, the industry's demand for silver paste has also surged. The price of silver paste has risen accordingly, costs have continued to rise, and profit margins have been increasingly squeezed. Summary of the Invention

[0005] The purpose of this application is to provide a solar cell and a photovoltaic module to ensure the power generation performance of the solar cell while reducing the manufacturing cost of the solar cell.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] A solar cell comprising:

[0008] The battery body comprises a first surface and a second surface arranged opposite to each other;

[0009] a conductive barrier layer, disposed at least on the first surface;

[0010] A plurality of first grid lines are provided on the conductive barrier layer, extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect; the first grid lines are formed of a non-burn-through paste, the resistivity of the first grid lines is 6 μΩ·cm to 60 μΩ·cm, and the cross-sectional area of ​​the first grid lines along a plane perpendicular to the first direction is greater than or equal to 250 μm 2 ;

[0011] Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1 to 0.5, and w ≥ 30 μm;

[0012] The distance between two adjacent first grid lines is 0.6 mm to 1.3 mm.

[0013] The present application adopts a non-burn-through type slurry, and a relatively cheap conductive metal such as copper slurry can be added to the non-burn-through type slurry to reduce the manufacturing cost of the gate line. In addition, in order to address technical problems such as low collection efficiency of the gate line current and large contact resistance, the present application comprehensively considers various parameters such as the resistivity of the first gate line, the cross-sectional area of ​​the first gate line, the aspect ratio h / w of the first gate line, the width w of the first gate line, and the spacing between two adjacent first gate lines, so that the resistivity of the first gate line, the cross-sectional area of ​​the first gate line, the aspect ratio h / w of the first gate line, the width w of the first gate line, and the spacing between two adjacent first gate lines are respectively within the above-mentioned reasonable range and match each other, thereby ensuring that the collection efficiency of the first gate line is low and the contact resistance of the first gate line is reduced. At the same time, in order to prevent the non-burn-through type slurry from damaging the passivation effect of the doped semiconductor layer, a conductive barrier layer is also provided in the present application. The conductive barrier layer can separate the first gate line and the first doped semiconductor layer, ensuring the passivation effect of the doped semiconductor layer while also ensuring the conductive performance between the first gate line and the first doped semiconductor layer.

[0014] A photovoltaic assembly comprises the solar cell as described in any one of the above and a first conductive member, wherein the first conductive member extends along the second direction and is electrically connected to the first grid line.

[0015] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A top view of a solar cell provided in an embodiment of the present application;

[0018] Figure 2 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0019] Figure 3 A top-down SEM image of the first gate line provided in an embodiment of the present application;

[0020] Figure 4 A top view of a solar cell provided in another embodiment of the present application;

[0021] Figure 5 for Figure 4 A partial cross-sectional view along the middle line A1-A2;

[0022] Figure 6 A top view of a solar cell provided in another embodiment of the present application;

[0023] Figure 7 SEM image of the conductive barrier layer provided in the embodiment of the present application;

[0024] Figure 8 An SEM image of the first gate line provided in an embodiment of the present application;

[0025] Figure 9 This is an SEM image of a modified layer provided in another embodiment of the present application;

[0026] Figure 10 for Figure 9 A partial cross-sectional view of

[0027] Figure 11 for Figure 9 A partial enlarged view of

[0028] Figure 12 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0029] Figure 13 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0030] Figure 14 A cross-sectional SEM image of a conductive barrier layer and a first gate line provided in another embodiment of the present application;

[0031] Figure 15 A top view of a solar cell provided in an embodiment of the present application;

[0032] Figure 16 for Figure 15 sectional view of

[0033] Figure 17 is a schematic diagram of the connection between the first grid line and the main grid;

[0034] Figure 18 A top view of a solar cell provided in another embodiment of the present application;

[0035] Figure 19 for Figure 18 sectional view of

[0036] Figure 20 Schematic diagram of the connection between the first gate line and the welding ribbon.

[0037] Reference numerals:

[0038] 1-first gate line, 1a-linear particles, 1b-spherical particles, 1c-flaky particles, 1d-V-shaped particles, 1e-thickened section, 101-main body, 102-spreading part, 2-passivation layer, 2a-opening, 2b-heat-affected zone, 3-first doped semiconductor layer, 3a-modified layer, 3a1-pit, 3b-metal crystal layer, 4-semiconductor substrate, 5-conductive barrier layer, 5a-conductive material, 5b-conductive channel, 5c-pore, 6-insulating block, 7-first conductive part, 7a-side protrusion, 8-second gate line, 9-first interface layer, 10-second doped semiconductor layer, 11-second interface layer, 12-bonding layer. DETAILED DESCRIPTION

[0039] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0042] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0043] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0044] In the solar cell manufacturing process, grid lines have always relied heavily on silver. Currently, screen-printing silver paste is the primary method for forming silver grid lines to form electrode patterns. Silver grid lines are a major constraint on reducing the cost of solar cells or photovoltaic modules. Copper, a relatively inexpensive metal with reasonable electrical conductivity, is highly valued. However, grid lines formed using copper paste currently suffer from low current collection efficiency and high contact resistance, hindering mass production of copper paste.

[0045] In view of the above, please refer to Figure 1-2 The solar cell provided in the embodiment of the present application includes a cell body, a conductive barrier layer 5, and a plurality of first grid lines 1. The cell body includes a first surface and a second surface opposite to each other, that is, the two surfaces opposite to each other along the thickness direction of the cell body are the first surface and the second surface respectively. The first surface can correspond to the backlight side of the solar cell, and the second surface can correspond to the light-facing side of the solar cell; or the first surface can correspond to the light-facing side of the solar cell, and the second surface can correspond to the backlight side of the solar cell.

[0046] The battery body may include a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10, and a passivation layer 2. The conductive barrier layer 5 is provided at least on the first surface, that is, the conductive barrier layer 5 is provided on the first surface; or the conductive barrier layer 5 is provided on both the first surface and the second surface. Specifically, the conductive barrier layer 5 can be partially provided on the first surface. A plurality of first gate lines 1 are provided on the conductive barrier layer 5, that is, the conductive barrier layer 5 is located between the battery body and the first gate lines 1. The function of the conductive barrier layer 5 is to separate the first gate lines 1 from the first doped semiconductor layer 3, while ensuring the electrical conductivity between the first gate lines 1 and the first doped semiconductor layer 3.

[0047] like Figure 1As shown, a plurality of first grid lines 1 extend along the first direction and are arranged along the second direction, that is, the length of the first grid lines 1 is set along the first direction. The first direction and the second direction intersect, that is, the first direction is different from the second direction, and the angle between the first direction and the second direction can be an acute angle or a right angle. The first direction can be the length direction of the battery body or the width direction of the battery body. When the first direction is the length direction of the battery body, the second direction is the width direction of the battery body; when the first direction is the width direction of the battery body, the second direction is the length direction of the battery body.

[0048] The first gate line 1 is formed from a non-burn-through paste, which may include one or more of a low-temperature silver paste, a copper paste, and an aluminum paste. The first gate line 1 can be formed in the area corresponding to the opening 2a using processes such as screen printing, electroplating, sputtering, or evaporation. The non-burn-through paste is a paste that cannot directly penetrate the passivation layer 2 through sintering to achieve contact with the first doped semiconductor layer 3. Generally speaking, the first gate line 1 formed by the non-burn-through paste ultimately retains an adhesive material, such as an organic component.

[0049] The first gate line 1 formed from a non-burn-through paste generally has a higher resistivity because it contains an organic material that cannot be sintered and volatilized. This organic material can increase adhesion, but the resistivity of the first gate line 1 needs to be kept within a reduced range, for example, it can be less than 80μΩ·cm. In some embodiments, the resistivity of the first gate line 1 is between 6μΩ·cm and 60μΩ·cm. This allows the cross-sectional area of ​​the first gate line 1 to be maintained within a reasonable range, preventing the resistivity of the first gate line 1 from being too high, resulting in a large cross-sectional area of ​​the first gate line 1, wasting raw materials and causing severe light blocking. At the same time, it also avoids the resistivity of the first gate line 1 being too low, which would require higher raw materials for the first gate line 1 and increase the raw material cost of the first gate line 1.

[0050] In some embodiments, if the cross-sectional area of ​​the first gate line 1 is too small, the line resistance of the first gate line 1 will be too large, affecting the current transmission. Therefore, in this application, the cross-sectional area of ​​the first gate line 1 along the plane perpendicular to the first direction is greater than or equal to 250 μm. 2 . In cross-sectional area greater than or equal to 250μm 2 When the resistivity of the first gate line 1 is matched to 6 μΩ·cm to 60 μΩ·cm, a higher efficiency current collection of the gate line can be achieved and a lower transmission resistance can be ensured.

[0051] In addition, along the thickness direction of the battery body, the height of the first gate line 1 is h; the width of the first gate line 1 is w, and h / w ​​is 0.1 to 0.5. When the aspect ratio of the first gate line 1 is less than 0.1, the width of the first gate line 1 needs to be wider, which will lead to an increase in the shading area of ​​the first gate line 1, reducing the light absorption utilization rate, and at the same time, the area of ​​the opening 2a of the passivation layer 2 needs to be increased accordingly, and the damage to the first doped semiconductor layer 3 caused during the opening 2a will also increase. When the aspect ratio of the first gate line 1 is greater than 0.5, the height of the first gate line 1 needs to be higher, and the gate is easy to break during printing. Therefore, in order to balance the above two aspects, h / w in this application is 0.1 to 0.5 to reduce the shading area and light loss, improve the light absorption utilization rate, reduce the damage to the first doped semiconductor layer 3, and reduce the risk of gate breakage during printing.

[0052] To ensure that the cross-sectional area is greater than or equal to 250 μm 2 , and the height-width is between 0.1-0.5, the width w of the first gate line 1 needs to be greater than or equal to 30 μm to ensure the transmission efficiency of the first gate line 1 and reduce the contact resistance of the first gate line 1.

[0053] Furthermore, the spacing between two adjacent first gridlines 1 also affects the light-transmitting area. If the spacing between two adjacent first gridlines 1 is too small, the light-transmitting area between the two adjacent first gridlines 1 is small, affecting the light absorption and utilization efficiency. If the spacing between two adjacent first gridlines 1 is too large, the current collection efficiency will be reduced. Therefore, in this application, the spacing between two adjacent first gridlines 1 is 0.6mm to 1.3mm to ensure a reasonable light-transmitting area between the two adjacent first gridlines 1 and the current collection efficiency is guaranteed, while also improving the current collection efficiency on both sides of the first gridlines 1.

[0054] As can be seen from the above, the present application adopts a non-burn-through type slurry, and a relatively cheap conductive metal such as copper paste can be added to the non-burn-through type slurry to reduce the manufacturing cost of the grid line. In addition, in order to solve the technical problems such as low collection efficiency of the grid line current and large contact resistance, the present application comprehensively considers various parameters such as the resistivity of the first grid line 1, the cross-sectional area of ​​the first grid line 1, the aspect ratio h / w of the first grid line 1, the width w of the first grid line 1, and the spacing between two adjacent first grid lines 1, so that the resistivity of the first grid line 1, the cross-sectional area of ​​the first grid line 1, the aspect ratio h / w of the first grid line 1, the width w of the first grid line 1, and the spacing between two adjacent first grid lines 1 are respectively within the above-mentioned reasonable range and match each other, thereby ensuring that the collection efficiency of the first grid line 1 is low and reducing the contact resistance of the first grid line 1. At the same time, in order to prevent the non-burn-through slurry from damaging the passivation effect of the doped semiconductor layer, a conductive barrier layer 5 is also provided in the present application. The conductive barrier layer 5 can separate the first gate line 1 and the first doped semiconductor layer 3, thereby ensuring the passivation effect of the doped semiconductor layer while also ensuring the conductivity between the first gate line 1 and the first doped semiconductor layer 3.

[0055] Exemplarily, the resistivity of the first grid line 1 is 6 μΩ·cm, 8 μΩ·cm, 10 μΩ·cm, 12 μΩ·cm, 15 μΩ·cm, 18 μΩ·cm, 20 μΩ·cm, 22 μΩ·cm, 25 μΩ·c m, 28μΩ·cm, 30μΩ·cm, 32μΩ·cm, 35μΩ·cm, 38μΩ·cm, 40μΩ·cm, 45μΩ·cm, 50μΩ·cm, 55μΩ·cm or 60μΩ·cm, etc.

[0056] Along the plane perpendicular to the first direction, the cross-sectional area of ​​the first gate line 1 is 250 μm 2 , 260μm 2 , 270μm 2 , 280μm 2 , 290μm 2 , 300μm 2 , 320μm 2 , 350μm 2 , 380μm 2 , 400μm 2 , 420μm 2 , 450μm 2 , 480μm 2 or 500 μm 2 wait.

[0057] The aspect ratio h / w of the first gate line 1 is 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45 or 0.5, etc. Optionally, the aspect ratio h / w of the first gate line 1 is 0.1-0.25.

[0058] The width w of the first gate line 1 is 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm or 180 μm.

[0059] The distance between two adjacent first gate lines 1 may be 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, 1.2 mm or 1.3 mm, etc.

[0060] The applicant selected the above-mentioned printable slurry with the required resistivity to form the first grid lines 1. The first grid lines 1 are fine grids and the spacing between adjacent first grid lines 1 is 0.9 mm. The battery is tested using a 182mm*91mm half-cell. The test results are shown in the following table:

[0061]

[0062]

[0063] It can be seen from the above table that, when other parameters meet the requirements and the aspect ratio of the fine grid is between 0.1 and 0.5, the efficiency of the solar cell can be maintained above 26%.

[0064] Considering that if the first gate line 1 is too wide, it will increase the shading area and light loss, reducing the light absorption and utilization rate; if the first gate line 1 is too narrow, it will increase the contact resistance of the first gate line 1 and reduce the photoelectric conversion efficiency. In view of the above two situations, in this technical solution, the width w of the first gate line 1 is set within a reasonable range of 140μm ≥ w ≥ 30μm to reduce the shading area and light loss, improve the light absorption and utilization rate, reduce the contact resistance of the first gate line 1, and improve the current transmission efficiency.

[0065] In other embodiments, if the height of the first grid lines 1 is too high, the grid lines may break easily during the printing process, affecting the product yield; if the height of the first grid lines 1 is too small, the width of the first grid lines 1 will need to be wider, which will increase the light-shielding area of ​​the first grid lines 1 and reduce the light absorption efficiency. In view of the above two situations, in this technical solution, the height h of the first grid lines 1 is set within a reasonable range of 5μm ≥ h ≥ 25μm, reducing the light-shielding area and light loss while ensuring product yield.

[0066] For example, the height h of the first gate line 1 may be 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, or 25 μm.

[0067] In some embodiments, the first grid lines 1 are made of a copper paste material, and after curing, the first grid lines 1 include copper powder and an organic material. Copper has a reasonable electrical conductivity and is inexpensive. Therefore, the inclusion of copper powder in the first grid lines 1 in this technical solution reduces manufacturing costs compared to the prior art where the first grid lines 1 only include silver. In addition, the organic material has good viscosity, and the particles contained in the copper powder can adhere to each other through the organic material. The organic material can also improve the adhesion between the first grid lines 1 and the first surface, preventing the first grid lines 1 from detaching from the first surface.

[0068] like Figure 8 As shown, the copper powder includes at least flaky particles 1c and spherical particles 1b. Among them, the flaky particles 1c are flat as a whole, and the edges of the flaky particles 1c can be smooth edges, serrated edges or any irregular edges. The spherical particles 1b can be spherical, ellipsoidal, quasi-spherical or quasi-ellipsoidal, etc. The contact area between the flaky particles 1c and other conductive particles is large, which is conducive to reducing the contact resistance, while the contact area between the spherical particles 1b and the organic matter is large, which is conducive to the formation of the grid line. Based on this, in the present technical solution, the copper powder includes both flaky particles 1c and spherical particles 1b, which can not only make the first grid line 1 have a suitable resistivity, but also facilitate the printing and forming of the first grid line 1.

[0069] like Figure 8 As shown, the copper powder may further include one or more of linear particles 1a, V-shaped particles 1d, polygonal particles, and columnar particles. Specifically, the copper powder may include particles of any shape. Particles of these shapes have more contact points, which facilitates contact and conductivity between adjacent conductive particles, thereby ensuring that the first gate line 1 has a suitable resistivity.

[0070] In some embodiments, if the diameter of the flaky particles 1c is too large, it will result in the inability to pass through the printing mesh during the printing process; if the diameter of the flaky particles 1c is too small, it will result in a small content of organic matter in the gaps between the particles, which is not conducive to the formation of the first grid line 1. Based on this, in the present technical solution, the median diameter of the flaky particles 1c is 0.8μm to 5μm. Among them, the diameter of the flaky particles 1c can be an equivalent diameter, specifically, the equivalent diameter can be a screening equivalent diameter, a volume equivalent diameter or a surface area equivalent diameter. With this technical solution, the diameter of most flaky particles 1c is within a reasonable range, which can prevent the diameter of the flaky particles 1c from being too large to pass through the mesh, and can also ensure the content of organic matter in the gaps between the particles, thereby improving the adhesion of the first grid line 1.

[0071] Illustratively, the median diameter of the flaky particles 1c is 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 5.8 μm or 5 μm, etc.

[0072] Furthermore, the median thickness of the flaky particles 1c is between 100 nm and 500 nm, keeping the thickness of most flaky particles 1c within a reasonable range. This ensures low contact resistance between the flaky particles 1c and other conductive particles while preventing excessively high transmission resistance of the flaky particles 1c due to excessively thin flaky particles 1c. Consequently, the transmission resistance of the flaky particles 1c themselves is low. For example, the median thickness of the flaky particles 1c is 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0073] In some embodiments, if the distance between the spherical particles 1b is too large, the contact area between the spherical particles 1b and other conductive particles will be further reduced, which will increase the resistivity of the first grid line 1; if the distance between the spherical particles 1b is too small, it will lead to a smaller content of organic matter in the gaps between the particles, which is not conducive to the formation of the first grid line 1. Based on this, in the present technical solution, the median value of the particle size of the spherical particles 1b is 100nm to 500nm. Among them, the diameter of the spherical particles 1b can be an equivalent diameter, specifically, the equivalent diameter can be a screening equivalent diameter, a volume equivalent diameter or a surface area equivalent diameter. With this technical solution, the diameter of most spherical particles 1b is within a reasonable range, which can not only make the resistivity of the first grid line 1 within a reasonable range, but also ensure the content of organic matter in the gaps between the particles, thereby improving the adhesion of the first grid line 1.

[0074] For example, the median particle size of the spherical particles 1b is 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm.

[0075] In other embodiments, the mass percentage of the flaky particles 1c is 35% to 60%, that is, in the slurry forming the first gate lines 1, the mass percentage of the flaky particles 1c accounts for 35% to 60% of the total mass of the slurry. This ensures that the content of the flaky particles 1c in the slurry is within a reasonable range, and the contact area between the flaky particles 1c and other conductive particles is large, which helps to reduce the resistivity of the first gate lines 1 formed by the slurry. For example, the mass percentage of the flaky particles 1c is 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%, etc.

[0076] In other embodiments, the mass percentage of the spherical particles 1b is 35% to 60%, that is, in the slurry for forming the first grid lines 1, the mass of the spherical particles 1b accounts for 35% to 60% of the total mass of the slurry. This ensures that the content of the spherical particles 1b in the slurry is within a reasonable range, and the contact area between the spherical particles 1b and the organic matter is large, which facilitates the formation of the first grid lines 1. For example, the mass percentage of the spherical particles 1b is 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%.

[0077] In some embodiments, the tap density of the flaky particles 1c is 3 g / ml to 6 g / ml, which ensures the compactness of the flaky particles 1c and further ensures the current transmission efficiency of the flaky particles 1c. For example, the tap density of the flaky particles 1c is 3 g / ml, 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, 5.5 g / ml, or 6 g / ml.

[0078] In some embodiments, the tap density of the spherical particles 1b is 3.5 g / ml to 5.5 g / ml, thereby ensuring the compactness of the spherical particles 1b. For example, the tap density of the spherical particles 1b is 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, or 5.5 g / ml.

[0079] Tap density, or the bulk density of a powder after tapping, refers to the density of the powder after it is filled into a specific container and then vibrated, thereby destroying the voids within the powder and achieving a densely packed state. Measuring tap density can determine a powder's flowability and porosity. This can be calculated using a BT-301 tap density meter by vibrating the container 1,000 times and then measuring the volume.

[0080] In addition, the specific surface area of ​​the flaky particles 1c is 0.4 m 2 / g~0.7m 2 / g, so that the flaky particles 1c can have a reasonable contact area with other conductive particles, thereby reducing the resistivity of the first gate line 1. For example, the specific surface area of ​​the flaky particles 1c is 0.4m 2 / g, 0.45m 2 / g, 0.5m 2 / g, 0.55m 2 / g, 0.6m 2 / g, 0.65m 2 / g or 0.7m 2 / g, etc.

[0081] The specific surface area of ​​spherical particle 1b is 1.5m 2 / g~3.5m 2 / g, so that the contact area between the spherical particles 1b and the organic matter is larger, thereby improving the adhesion of the first grid line 1. For example, the specific surface area of ​​the spherical particles 1b is 1.5m 2 / g, 1.52m 2 / g, 1.55m 2 / g, 1.58m 2 / g, 2m 2 / g, 2.2m 2 / g, 2.5m 2 / g, 2.8m 2 / g、3m 2 / g, 3.2m 2 / g or 3.5m 2 / g, etc.

[0082] The specific surface area refers to the surface area per unit mass of a porous solid substance, and can be tested using conventional methods, such as the method for determining the specific surface area of ​​metal powders in GB / T 13390-2008.

[0083] In some embodiments, the organic material includes one or more of saturated / unsaturated fatty acids containing 8-18 carbon atoms, silane coupling agents, PVP, and thiols. These organic materials have high adhesion and are reasonably priced, and are suitable for forming the first gate lines 1 .

[0084] like Figure 2 and 3 As shown, the first gate line 1 includes a main portion 101 and a spreading portion 102 arranged along the second direction, and the main portion 101 and the spreading portion 102 extend along the first direction. That is, the spreading portion 102 is formed on both sides of the main portion 101. During the gate line manufacturing process, after slurry printing or laser transfer, and before the slurry solidifies, the slurry (such as one or more organic substances in the slurry) diffuses toward the cell surfaces on both sides of the main portion 101, forming the spreading portions 102 on both sides of the main portion 101. By adopting this technical solution, forming the spreading portions 102 on both sides of the main portion 101 can increase the width of the root of the first gate line 1, thereby increasing the contact area between the first gate line 1 and the first surface, thereby reducing the contact resistance of the first gate line 1 and improving the adhesion between the first gate line 1 and the first surface, preventing the first gate line 1 from falling off.

[0085] In some embodiments, as Figure 2As shown, along the second direction, the width W1 of the main body 101 is 30 μm to 120 μm, so as to facilitate controlling the cross-sectional area of ​​the first gate line 1 within a reasonable range according to the width W1 of the main body 101. For example, the width W1 of the main body 101 is 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, 105 μm, 110 μm, 105 μm or 120 μm, etc.

[0086] like Figure 2 As shown, considering that the width W2 of the spreading portion 102 is too wide, it will extend into the area with opposite polarity and cause leakage. At the same time, if the width W2 of the spreading portion 102 is too small, the adhesion between the first gate line 1 and the first surface will be reduced. Therefore, in this technical solution, along the second direction, the width W2 of the spreading portion 102 is 1μm-60μm to reduce the risk of leakage while ensuring the adhesion between the first gate line 1 and the first surface. For example, the width W2 of the spreading portion 102 can be 1μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm or 60μm, etc.

[0087] Along the second direction, the width of the spreading portion 102 is 5%-50% of the width of the main portion 101 to reduce the risk of leakage while ensuring adhesion between the first gate line 1 and the first surface. For example, the width of the spreading portion 102 is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, or 50% of the width of the main portion 101.

[0088] It should be noted that, in the foregoing, the width of the first gate line 1 is the sum of the widths of the main portion 101 and the spreading portion 102 , while the height of the first gate line 1 is the same as that of the main portion 101 .

[0089] like Figure 2 As shown, along the thickness direction of the battery body, the height h1 of the main body 101 is 8μm to 25μm. This prevents the height h1 of the main body 101 from being too high, which increases the risk of gate breakage, and prevents the height of the main body 101 from being too low, which affects the current transmission efficiency of the gate line. Exemplarily, the height h1 of the main body 101 is 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, or 25μm.

[0090] Along the thickness direction of the battery body, the height of the main body 101 is h1, and the height of the spreading portion 102 is h2, where h2 ≤ 1 / 3 h1. This technical solution ensures that the height h2 of the spreading portion 102 and the height h1 of the main body 101 are in a reasonable ratio, preventing the spreading portion 102 from being too high, which would reduce the cross-sectional area of ​​the main body 101 and increase its resistivity, thereby ensuring the overall current transmission efficiency of the first gate line 1. Exemplary values ​​of h2 are 1 / 3 h1, 0.3 h1, 0.25 h1, 0.2 h1, 0.15 h1, or 0.1 h1, etc.

[0091] In some embodiments, the median particle size of the copper powder contained in the spreading portion 102 is smaller than the median particle size of the copper powder contained in the main portion 101. The copper powder particle size may also be an equivalent diameter. That is, the particle size of the majority of the copper powder contained in the spreading portion 102 is smaller than the particle size of the majority of the copper powder contained in the main portion 101. This configuration allows the particle size of the copper powder contained in the spreading portion 102 to better match the thickness of the spreading portion 102, thereby improving the conductive performance of the spreading portion 102.

[0092] In this embodiment, the battery body includes a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10 and a passivation layer 2. The first doped semiconductor layer 3 and the second doped semiconductor layer 10 have opposite conductivity types so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. The two opposite surfaces of the semiconductor substrate 4 correspond to the first surface and the second surface, respectively. The first doped semiconductor layer 3 is provided on the first surface of the semiconductor substrate 4. The first doped semiconductor layer 3 can be formed in the semiconductor substrate 4 by diffusion, ion implantation, etc., or the first doped semiconductor layer 3 can also be additionally formed on the semiconductor substrate 4 by deposition technology. The passivation layer 2 covers at least one side of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4. The conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 through the passivation layer 2. The carriers collected by the first doped semiconductor layer 3 are conducted through the conductive barrier layer 5 and the first gate line 1.

[0093] The passivation layer 2 can be a single layer or multilayer structure, and includes at least one of aluminum oxide, silicon oxide, and silicon nitride. The thickness of the passivation layer 2 is 50 nm to 400 nm, for example, the thickness of the passivation layer 2 is 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm. The passivation layer 2 can passivate the cell body or the surface of the doped layer, reduce its carrier recombination rate, and further improve the photoelectric conversion efficiency of the solar cell.

[0094] In some embodiments, as Figure 12 As shown, the conductive barrier layer 5 can be discontinuously arranged along the first direction. This can appropriately reduce the consumption of raw materials for the conductive barrier layer 5, save raw materials, and reduce the manufacturing cost of the solar cell. Alternatively, as shown Figure 13 As shown, the conductive barrier layer 5 can be continuously arranged along the first direction, which can increase the contact area between the conductive barrier layer 5 and the first gate line 1 and reduce the contact resistance and current transmission loss between the conductive barrier layer 5 and the first gate line 1.

[0095] In some embodiments, the passivation layer 2 has an opening 2a exposing the first doped semiconductor layer 3 ; the first gate line 1 covers the opening 2a and is electrically connected to the first doped semiconductor layer 3 , so that the first gate line 1 can collect and conduct carriers collected by the first doped semiconductor layer 3 .

[0096] Among them, such as Figure 4 As shown, the multiple openings 2a corresponding to the same gate line can be arranged in at least one row along the first direction, that is, the multiple openings 2a can be distributed in one row and arranged in sequence along the first direction. Alternatively, the multiple openings 2a can be distributed in multiple rows and each row of openings 2a can be arranged in sequence along the first direction. For example, the multiple openings 2a can also be distributed in two rows, three rows or more rows. In this way, the multiple openings 2a are distributed more evenly, and the positions where the first gate line 1 is electrically connected to the first doped semiconductor layer 3 are distributed more evenly, which is beneficial for the first gate line 1 to conduct the current at various positions of the first doped semiconductor layer 3 in a timely manner to avoid local overheating. Alternatively, as Figure 6 As shown, the openings 2a corresponding to the same grid line can be strip-shaped holes, wherein the orthographic projection of the openings 2a corresponding to the same grid line on the first surface is located inside the orthographic projection of the grid line on the first surface.

[0097] In some embodiments, the copper paste in the first gate line 1 directly contacts the first doped semiconductor layer 3, which may reduce the passivation effect of the first doped semiconductor layer 3. Figure 5 and Figure 7 As shown, in this technical solution, a conductive barrier layer 5 is filled in the opening 2a, so that the conductive barrier layer 5 can completely separate the first doped semiconductor layer 3 and the first gate line 1, thereby improving the passivation effect of the first doped semiconductor layer 3. The thickness of the conductive barrier layer 5 can be greater than or equal to the thickness of the passivation layer 2 to ensure the isolation effect. During the manufacturing process, a patterning process (such as a laser perforation process) can be used to form multiple through openings 2a in the passivation layer 2, and then the conductive barrier layer 5 can be formed by electroplating, chemical plating, or other processes. The conductive barrier layer 5 can be made of a metal barrier material such as nickel, silver, or titanium.

[0098] In some embodiments, as Figure 2As shown, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is greater than the thickness of the passivation layer 2. With this arrangement, the portion of the conductive barrier layer 5 that exceeds the opening 2a can extend to the surface of the passivation layer 2 on the side facing away from the semiconductor substrate 4, thereby increasing the width of the conductive barrier layer 5, thereby increasing the contact area between the conductive barrier layer 5 and the first gate line 1, and reducing the contact resistance and current transmission loss between the conductive barrier layer 5 and the first gate line 1.

[0099] On the one hand, if the thickness of the conductive barrier layer 5 is too large, raw materials will be wasted, and the time required for electroplating, chemical plating and other processes will be long, reducing processing efficiency; on the other hand, if the thickness of the conductive barrier layer 5 is too small, it will not be able to effectively isolate the first gate line 1 and the first doped semiconductor layer 3, and ensure the passivation effect of the passivation layer 2. Therefore, in order to take into account the above two aspects, in this technical solution, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is set within a reasonable range of 0.5μm to 5μm, so as to effectively isolate the first gate line 1 and the first doped semiconductor layer 3 and ensure the passivation effect of the passivation layer 2, while reducing the waste of raw materials of the conductive barrier layer 5 and improving processing efficiency. Exemplarily, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm or 5μm, etc.

[0100] like Figure 5 As shown, the solar cell further includes a modified layer 3a. The modified layer 3a is formed in the area of ​​the first doped semiconductor layer 3 corresponding to the opening 2a. Of course, the modified layer 3a can also be formed in the area of ​​the first doped semiconductor layer 3 corresponding to the surrounding area of ​​the opening 2a. The modified layer 3a can be formed by the laser heat during the laser opening 2a process. For example, Figure 9 A modified layer 3a is formed in the area of ​​the first doped semiconductor layer 3 corresponding to the circular opening.

[0101] Among them, such as Figure 10 As shown, the roughness of the modified layer 3a is greater than the roughness of the other parts of the first doped semiconductor layer 3. This configuration can increase the contact area between the conductive barrier layer 5 and the modified layer 3a, improve the adhesion between the conductive barrier layer 5 and the modified layer 3a, and reduce the contact resistance between the conductive barrier layer 5 and the modified layer 3a.

[0102] The degree of crystallization of the modified layer 3a is lower than that of the other parts of the first doped semiconductor layer 3, so that the modified layer 3a can better block the copper paste. The degree of crystallization includes indicators such as crystallization rate, number of grains, and grain size.

[0103] The thickness of the modified layer 3 a may be 5 nm to 20 nm, for example, the thickness of the modified layer 3 a is 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm or 20 nm.

[0104] In some embodiments, as Figure 5 As shown, the passivation layer 2 has a heat-affected zone 2b surrounding the opening 2a. Specifically, during the laser grooving process of the passivation layer 2, the area near the edge of the opening 2a is not removed, but is affected by the heat of the laser, which is called the heat-affected zone 2b. This heat-affected zone 2b is formed around the opening 2a. The shape of the opening 2a can be circular, elliptical, rectangular, or other shapes. The surrounding shape of the heat-affected zone 2b also varies with the shape of the opening 2a, and its annular shape can be a circular ring, an elliptical ring, a rectangular ring, etc. The width of the modified layer 3a can reach the boundary of the heat-affected zone 2b.

[0105] In some embodiments, the width of the heat-affected zone 2b is D, 1 μm ≤ D ≤ 5 μm, so as to avoid the heat-affected zone 2b being too wide and reducing the passivation effect. For example, D can be 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0106] In some embodiments, as Figure 5 As shown, during the laser opening 2a, the laser energy at the edge is appropriately increased, for example, greater than 200 J / cm 2 , the passivation layer 2 material in the heat-affected zone 2b will be opened, and multiple holes and / or cracks will be formed. The purpose of such a setting is that if no holes and / or cracks are formed in the heat-affected zone 2b, the thermal damage to the first doped semiconductor layer 3 corresponding to the position of the heat-affected zone 2b cannot be repaired. In this embodiment, the holes and / or cracks are filled with a conductive material 5a, and the conductive material 5a is electrically connected to the first doped semiconductor layer 3. Specifically, the conductive material 5a in the holes and / or cracks can be in contact with the modified layer 3a or with other parts of the first doped semiconductor layer 3. With such a setting, the first gate line 1 can be electrically connected to the first doped semiconductor layer 3 through the opening 2a while also being electrically connected to the first doped semiconductor layer 3 through the conductive material 5a in the holes and / or cracks. Moreover, the first doped semiconductor layer 3 at the position corresponding to the hole is also a heat concentration area with greater damage (heat concentration areas are prone to holes), and the conductive material 5a can repair the damage at this position. Conductive material 5a is distributed in heat-affected zone 2b in a granular form, and the granular conductive material 5a located farthest from the center of opening 2a defines the width D of heat-affected zone 2b. Conductive material 5a within the holes and / or cracks can be the same as conductive barrier layer 5 and formed together with conductive barrier layer 5 by electroplating or chemical plating.

[0107] On the one hand, if the total area of ​​the orthographic projections of the openings 2a corresponding to the same first gate line 1 on the first surface is too large, damage to the semiconductor substrate 4 during the opening 2a process will increase. On the other hand, if the total area of ​​the orthographic projections of the openings 2a corresponding to the same first gate line 1 on the first surface is too small, the contact area of ​​the first gate line 1 will be too large, affecting the current transmission efficiency. Taking these two aspects into consideration, in this application, the total area of ​​the orthographic projections of the openings 2a corresponding to the same first gate line 1 on the first surface is 20% to 80% of the orthographic projection area of ​​the first gate line 1 on the first surface, so as to reduce damage to the semiconductor substrate 4 during the opening 2a process while ensuring the current transmission efficiency of the first gate line 1.

[0108] In other embodiments, Figure 11 As shown, the area corresponding to the first doped semiconductor layer 3 and the opening 2a includes a plurality of pits 3a1, which can be any shape such as circular or elliptical. The inner diameter of the pit 3a1 is 0.5μm to 2μm, and the inner diameter of the pit 3a1 can be the inner diameter of the largest position of the pit 3a1 or an equivalent inner diameter. Exemplarily, the inner diameter of the pit 3a1 is 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm or 2μm, etc. With this technical solution, the provision of the pit 3a1 can also increase the surface area of ​​the area, thereby increasing the contact area between the conductive barrier layer 5 and the area, and further reducing the contact resistance.

[0109] In other embodiments, the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3 by burning through. Figure 12 As shown, the portion of the conductive barrier layer 5 passing through the passivation layer 2 includes a plurality of conductive channels 5b. That is, one end of the plurality of conductive channels 5b (eg Figure 12 The upper middle end) is electrically connected to the first gate line 1, and the other ends of the plurality of conductive channels 5b (such as Figure 12 The lower and middle ends of the conductive barrier layer 5 are electrically connected to the first doped semiconductor layer 3 to achieve electrical conduction between the first gate line 1 and the first doped semiconductor layer 3 through the multiple conductive channels 5b. Any two adjacent conductive channels 5b are partially connected, that is, any two adjacent conductive channels 5b can be partially continuous; or any two adjacent conductive channels 5b are not connected, that is, the multiple conductive channels 5b are independent and discretely distributed. This helps reduce the difficulty of forming the multiple conductive channels 5b when the conductive barrier layer 5 burns through the passivation layer 2, thereby improving processing efficiency.

[0110] When the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3 by burning through, the passivation layer 2 below the conductive barrier layer 5 does not need to be opened through a patterning step. The conductive barrier layer 5 can be formed by a burn-through paste, and the conductive barrier layer 5 can be formed by printing, transfer, or spraying. Specifically, a high-temperature annealing process can be performed first to allow the corrosive material in the conductive barrier layer 5 (e.g., glass frit in the silver paste) to corrode the passivation layer 2, thereby forming a conductive channel 5b in the passivation layer 2. The conductive channel 5b is the metal material of the conductive barrier layer 5 that penetrates the passivation layer 2 and contacts the doped semiconductor layer.

[0111] When the conductive barrier layer 5 is discontinuously arranged along the first direction, the conductive barrier layer 5b includes a plurality of sub-conductive barrier layers spaced apart along the first direction, and each sub-conductive barrier layer may include a plurality of conductive channels 5b.

[0112] On the one hand, if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too large, the carrier transmission efficiency will be reduced; if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too small, the process difficulty of forming the sub-conductive barrier layers will be increased, resulting in reduced production efficiency. Therefore, in order to take into account the above two aspects, in this technical solution, if Figure 12 As shown, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is set within a reasonable range of 0.2 mm to 3 mm to improve the carrier transmission efficiency while reducing the process difficulty of forming the sub-conductive barrier layers and improving production efficiency. It can be understood that the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction refers to the distance between the closest positions of the boundaries of the two adjacent sub-conductive barrier layers. Exemplarily, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction can be 0.2 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, 2.4 mm, 2.5 mm, 2.8 mm or 3 mm.

[0113] In some embodiments, the orthographic projection of the sub-conductive barrier layer on the first surface is a circle, an ellipse, a strip, or a polygon, wherein the polygon can be a square, a triangle, a trapezoid, an irregular polygon, or the like.

[0114] In some embodiments, the first doped semiconductor layer 3 further includes a metal crystal layer 3b located on the side of the conductive barrier layer 5 closest to the semiconductor substrate 4. For example, the silver in the conductive barrier layer 5 forms an AgSi alloy phase with silicon, which exhibits high thermal stability and mechanical strength. In this technical solution, chemical bonding within the metal crystal layer 3b enhances the adhesion between the metal elements contained in the conductive barrier layer 5 and silicon, reducing the risk of delamination of the conductive barrier layer 5 due to thermal or mechanical stress. Furthermore, the metal crystal layer 3b has a high electrical conductivity, and the provision of the metal crystal layer 3b can also improve the carrier transfer efficiency between the conductive barrier layer 5 and the first doped semiconductor layer 3.

[0115] In some embodiments, the thickness of the metal crystal layer 3b along the thickness direction of the semiconductor substrate 4 is less than or equal to the thickness of the first doped semiconductor layer 3. In this technical solution, the metal crystal layer 3b is formed at least in the area near the surface of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4. This improves the adhesion of the conductive barrier layer 5 and the carrier transfer efficiency while reducing the processing difficulty of the metal crystal layer 3b. In some embodiments, a portion of the metal crystal layer 3b may abut the interface layer (for example, an oxide layer including first and second interface layers) between the first doped semiconductor layer 3 and the semiconductor substrate 4, or the distance from the interface layer may be less than 10 nm.

[0116] In some embodiments, along the thickness direction of the semiconductor substrate 4, the thickness of the metal crystal layer 3b is 2 / 3 of the thickness of the first doped semiconductor layer 3. This improves the adhesion of the conductive barrier layer 5 and the carrier transfer efficiency while preventing excessive heat from reaching the semiconductor substrate 4 during the burn-through process and damaging the semiconductor substrate 4. For example, the thickness of the metal crystal layer 3b can be 2 / 3, 1 / 3, 1 / 2, 3 / 5, etc., of the thickness of the first doped semiconductor layer 3.

[0117] In some embodiments, as Figure 14 As shown, the conductive barrier layer 5 includes a plurality of pores 5c, and there are no organic matter and / or metal particles in the pores 5c. This arrangement is conducive to improving the heat dissipation effect of the conductive barrier layer 5 and preventing local overheating.

[0118] When the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3 by burning through, the thickness of the conductive barrier layer 5 is 0.1 μm to 10 μm. While ensuring that the conductive barrier layer 5 can burn through the passivation layer 2, the waste of raw materials of the conductive barrier layer 5 is reduced, thereby improving processing efficiency. It can be understood that at the location of the conductive channel 5b, the thickness of the conductive barrier layer 5 is the distance from the side surface of the conductive barrier layer 5 facing away from the semiconductor substrate 4 to the end of the conductive channel 5b close to the semiconductor substrate 4 along the thickness direction of the semiconductor substrate 4. Exemplarily, in this technical solution, the thickness of the conductive barrier layer 5 is 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm.

[0119] In some embodiments, the solar cell further includes a second doped semiconductor layer 10 and a plurality of second gridlines 8, wherein the second gridlines 8 are disposed on a side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4. The first gridlines 1 and the second gridlines 8 are made of the same material, and the first gridlines 1 and the second gridlines 8 have opposite polarities. Parameters such as the resistivity, cross-sectional area, height, width, and spacing between adjacent second gridlines 8 of the second gridlines 8 can be found in the description of the first gridlines 1 above and are not further described here.

[0120] In the case where the solar cell is a back-contact cell, the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are both located on the first surface, and the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are arranged at intervals along the second direction. Specifically, the second doped semiconductor layer 10 and the first doped semiconductor layer 3 can be arranged alternately and alternately in strips, or can be arranged alternately and alternately in interdigitated shapes. The first gate line 1 and the second gate line 8 are both formed on the first surface, the first gate line 1 is electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is electrically connected to the second doped semiconductor layer 10. The second gate line 8 also extends along the first direction and is arranged along the second direction, and a plurality of first gate lines 1 and a plurality of second gate lines 8 are alternately distributed along the second direction. In this technical solution, the passivation layer 2 can cover the side of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 facing away from the semiconductor substrate 4, the first gate line 1 passes through the opening 2a of the passivation layer 2 to be electrically connected to the first doped semiconductor layer 3, and the second gate line 8 passes through the opening 2a of the passivation layer 2 to be electrically connected to the second doped semiconductor layer 10.

[0121] When the solar cell is a bifacial cell, the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are located on the first surface and the second surface respectively, and the first gate line 1 is formed on the first surface and electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is formed on the second surface and electrically connected to the second semiconductor layer.

[0122] In some embodiments, the passivation layer 2 further covers the side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4, the conductive barrier layer 5 further passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10, and a plurality of second gate lines 8 are disposed on the conductive barrier layer 5. Specifically, a portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3, and another portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10. It is understood that the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 and the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 should be non-conductive to prevent leakage. In this manner, the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 can separate the second gate line 8 from the second doped semiconductor layer 10, thereby ensuring the passivation effect of the doped semiconductor layer while also ensuring the electrical conductivity between the second gate line 8 and the second doped semiconductor layer 10.

[0123] The conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 can be electrically connected to the second doped semiconductor layer 10 by burning through or opening a hole in the passivation layer 2. The material, thickness, structure and other technical features of the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 can refer to the description of the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 above, and will not be repeated here.

[0124] In the case where the conductive barrier layer 5 can pass through the passivation layer 2 and be electrically connected to the first doped semiconductor layer 3 or the second doped semiconductor layer 10 by burning through, the first doped semiconductor layer 3 and the semiconductor substrate 4 have the same doping type. In this way, the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower, and carriers can more easily pass through the interface between the first doped semiconductor layer 3 and the semiconductor substrate 4.

[0125] The conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 includes multiple sub-conductive barrier layers spaced apart along a first direction, with the minimum distance between two adjacent sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 along the first direction being L1. The conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 includes multiple sub-conductive barrier layers spaced apart along the first direction, with the minimum distance between two adjacent sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 along the first direction being L2. Because the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower than the transmission resistance between the second doped semiconductor layer 10 and the semiconductor substrate 4, in this technical solution, L2 is less than L1, thereby reducing the distance between the multiple sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 and increasing the density of the multiple sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10. This balances the transmission efficiency of carriers through the first doped semiconductor layer 3 and the second doped semiconductor layer 10, reduces the current difference between the first doped semiconductor layer 3 and the second doped semiconductor layer 10, and thus improves the overall power generation efficiency of the solar cell.

[0126] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 is set within a reasonable range of 1 mm ≤ L1 ≤ 3 mm to improve carrier transmission efficiency while reducing the difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L1 can be 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, 2.4 mm, 2.5 mm, 2.8 mm, or 3 mm.

[0127] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is set within a reasonable range of 0.2 mm ≤ L2 ≤ 2 mm to improve carrier transmission efficiency while reducing the difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L2 can be 0.2 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm, or 2 mm.

[0128] In actual application, the material of the semiconductor substrate 4 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 4 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 4 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the solar cell finally obtained has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0129] For example, the semiconductor substrate 4 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0130] The first doped semiconductor layer 3 includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport properties. Therefore, when the first doped semiconductor layer 3 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is conducive to improving the photoelectric conversion efficiency of the solar cell. Of course, the first doped semiconductor layer 3 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped semiconductor layer 10 also includes one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0131] In some embodiments, a first interface layer 9 is provided between the first doped semiconductor layer 3 and the semiconductor substrate 4, and a second interface layer 11 is provided between the second doped semiconductor layer 10 and the semiconductor substrate 4. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region of the semiconductor substrate 4 where the semiconductor layer is formed, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 9 can be set according to the material of the first doped semiconductor layer 3 and actual requirements, and the material and thickness of the second interface layer 11 can be set according to the material of the second doped semiconductor layer 10 and actual requirements, and are not specifically limited here.

[0132] For example, the first doped semiconductor layer 3 may be a doped polysilicon layer, the first interface layer 9 may be a tunneling oxide layer, the second doped semiconductor layer 10 may be a doped polysilicon layer, and the second interface layer 11 may be a tunneling oxide layer.

[0133] Of course, when the first doped semiconductor layer 3 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 9 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon. When the second doped semiconductor layer 10 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 11 includes one or more of an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, and an intrinsic nanocrystalline silicon.

[0134] The materials of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs). In terms of conductivity type, the first doped semiconductor layer 3 can be an n-type doped layer, and the second doped semiconductor layer 10 can be a p-type doped layer; alternatively, the first doped semiconductor layer 3 can be a p-type doped layer, and the second doped semiconductor layer 10 can be an n-type doped layer.

[0135] It should be noted that the first gate line 1 can be a fine gate or a main gate.

[0136] For a solar cell without a busbar, the fine grids of the solar cell include a first fine grid and a second fine grid, and the first fine grid and the second fine grid are arranged alternately along the second direction. The first fine grid can be the first grid line 1 described above. In this embodiment, the first fine grid and the second fine grid can be arranged continuously and uninterruptedly along the first direction or intermittently to form multiple sections.

[0137] For a solar cell with a main grid, the fine grid of the solar cell includes a first fine grid and a second fine grid, and the main grid of the solar cell includes a first main grid and / or a second main grid, and the first fine grid and / or the first main grid is the above-mentioned first grid line 1. In this embodiment, the first fine grid and the second fine grid can be arranged continuously and uninterruptedly along the first direction, or can be discontinuously formed into multiple sections. In one case, the number of the first main grid and the second main grid are both multiple, and the multiple first main grids and the second main grids are arranged in sequence along the first direction. Any first fine grid and any second fine grid between adjacent first main grids and second main grids are arranged continuously and uninterruptedly along the first direction, and the multiple first fine grids are all electrically connected to the first main grid, and the multiple second fine grids are all electrically connected to the second main grid. In another case, when there is only one first main grid and one second main grid, at least one first fine grid is electrically connected to the first main grid, and at least one second fine grid is electrically connected to the second main grid.

[0138] When the first gate line 1 serves as the main gate, the width of the first gate line 1 is greater than or equal to 400 μm, for example, 400 μm, 420 μm, 450 μm, 480 μm, 500 μm, 520 μm, 550 μm, 580 μm, or 600 μm, etc. This can prevent the main gate from being too narrow, causing the slurry forming the main gate to flow into the gap between adjacent insulating blocks 6, resulting in the main gate being disconnected.

[0139] In the case of a back-contact solar cell, first gridlines 1 and second gridlines 8 are both formed on the first surface. The solar cell also includes a first conductive member 7 and a second conductive member. The first conductive member 7 is electrically connected to the plurality of first gridlines 1 and has an insulating block 6 between it and the plurality of second gridlines 8. The second conductive member is electrically connected to the plurality of second gridlines 8 and has an insulating block 6 between it and the plurality of first gridlines 1. This arrangement uses the insulating blocks 6 to separate the first conductive member 7 from the plurality of second gridlines 8 and the second conductive member from the plurality of first gridlines 1, thereby reducing the risk of leakage.

[0140] Along the second direction, the spacing between adjacent insulating blocks 6 is greater than or equal to 100 μm. This allows for a sufficient distance between adjacent insulating blocks 6 to allow for slurry flow. This prevents the slurry forming the insulating blocks 6 from covering grid lines that should not be covered, ensuring the stability of the electrical connection between the first grid line 1 and the first conductive member 7, and between the second grid line 8 and the second conductive member, thereby improving the stability of the solar cell performance. For example, the spacing between adjacent insulating blocks 6 can be 100 μm, 110 μm, 120 μm, or 130 μm, etc.

[0141] Along the thickness direction of the cell body, the thickness of the insulating block 6 is less than or equal to 80 μm, for example, the thickness of the insulating block 6 is 80 μm, 70 μm, 60 μm, 50 μm, 40 μm, 30 μm, or 20 μm. This ensures the isolation effect of the insulating block 6 and prevents the slurry forming the insulating block 6 from climbing up to cover the grid lines that it should not cover, thereby improving the stability of the solar cell performance.

[0142] like Figure 15 and Figure 16 As shown, when the first conductive member 7 is a main grid, the main grid can be in direct physical contact and electrical connection with the first grid line 1 (first fine grid). Figure 17 As shown, the intersection of the first conductive member 7 (main grid) and the first grid line 1 (first fine grid) has a side protrusion 7a protruding along the first direction. That is, along the first direction, the width of the position where the first conductive member 7 (main grid) has the side protrusion 7a is greater than the width of the remaining positions of the first conductive member 7. With this arrangement, the side protrusion 7a can increase the contact area between the first conductive member 7 (main grid) and the first grid line 1 (first fine grid), thereby reducing the transmission resistance between the first conductive member 7 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell. In addition, in this technical solution, when there are spreading portions 102 on both sides of the first grid line 1, the spreading portions 102 can limit the slurry forming the first conductive member 7 from flowing too far in the first direction, thereby preventing the formed side protrusion 7a from being too wide.

[0143] In addition, an embodiment of the present application further provides a photovoltaic assembly, comprising a solar cell and a first conductive member 7 provided in any of the above embodiments. The first conductive member 7 extends along the second direction and is electrically connected to the first grid line 1. The first conductive member 7 and the first grid line 1 can be electrically connected by direct physical contact, or electrically connected through a bonding layer. Compared with the prior art, the beneficial effects of the photovoltaic assembly provided in the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell, and will not be described in detail here.

[0144] In the photovoltaic module, Figure 18As shown, the first conductive member 7 is a welding ribbon, which connects at least two solar cells to form a battery structure (i.e., a battery string structure). In this case, the solar cell can be a main grid-less battery, such as Figure 19 As shown, the soldering ribbon is electrically connected to the first grid line 1 via a bonding layer 12. The bonding layer 12 can be specifically solder or a conductive adhesive. Using this technical solution, the soldering ribbon is directly electrically connected to the first grid line 1, achieving the effect of reducing shading and resistance loss. When the first conductive member 7 is the main grid, the photovoltaic module will also include a soldering ribbon. The soldering ribbon needs to be welded to the main grid via a bonding material to achieve series or parallel connection of multiple cells at the module end.

[0145] In some embodiments, as Figure 20 As shown, the first grid line 1 includes thickened segments 1e spaced apart along a first direction, and along a second direction, the width of the thickened segments 1e is greater than the width of the remaining portion of the first grid line 1. That is, the thickened segments 1e are provided at the location where the first grid line 1 is connected to the first conductive member 7. The thickened segments 1e can be integrally formed with the remaining portion of the first grid line 1, or can be formed by separate processing. With this technical solution, the provision of the thickened segments 1e can increase the contact area between the first grid line 1 and the bonding layer 12, thereby reducing the transmission resistance between the bonding layer 12 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell.

[0146] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0147] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: The battery body comprises a first surface and a second surface arranged opposite to each other; a conductive barrier layer, disposed at least on the first surface; A plurality of first gate lines are provided on the conductive barrier layer, extending along a first direction and arranged along a second direction, wherein the first direction and the second direction intersect; the first gate lines are formed of a non-burn-through paste, the resistivity of the first gate lines is 6 μΩ·cm to 60 μΩ·cm, and the cross-sectional area of ​​the first gate lines along a plane perpendicular to the first direction is greater than or equal to 250 μm 2 ; Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1-0.5, and w ≥ 30 μm; The distance between two adjacent first grid lines is 0.6 mm to 1.3 mm.

2. The solar cell according to claim 1, wherein 140 μm ≥ w ≥ 30 μm; and / or, 5 μm ≥ h ≥ 25 μm.

3. The solar cell according to claim 1, wherein The first gate line includes copper powder and organic matter; The copper powder includes at least flake particles and spherical particles.

4. The solar cell according to claim 3, characterized in that The copper powder further includes one or more of linear particles, V-shaped particles, polygonal particles and columnar particles; and / or the median diameter of the flaky particles is 0.8 μm to 5 μm; and / or the median thickness of the flaky particles is 100 nm to 500 nm; and / or the median particle size of the spherical particles is 100 nm to 500 nm.

5. The solar cell according to claim 4, wherein The mass percentage of the flaky particles is 35% to 60%; and / or, the mass percentage of the spherical particles is 35% to 60%; and / or, the tap density of the flaky particles is 3g / ml to 6g / ml; and / or, the tap density of the spherical particles is 3.5g / ml to 5.5g / ml; and / or, the specific surface area of ​​the flaky particles is 0.4m 2 / g~0.7m 2 / g; and / or, the specific surface area of ​​the spherical particles is 1.5m 2 / g~3.5m 2 / g; and / or, the organic matter includes one or more of saturated / unsaturated fatty acids containing 8-18 carbon atoms, silane coupling agents, PVP, and thiols.

6. The solar cell according to claim 1, wherein The first gate line includes a main portion and a spreading portion arranged along the second direction, and the main portion and the spreading portion extend along the first direction; Along the second direction, the width W1 of the main body is 30μm to 120μm; and / or, along the second direction, the width W2 of the spreading portion is 1μm-60μm; and / or, along the second direction, the width of the spreading portion is 5%-50% of the width of the main body; and / or, along the thickness direction of the battery body, the height h1 of the main body is 8μm to 25μm; and / or, along the thickness direction of the battery body, the height of the main body is h1, the height of the spreading portion is h2, h2≤1 / 3h1; and / or, the median value of the copper powder particle size contained in the spreading portion is smaller than the median value of the copper powder particle size contained in the main body.

7. The solar cell according to claim 1, wherein The battery body includes a semiconductor substrate, a first doped semiconductor layer and a passivation layer; The first doped semiconductor layer is provided on the first surface of the semiconductor substrate, the passivation layer covers the side of the first doped semiconductor layer away from the semiconductor substrate, and the conductive barrier layer passes through the passivation layer and is electrically connected to the first doped semiconductor layer.

8. The solar cell according to claim 7, characterized in that The conductive barrier layer is disposed discontinuously along the first direction; or, the conductive barrier layer is disposed continuously along the first direction.

9. The solar cell according to claim 7, wherein: The passivation layer has an opening exposing the first doped semiconductor layer; the first gate line covers the opening and is electrically connected to the first doped semiconductor layer.

10. The solar cell according to claim 9, characterized in that The conductive barrier layer is filled in the opening; The thickness of the portion of the conductive barrier layer corresponding to the region of the opening is greater than the thickness of the passivation layer; and / or the thickness of the portion of the conductive barrier layer corresponding to the region of the opening is 0.5 μm to 5 μm.

11. The solar cell according to claim 10, characterized in that The first doped semiconductor layer and the region corresponding to the opening form a modified layer; The roughness of the modified layer is greater than that of other portions of the first doped semiconductor layer, and / or the degree of crystallization of the modified layer is lower than that of other portions of the first doped semiconductor layer.

12. The solar cell according to claim 9, wherein The passivation layer has a heat-affected zone surrounding the opening; The width of the heat-affected zone is D, 1μm≤D≤5μm; and / or the heat-affected zone includes a plurality of holes and / or cracks, the holes and / or cracks are filled with conductive material, and the conductive material is electrically connected to the first doped semiconductor layer.

13. The solar cell according to claim 9, characterized in that The total area of ​​the orthographic projections of the openings corresponding to the same first gate line on the first surface is 20% to 80% of the orthographic projection area of ​​the first gate line on the first surface; or, the number of the openings corresponding to the same first gate line is multiple and distributed at intervals; or, the openings corresponding to the same first gate line are arranged in a strip shape.

14. The solar cell according to claim 9, wherein The area of ​​the first doped semiconductor layer corresponding to the opening includes a plurality of pits; the inner diameter of the pits is 0.5 μm to 2 μm.

15. The solar cell according to claim 7, wherein The conductive barrier layer passes through the passivation layer and is electrically connected to the first doped semiconductor layer in a burn-through manner.

16. The solar cell according to claim 15, characterized in that The first doped semiconductor layer further includes a metal crystal layer located on a side of the conductive barrier layer close to the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is less than or equal to the thickness of the first doped semiconductor layer; Or, along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is 2 / 3 of the thickness of the first doped semiconductor layer; or, along the thickness direction of the semiconductor substrate, the distance between the metal crystal layer and the interface layer between the first doped semiconductor layer and the semiconductor substrate is less than 10nm.

17. The solar cell according to claim 15, characterized in that The conductive barrier layer includes a plurality of pores therein; and / or the conductive barrier layer has a thickness of 0.1 μm to 10 μm.

18. The solar cell according to claim 7, characterized in that The solar cell further includes a second doped semiconductor layer and a plurality of second gate lines, wherein the second doped semiconductor layer has a conductivity type opposite to that of the first doped semiconductor layer, and the second gate lines are arranged on a side of the second doped semiconductor layer away from the semiconductor substrate; The first gate line and the second gate line are made of the same material, and have opposite polarities; The second doped semiconductor layer and the plurality of second gate lines are arranged on the first surface, the plurality of second gate lines extend along the first direction and are arranged along the second direction, the first doped semiconductor layer and the second doped semiconductor layer are alternately distributed along the second direction, and the plurality of first gate lines and the second gate lines are alternately distributed along the second direction; or, the second doped semiconductor layer and the plurality of second gate lines are arranged on the second surface, the plurality of second gate lines extend along the first direction and are arranged along the second direction.

19. The solar cell according to claim 18, characterized in that The passivation layer also covers the side of the second doped semiconductor layer away from the semiconductor substrate. The conductive barrier layer also passes through the passivation layer and is electrically connected to the second doped semiconductor layer. A plurality of second gate lines are arranged on the conductive barrier layer.

20. The solar cell according to claim 19, characterized in that The conductive barrier layer passes through the passivation layer and is electrically connected to the first doped semiconductor layer or the second doped semiconductor layer by burning through; the first doped semiconductor layer has the same doping type as the semiconductor substrate; the conductive barrier layer includes a plurality of sub-conductive barrier layers spaced apart along a first direction; Among the multiple sub-conductive barrier layers electrically connected to the first doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L1; among the multiple sub-conductive barrier layers electrically connected to the second doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L2; L2<L1; and / or, 1mm≤L1≤3mm; and / or, 0.2mm≤L2≤2mm.

21. The solar cell according to claim 18, wherein A plurality of second gate lines are disposed on the first surface, extending along the first direction and arranged along the second direction, and the plurality of first gate lines and second gate lines are alternately distributed along the second direction; The solar cell further includes a first conductive member and a second conductive member, wherein the first conductive member is electrically connected to the first grid lines and has an insulating block between the first conductive member and the second grid lines; the second conductive member is electrically connected to the second grid lines and has an insulating block between the first conductive member and the second grid lines.

22. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 21 and a first conductive member, wherein the first conductive member extends along the second direction and is electrically connected to the first grid line.

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