Hierarchical storage queues

Abstract

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, on a processor using tiered storage queues. In one aspect, a system includes a processor configured to receive a load instruction having an address corresponding to an entry in a tiered store queue. The processor performs a store-to-load forwarding process for the load instruction, including performing a hierarchical search to find the entry in the hierarchical storage queue, where performing the hierarchical search includes searching in the first partition of the hierarchical storage queue prior to searching the entry in the second partition of the hierarchical storage queue. The processor reads a value of the entry from a tiered store queue for load instructions.

Description

Background Art

[0001] This specification relates to techniques for performing memory operations using tiered storage queues.

[0002] In modern computing, loading from and storing to memory are performance-critical memory operations in processors. The store queue of the load-store unit (LSU) within the processor tracks in-flight store entries in the processing window to ensure the correctness of data written to memory by store instructions in the presence of out-of-order (OOO) execution. When data is requested to be read from memory by a store instruction, the store queue of the LSU can ensure the correctness of the data. A conventional technique for optimizing data reads from memory is to perform a store-to-load forwarding (STLF) process. STLF allows data to be forwarded from store instructions in the window to load instructions within the processor, rather than using store instructions to write data out to memory and using load instructions to read the same data back.

[0003] As the processing window size increases, the processor can increase the store queue size to accommodate a larger number of entries in order to track in-flight store entries. However, increasing the store queue size may result in increased latency when executing a STLF because the processor must read a larger number of store queue entries. On the other hand, a smaller store queue can achieve faster STLF performance, but a smaller store queue may also result in performance losses due to the introduction of more store instruction stalls when the store queue is full. Summary of the Invention

[0004] This specification describes a system for performing memory operations using a hierarchical storage queue with multiple partitions, which can significantly improve the performance of a STLF for large processor windows. When using a hierarchical storage queue, the system can accelerate searches for store instructions by first searching in the first partition of the storage queue, where they are more likely to be found. If the store instruction is not in the first partition, the system can search in other partitions of the storage queue. The hierarchical structured approach disclosed herein can increase processor efficiency by improving STLF performance.

[0005] Particular embodiments of the subject matter described in this specification can be implemented so as to realize one or more of the following advantages.

[0006] The described methods and systems improve the performance of a store queue included in a processor (e.g., a store queue with a large number of instructions associated with a large processing window size). For example, the described methods and systems allow for more efficient execution of a STLF by dividing the store queue into two partitions. The system executes the STLF at a relatively faster rate in the first partition than in the second partition. By executing the STLF faster in the first partition, the system improves the overall efficiency of the store queue by finding store instructions at a faster rate, which reduces the latency when writing data to memory.

[0007] Additionally, if the system searches for and locates data to be forwarded in a first partition, the system can save power by avoiding searching for data in a second partition.

[0008] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram of an example system.

[0010] Figure 2 This is an example diagram of a logically divided hierarchical storage queue structure.

[0011] Figure 3 This is an example diagram of a physically divided hierarchical storage queue structure.

[0012] Figure 4 is a flow chart of an example process for performing memory operations on a processor using a hierarchical memory queue.

[0013] Like reference numbers and designations in the various drawings refer to like elements. DETAILED DESCRIPTION

[0014] Figure 1 An example system 100 is shown. System 100 is an example of a system in which the systems, components, and techniques described below are implemented.

[0015] System 100 includes a processor 102 coupled to a main memory 118 (e.g., a cache, random access memory (RAM), read-only memory (ROM), etc.). As described above, processor 102 can use a load-store unit (LSU) to perform the STLF process. Processor 102 includes a load-store unit (LSU) 106 and main execution logic 104.

[0016] The LSU 106 communicates with the main execution logic 104 to receive and send data. For example, communications 120 between the LSU 106 and the main execution logic 104 may include store instructions, load instructions, stored values, etc. The processor 102 communicates with the main memory 118 to receive and send data. For example, communications 120 between the processor 102 and the main memory 118 may include memory addresses, stored values, etc.

[0017] LSU 106 includes a load reservation station 108 and a store queue 110 .

[0018] The store queue 110 may include a content addressable memory (CAM) structure that stores in-transit store instructions, which may support simultaneous searches. The store queue 110 is associated with at least one tail pointer that represents the entry most recently added to the store queue 110 by the processor 102. The processor 102 obtains the most recently added entry from the load reservation station 108. Additionally, the store queue 110 is associated with at least one head pointer that represents the oldest entry in the store queue 110 (e.g., the entry last added by the processor). Conventionally, the processor 102 retires entries (e.g., retired stores 114) from the store queue 110 in a first-in, first-out (FIFO) manner. The processor 102 may retire the entry at the head pointer (e.g., the oldest entry). In some examples, the processor 102 retires the entry to a store gather buffer, as described with reference to FIG. Figure 3 described in further detail.

[0019] Regardless of the implementation, the load reservation station 108 at the LSU 106 can receive a communication 116 from the main execution logic to fetch or read data. The load reservation station 108 sends a load instruction 112 for the data to the store queue 110. The load instruction 112 includes an address corresponding to an entry in the store queue 110 associated with the data.

[0020] In some implementations, the processor 102 may use the store queue 110 to perform a STLF on one or more of the entries of the load instruction 112. The store queue 110 keeps track of pending store instructions within a processing window. When executing a subsequent load instruction, the processor 102 may check the pending store instructions of the store queue 110 to determine whether the data to be loaded is present in the store queue 110. If the data is present in the pending store instruction, the processor 102 may perform a STLF by retrieving the data from the pending store instruction of the store queue 110 instead of from the main memory 118. The processor 102 may forward the data from the pending store instruction to the load instruction 112 instead of writing the data out to the main memory 118 and reading the same data back into the main memory 118 along with the load instruction 112, which improves the efficiency of the store queue 110.

[0021] In this example, the processor 102 performs a STLF process on the load instruction 112 by performing a hierarchical search of the storage queue 110 (e.g., a hierarchical storage queue). In this case, the hierarchical storage queue 110 is divided into a first partition and a second partition. Before searching the second partition of the hierarchical storage queue 110 for the entry included in the load instruction 112, the processor 102 first searches the first partition. The first partition may be smaller than the second partition, and the first partition may include the most recently stored entries that are more likely to be requested by the load instruction 112. Therefore, the processor 102 can perform the STLF more efficiently, which can generally reduce the latency of performing the STLF in the hierarchical storage queue.

[0022] In some implementations, the storage queue 110 is logically divided into two partitions. The storage queue 110 is partitioned using a head pointer and a tail pointer of the storage queue 110, along with a third pointer representing the first entry to be searched in the first partition, which will be referred to as Figure 2 Described in further detail.

[0023] Alternatively, in another implementation, the tiered storage queue 110 is physically divided into two partitions, where each partition is a separate storage queue device. Each storage queue device is associated with a head pointer and a tail pointer that are associated with the storage and retirement of entries of the tiered storage queue 110, which will be referred to herein. Figure 3 Described in further detail.

[0024] Figure 2 is an example diagram of a logically divided hierarchical storage queue structure. For convenience, Figure 200 will be described as being implemented by a processor. For example, a processor appropriately configured according to this specification (e.g., Figure 1 The processor 102) can implement Figure 200.

[0025] Conventional store queues have been implemented as an overall circular queue associated with a store queue tail pointer and a store queue head pointer. The offset range between store queue tail pointer 208 and store queue head pointer 204 indicates the region of store queue 202 with active entries. The position of store queue head pointer 204 indicates the oldest entry in the processor, and the position of store queue tail pointer 208 indicates the most recently added entry (e.g., the newest entry) in the processor.

[0026] In this example, store queue 202 is an overall circular queue that is logically divided into a first partition and a second partition by a third pointer (e.g., store queue STLF pointer 206). The first partition ranges from store queue tail pointer 208 to store queue STLF pointer 206, and the second partition ranges from store queue STLF pointer 206 to store queue head pointer 204. Store queue STLF pointer 206 indicates the first entry that the processor searches for in the first partition when executing STLF. The first partition is smaller than the second partition.

[0027] Store queue STLF pointer 206 is located at an offset from store queue tail pointer 208, where the offset is a STLF window 210. STLF window 210 can be constructed globally for the processor. In this case, the offset between STLF pointer 206 and store queue tail pointer 208 is a fixed value for the processor, where STLF window 210 is applicable to each load instruction and each active entry for executing STLF. Alternatively, the STLF window can be local for each load instruction. In this case, the processor can set a relatively smaller offset, thereby generating a smaller STLF window 210, which can improve the efficiency of executing STLF in the first partition.

[0028] The processor performs a STLF by searching for an active entry within the STLF window 210 starting at the entry at the store queue STLF pointer 206. The first partition is smaller than the second partition, which improves the efficiency of performing the STLF in the first partition and throughout the store queue 202. Thus, the first partition supports relatively faster STLF performance than the second partition (e.g., the second partition supports a slower STLF). The processor performs a hierarchical search by determining whether the entry from the load instruction is not located in the first partition. If not, only in this case does the processor start searching in the second partition instead, starting at the location indicated by the head pointer.

[0029] For example, the storage queue 202 may have a storage queue size of 128 entries and a maximum STLF window size of 64. If the storage queue STLF pointer 206 is located at the entry at index 100 (e.g., the 100th entry in the storage queue), the processor determines that the newest entry (e.g., the most recently added entry) is located at the entry at index 100. The processor determines that the current STLF window 210 spans a certain number of entries (e.g., 36 entries) by calculating the difference between the number of entries and the maximum STLF window size (e.g., 100 - 64). The processor can perform STLF more efficiently in the first partition because the first partition contains a relatively smaller number of entries (e.g., 36 entries) than the second partition (e.g., 64 entries).

[0030] This technology retires the stored entries in a first-in, first-out (FIFO) manner. The processor can receive a store instruction that includes a new entry, and the processor stores the new entry in the store queue 202. Therefore, as the processor stores the new entry, the store queue tail pointer 208 shifts in the circular queue to indicate the latest entry. As the store queue tail pointer 208 shifts, the store queue STLF pointer 206 also shifts to maintain the maximum STLF window size. The store queue head pointer 204 also shifts in the circular queue so that the STLF window 210 includes active entries (e.g., not retired entries).

[0031] To maintain the maximum STLF window size, the processor retires entries to the store gather buffer from the store queue 202. The processor first retires the oldest entry in the store queue 202, where the oldest entry is indicated by the store queue head pointer 204. Once the processor retires the oldest entry in the store queue 202, the processor may write new entries from store instructions in the hierarchical store queue.

[0032] Figure 3 is an example diagram of a physically divided hierarchical storage queue structure. For convenience, Figure 300 will be described as being implemented by a processor. For example, a processor appropriately configured according to this specification (e.g., Figure 1 The processor 102) can implement Figure 300.

[0033] The load store unit (LSU) 302 includes a load reservation station 304 , a store queue 306 , and a store gather buffer 322 .

[0034] In this implementation, the storage queue 202 is physically divided into separate hierarchical storage queue devices (a first storage queue 308 and a second storage queue 310). These storage queue devices have unequal sizes, with the first storage queue 308 being smaller than the second storage queue 310. The first storage queue 308 includes a first storage queue tail pointer 314 and a first storage queue head pointer 316, and the second storage queue 310 includes a second storage queue tail pointer 318 and a second storage queue head pointer 320. The first storage queue tail pointer 314 and the second storage queue tail pointer 318 each indicate the most recent entry in the corresponding partition. The first storage queue head pointer 316 and the second storage queue head pointer 320 each indicate the oldest entry in the corresponding partition.

[0035] In this case, the processor receives a load instruction with an entry. The processor performs a hierarchical search for the data associated with the entry by searching first store queue 308. If the processor finds the entry in first store queue 308, the processor can execute the STLF relatively quickly due to the smaller size and relatively lower number of entries in first store queue 308. If the processor determines that the value is not in first store queue 308, the processor searches second store queue 310. The processor executes the STLF in second store queue 310 one cycle slower than in first store queue 308 to reduce the STLF timing pressure associated with the larger size of second store queue 310 and the larger number of entries in second store queue 310.

[0036] In this implementation, the processor retires entries based on the positions of the entries' reference pointers in first store queue 308 and second store queue 310. The processor receives a store instruction to store value 326 in store queue 306. Store queue 306 receives value 326 from load reservation station 304. The processor determines whether to retire older entries in store queue 306 by determining whether first store queue 308 is full (e.g., contains a finite number of entries for first store queue 308).

[0037] If first store queue 308 is not full, the processor writes value 326 to store queue 306. If first store queue 308 is full, the processor ejects (e.g., moves) entry 312 to second store queue 310. Entry 312 is the oldest entry in first store queue 308, as indicated by first store queue head pointer 316. In some cases, the processor ejects entry 312 in first store queue 308 when the processor commits the entry.

[0038] If the second store queue is full, the processor may move retired entries 324 from the second store queue 310 to the store gathering buffer 322. In some cases, the processor drains the retired entry 324 in the second store queue 310 when the processor commits the retired entry 324.

[0039] The processor writes the value 326 to the first store queue tail pointer 314 of the first store queue 308. By writing the value 326 to the first store queue 308, the processor can perform the STLF more efficiently because the processor is more likely to use the most recently added entry to forward data.

[0040] For example, the storage queue 306 can have a storage queue size of 128 entries. The first storage queue 308 can contain 32 entries, and the second storage queue 310 can contain 96 entries. The processor can perform the STLF more efficiently in the first storage queue 308 because the first storage queue 308 contains a relatively smaller number of entries (e.g., 32) than the second storage queue 310 (e.g., 96). In addition, the first storage queue 308 contains the newest entries that are most likely to be used in the STLF, which further improves the efficiency of the storage queue 306.

[0041] Figure 4 is a flow chart of an example process for performing a backend sacrifice process. For convenience, process 400 will be described as being performed by a processor. For example, a processor appropriately configured according to this specification (e.g., Figure 1 The processor 102) can perform process 400.

[0042] In some cases, the processor may receive a load instruction (402) having an address corresponding to an entry in a hierarchical storage queue. For example, referring to Figure 2 , the processor receives a load instruction with the address of an entry in the store queue and the corresponding value located in the LSU. Figure 3 , the processor receives a load instruction with an address and value corresponding to an entry in a load reservation station of an LSU. In this case, the load reservation station sends the value to the store queue for the processor to execute STLF.

[0043] The processor performs a hierarchical search for the load instruction to find an entry in the store queue (404). The processor searches the hierarchical store queue to determine whether the data requested in the load instruction is present in the store queue. The processor searches the first partition of the store queue before searching the second partition of the store queue.

[0044] In one example, reference Figure 2, the storage queue is logically divided into a first partition and a second partition. In another example, referring to Figure 3 , the storage is physically divided into two separate storage queue devices, where the first storage queue device is a first partition and the second storage queue device is a second partition. In both cases, the first partition is relatively smaller than the second partition, and the processor executes the STLF relatively faster in the first partition than in the second partition because the processor must search fewer entries in the first partition than in the second partition.

[0045] The processor reads the value of the entry from the hierarchical storage queue for the load instruction (406). If the processor finds the entry in any of the partitions, the processor can perform STLF by forwarding the value of the entry from the first partition or the second partition of the hierarchical storage queue to the pending load instruction. For example, the processor can forward the data from the active entry of the storage queue instead of writing the data out to main memory.

[0046] This specification uses the term "configured" in conjunction with system and computer program components. With respect to a system of one or more computers to be configured to perform a particular operation or action, it is meant that the system has installed thereon software, firmware, hardware, or a combination thereof that, in operation, causes the system to perform those operations or actions. With respect to one or more computer programs to be configured to perform a particular operation or action, it is meant that the one or more programs include instructions that, when executed by a data processing device, cause the device to perform the operations or actions.

[0047] Embodiments of the subject matter and functional operations described in this specification may be implemented in digital electronic circuit systems, in tangibly embodied computer software or firmware, in computer hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more thereof. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by a data processing device or for controlling the operation of a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more thereof. Alternatively or in addition, the program instructions may be encoded on an artificially generated propagated signal (e.g., a machine-generated electrical, optical, or electromagnetic signal), generating an artificially generated propagated signal to encode information for transmission to a suitable receiver device for execution by the data processing device.

[0048] The term "data processing equipment" refers to data processing hardware and includes all types of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer or multiple processors or computers. The equipment may also be or further include special-purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may optionally include code that creates an execution environment for a computer program, for example, code constituting processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of these.

[0049] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script, or code, may be written in any form of programming language (including compiled or interpreted languages ​​or declarative or procedural languages); and it may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or code portions). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a data communications network.

[0050] In this specification, the term "engine" is used broadly to refer to a software-based system, subsystem, or process that is programmed to perform one or more specific functions. Typically, an engine will be implemented as one or more software modules or components installed on one or more computers in one or more locations. In some cases, one or more computers will be dedicated to a specific engine; in other cases, multiple engines can be installed and run on the same one or more computers.

[0051] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by special purpose logic circuitry (e.g., an FPGA or ASIC), or by a combination of special purpose logic circuitry and one or more programmed computers.

[0052] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit will receive instructions and data from a read-only memory or random access memory, or both. The basic elements of a computer are a central processing unit for performing or executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory can be supplemented by or incorporated into a dedicated logic circuit system. Typically, a computer will also include one or more mass storage devices for storing data, such as magnetic disks, magneto-optical disks, or optical disks, or be operatively coupled to receive data from them or transfer data to them or both. However, a computer does not necessarily have such devices. In addition, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few.

[0053] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0054] To provide for user interaction, embodiments of the subject matter described in this specification may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices may also be used to provide for user interaction; for example, feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input. Furthermore, a computer may interact with a user by sending documents to and receiving documents from a device used by the user; for example, by sending a web page to a web browser on a user's device in response to a request received from the web browser. Furthermore, a computer may interact with a user by sending text messages or other forms of messages to a personal device (e.g., a smartphone running a messaging application) and receiving a response message from the user in return.

[0055] A data processing device used to implement a machine learning model may also include, for example, dedicated hardware accelerator units for processing general-purpose and computationally intensive parts of machine learning training or production (i.e., inference, workloads).

[0056] Machine learning models can be implemented and deployed using a machine learning framework (e.g., the TensorFlow framework).

[0057] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back-end component (e.g., as a data server), or includes a middleware component (e.g., an application server), or includes a front-end component (e.g., a client computer with a graphical user interface, a web browser, or an app through which a user can interact with an implementation of the subject matter described in this specification), or any combination of one or more such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0058] A computing system may include a client and a server. The client and server are generally remote from each other and typically interact via a communication network. The relationship of client and server arises by virtue of computer programs running on respective computers that establish a client-server relationship with each other. In some embodiments, the server transmits data (e.g., an HTML page) to a user device, for example, for the purpose of displaying data to a user interacting with the device acting as a client and receiving user input from the user. Data generated at the user device (e.g., the results of the user interaction) can be received from the device at the server.

[0059] In addition to the embodiments described above, the following embodiments are also innovative:

[0060] Embodiment 1 is a method executed on a processor using a hierarchical storage queue, comprising:

[0061] receiving a load instruction having an address corresponding to an entry in the hierarchical storage queue;

[0062] performing a tiered search to find the entry in the tiered storage queue, wherein performing the tiered search includes searching in a first partition of the tiered storage queue before searching for the entry in a second partition of the tiered storage queue; and

[0063] The value of the entry is read from the hierarchical storage queue for the load instruction.

[0064] Embodiment 2 is the method of embodiment 1, wherein the first partition is smaller than the second partition.

[0065] Embodiment 3 is the method of any one of embodiments 1 to 2, wherein performing the hierarchical search comprises: A store-to-load forwarding process is performed for the load instruction.

[0066] Embodiment 4 is the method of any one of embodiments 1 to 33, wherein the tiered storage queue is a circular queue that is logically partitioned using a pointer representing a first entry to be searched in the first partition.

[0067] Embodiment 5 is the method of embodiment 4, wherein the pointer representing the first entry in the first partition is located at an offset from a tail pointer representing a most recently added entry in the tiered storage queue.

[0068] Embodiment 6 is the method of embodiment 5, wherein performing the hierarchical search comprises:

[0069] determining that the entry is not located in the first partition; and

[0070] In response, a search is performed in the second partition starting at a position indicated by a head pointer, the head pointer representing the oldest entry in the tiered storage queue.

[0071] Embodiment 7 is the method of embodiment 6, wherein the first partition ranges from the tail pointer to the pointer representing the first entry, and the second partition ranges from the pointer representing the first entry to the head pointer.

[0072] Embodiment 8 is the method of embodiment 5, wherein the offset is a store-to-load window of the store-to-load forwarding process.

[0073] Embodiment 9 is the method of embodiment 8, wherein the size of the store-to-load window is global to the processor or local to the load instruction of the store-to-load forwarding process.

[0074] Example 10 is the method of Example 6, further comprising: receiving a store instruction to store a value in the tiered storage queue; determining to retire entries from the tiered storage queue to a storage aggregation buffer; retiring the entry to the store gather buffer in a first-in, first-out manner, wherein the entry is the oldest entry indicated by the head pointer; and The value from the store instruction is written into the tiered storage queue.

[0075] Embodiment 11 is the method of any one of embodiments 1 to 33, wherein the tiered storage queue is physically partitioned using separate tiered storage queue devices.

[0076] Embodiment 12 is the method of embodiment 11, wherein performing the hierarchical search comprises: determining that the entry is not located in the first partition; and In response, a search is performed in a second device implementing the second partition.

[0077] Embodiment 13 is a method as described in embodiment 12, wherein the range of the first partition is from a first tail pointer to a first head pointer, and the range of the second partition is from a second tail pointer to a second head pointer, wherein the first tail pointer and the second tail pointer indicate the most recent entry in the corresponding partition, and the first head pointer and the second head pointer indicate the oldest entry in the corresponding partition.

[0078] Embodiment 14 is the method of embodiment 11, wherein performing the store-to-load forwarding process at the second partition is at least one cycle slower than performing the store-to-load forwarding process at the first partition.

[0079] Embodiment 15 is the method of embodiment 11, further comprising: receiving a store instruction to store a value in the tiered storage queue; determining whether to retire entries of the tiered storage queue to a storage aggregation buffer by determining whether the first partition and the second partition are full; and The value of the store instruction is written to the first partition or the second partition based on determining whether the first partition and the second partition are full.

[0080] Embodiment 16 is a system comprising a processor having a tiered storage queue, wherein the processor is configured to perform the method of any one of embodiments 1 to 15.

[0081] Embodiment 17 is one or more storage media storing instructions, which are operable to cause a data processing device to perform the method of any one of embodiments 1 to 15 when executed by the data processing device.

[0082] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather should be interpreted as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may involve a variant of a sub-combination or sub-combination.

[0083] Similarly, although operations are depicted in the drawings and recited in the claims in a particular order, this should not be construed as requiring that such operations be performed in the particular order shown or in an ordered order, or that all illustrated operations be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0084] Specific embodiments of the present subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

Claims

1. A method executed on a processor using a hierarchical storage queue, the method comprising: receiving a load instruction having an address corresponding to an entry in the hierarchical storage queue; performing a tiered search to locate the entry in the tiered storage queue, wherein performing the tiered search includes searching in a first partition of the tiered storage queue before searching for the entry in a second partition of the tiered storage queue; as well as The value of the entry is read from the hierarchical storage queue for the load instruction.

2. The method according to claim 1, wherein The first partition is smaller than the second partition.

3. The method according to any one of claims 1 to 2, further comprising: A store-to-load forwarding process is performed for the load instruction.

4. The method according to any one of claims 1 to 3, wherein The tiered storage queue is a circular queue that is logically partitioned using a pointer indicating a first entry to be searched for in the first partition.

5. The method according to claim 4, wherein: The pointer representing the first entry in the first partition is located at an offset from a tail pointer representing a most recently added entry in the tiered storage queue.

6. The method according to claim 5, wherein: Performing the hierarchical search includes: determining that the entry is not located in the first partition; and In response, a search is performed in the second partition starting at a position indicated by a head pointer, the head pointer representing the oldest entry in the tiered storage queue.

7. The method according to claim 6, wherein: The first partition ranges from the tail pointer to the pointer representing the first entry, and the second partition ranges from the pointer representing the first entry to the head pointer.

8. The method of claim 5, wherein: The offset is the store-to-load window of the store-to-load forwarding process.

9. The method of claim 8, wherein: The store-to-load window size is global to the processor or local to the load instruction of the store-to-load forwarding process.

10. The method of claim 6, further comprising: receiving a store instruction to store a value in the tiered storage queue; determining to retire entries from the tiered storage queue to a storage aggregation buffer; retiring the entry to the store gather buffer in a first-in, first-out manner, wherein the entry is the oldest entry indicated by the head pointer; as well as The value from the store instruction is written into the tiered storage queue.

11. The method according to any one of claims 1 to 3, wherein The tiered storage queues are physically partitioned using separate tiered storage queue devices.

12. The method of claim 11, wherein: Performing the hierarchical search includes: determining that the entry is not located in the first partition; and In response, a search is performed in a second device implementing the second partition.

13. The method of claim 12, wherein: The first partition ranges from a first tail pointer to a first head pointer, and the second partition ranges from a second tail pointer to a second head pointer, wherein the first tail pointer and the second tail pointer indicate the most recent entry in the corresponding partitions, and the first head pointer and the second head pointer indicate the oldest entry in the corresponding partitions.

14. The method of claim 11, wherein: Executing the store-to-load forwarding process at the second partition is at least one cycle slower than executing the store-to-load forwarding process at the first partition.

15. The method of claim 11, further comprising: receiving a store instruction to store a value in the tiered storage queue; determining whether to retire entries of the tiered storage queue to a storage aggregation buffer by determining whether the first partition and the second partition are full; as well as The value of the store instruction is written to the first partition or the second partition based on determining whether the first partition and the second partition are full.

16. A system comprising a processor having a hierarchical storage queue, wherein: The processor is configured to perform the method of any one of claims 1 to 15.

17. One or more storage media storing instructions operable, when executed by a data processing apparatus, to cause the data processing apparatus to perform the method of any one of claims 1 to 15.

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