Electronic device with patch antenna in package substrate

Abstract

An electronic device (100) includes a multi-level package substrate (108) having a first level, a second level, and a third level (L1-L3) including respective dielectric layers and conductive features, a semiconductor die (102), and a package structure (106), the first level (L1) comprises a first trace layer (M1) having an antenna (110) and a first via layer (V1) having a portion of a ground wall (GW) spaced laterally outward from and surrounding the antenna (110), and the second level (L2) comprises a second trace layer (M2) having a ground plane (GP) connected to the ground wall, the semiconductor die (102) is attached to the first level (L1) of the multi-level package substrate (108), and the package structure (106) includes a molding compound enclosing the semiconductor die (102) and extending on one side of the antenna (110), where the material and thickness of the package structure molding compound may be adjusted to improve performance.

Description

Background Art

[0001] Antennas can be integrated into electronic devices or systems to implement wireless communication functions for millimeter wavelengths, terahertz frequencies, and other applications. Integrated antennas can be implemented on-chip, within semiconductor packages, and on host system printed circuit boards (PCBs). However, due to ohmic losses (e.g., I 2 Due to R losses, on-chip antennas operating in the millimeter wavelength and terahertz bands can suffer from poor radiation efficiency and the high dielectric loss tangent of the encapsulation molding compound at these frequencies. On-package antennas can also suffer performance degradation due to the dielectric losses of the encapsulation material, and the resulting high-order surface wave modes can cause radiated power losses, further limiting the radiation efficiency of planar antenna structures. Furthermore, the proximity of off-chip components can cause reflections and absorption of electromagnetic energy, which can reduce the directivity and overall radiation performance of these antennas. Summary of the Invention

[0002] In one aspect, an electronic device includes a multi-level packaging substrate, a semiconductor die attached to a first level of the multi-level packaging substrate, and a packaging structure. The multi-level packaging substrate has a first level, a second level, and a third level, each of the first level, the second level, and the third level including a respective dielectric layer and patterned conductive features, the first level, the second level, and the third level extending in respective first, second, and third planes in a first direction and an orthogonal second direction, the second level extending between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally outward from and surrounding the antenna, and the second level including a second trace layer including a ground plane connected to the ground wall. The packaging structure includes a molding compound enclosing the semiconductor die and extending over one side of the antenna.

[0003] In another aspect, a system includes a circuit board and an electronic device. The electronic device includes a multi-level packaging substrate, a semiconductor die attached to a first level of the multi-level packaging substrate, and a packaging structure. The multi-level packaging substrate has a first level, a second level, and a third level, each of the first level, the second level, and the third level including a corresponding dielectric layer and patterned conductive features, the first level, the second level, and the third level extending in a first direction and a second direction orthogonal to the first, second, and third planes, respectively, the second level extending between the first and third levels along a third direction orthogonal to the first and second directions, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally outward from and surrounding the antenna, and the second level including a second trace layer including a ground plane connected to the ground wall. The packaging structure includes a molding compound enclosing the semiconductor die and extending on one side of the antenna.

[0004] In another aspect, a method of manufacturing an electronic device includes: manufacturing a multi-level packaging substrate, including forming a first level, a second level, and a third level, each of the first level, the second level, and the third level including a respective dielectric layer and a respective patterned conductive feature, the second level being between the first level and the third level, the first level including a first trace layer including an antenna and a first via layer including a portion of a ground wall spaced laterally outward from and surrounding the antenna, and the second level including a second trace layer including a ground plane connected to the ground wall. The method further includes: flip-chip attaching a semiconductor die to the first level of the multi-level packaging substrate; and forming a packaging structure including a molding compound enclosing the die and extending over one side of the antenna. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a top plan view of an electronic device having a leadless package, a flip-chip mounted semiconductor die, and a multi-level packaging substrate with an integrated antenna and an epoxy molding compound encapsulation extending over the antenna.

[0006] Figure 1A It is along Route 1A-1A Figure 1 A cross-sectional side view of an electronic device.

[0007] Figure 1B yes Figure 1 and 1A A partial cross-sectional top view of a first metal trace layer in a multi-level packaging substrate of an electronic device.

[0008] Figure 1C yes Figure 1-1B A partial cross-sectional top view of a first through-hole layer in a multi-level packaging substrate of an electronic device.

[0009] Figure 1D yes Figure 1-1C A partial top plan view of a second metal trace layer in a multi-level packaging substrate of an electronic device.

[0010] Figure 1E is included with the circuit board Figure 1-1D A partial side view of a system of electronic devices.

[0011] Figure 2 is a flow chart of a method of manufacturing an electronic device.

[0012] Figure 3-22 It is based on experience Figure 2 Method of manufacturing process Figure 1 A partial side view of an electronic device.

[0013] Figure 23 is included Figure 1-1E Graphs of simulated reflection coefficient and peak gain as a function of frequency for an antenna in an electronic device.

[0014] Figure 24 is a graph with curves showing simulated radiation efficiency of various encapsulant materials as a function of epoxy molding compound encapsulation thickness. DETAILED DESCRIPTION

[0015] In the drawings, the same reference numerals always refer to the same elements, and the various features are not necessarily drawn to scale. In addition, the term "couple" or "couples" includes indirect or direct electrical connections or mechanical connections or a combination thereof. For example, if a first device is coupled to or coupled with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. One or more operating characteristics of various circuits, systems and / or components are described below in the context of functions, which in some cases are generated by the configuration and / or interconnection of various structures when the circuit system is powered and operating. Example structures include a layer or material described as being above or on another layer or material, which can be a layer or material directly on and in contact with another layer or material, where other materials (e.g., impurities or artifacts or residual materials from the manufacturing process) may be present between the layer or material and the other layer or material.

[0016] Unless otherwise stated, the word "about," "substantially," or "approximately" preceding a value means + / - 10% of the stated value. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc. may be referred to herein as first, second, third, etc., such as a first terminal and a second terminal, a first well, a second well, and a third well, etc., which should not be construed as limiting the claims. The various disclosed structures and methods of the present disclosure can be advantageously applied to the manufacture of electronic devices such as integrated circuits. Although such examples can be expected to provide various improvements, the present disclosure does not require a specific result unless explicitly recited in a specific claim.

[0017] First reference Figure 1-1E , Figure 1 and 1A An example electronic device 100 (e.g., an integrated circuit or a single-component electronic device) is shown packaged in a quad flat no-lead (QFN) structure with a flip-chip mounted semiconductor die 102 to provide a flip-chip enhanced QFN (FCeQFN) package, wherein an antenna is integrated into a multi-level packaging substrate and encapsulated by any epoxy-based encapsulation molding compound for millimeter wavelength or terahertz band wireless communications. Figures 1B-1D showing portions of an example 300-GHz rectangular patch implementation of antenna structures in a first level and a second level of a multi-level package substrate, and Figure 1E A partial side view of a system including an electronic device 100 mounted on a host system circuit board 140 is shown.

[0018] like Figure 1 and 1A As best shown in FIG. 1 , a semiconductor die 102 has conductive terminals 104 and conductive pads 105 coupled to respective ones of the conductive terminals 104. In one example, the conductive pads 105 are or include aluminum. In this or another embodiment, the conductive terminals 104 are or include copper. A molded package structure 106 encloses the semiconductor die 102 and a portion of a multi-level package substrate 108 ( Figure 1A ).like Figures 1A-1DAs shown, the conductive pads 105 are mechanically and electrically connected to conductive features of the multi-level packaging substrate 108 through solder connections to copper metal pillars 107. Certain conductive pads 105 and conductive terminals 104 provide RF interconnects from the semiconductor die 102 to the integrated antenna in a ground-signal-ground (GSG) configuration through conductive features (e.g., lines or traces) in the multi-level packaging substrate 108. This allows RF signals to flow from the semiconductor die 102 to the antenna of the multi-level packaging substrate 108 through the conductive terminals 104, conductive pads 105, and pillars 107. The electronic device 100 provides an integrated antenna-in-package (AiP) or antenna-on-package (AoP) transmission line in a multi-level packaging substrate solution for a radio frequency (RF) front-end module for wireless applications with an integrated antenna.

[0019] The multi-level package substrate 108 is generally rectangular in shape having a top or first level L1, a second level L2, and a bottom or third level L3, wherein conductive leads 109 allow the electronic device 100 to be soldered to a host printed circuit board or other host system structure (e.g., Figure 1A and 1E 140 is shown. In another embodiment (not shown), the multi-level package substrate 108 includes more than three levels, with the conductive leads 109 on the last or lowest level. In one example, the electronic device 100 has leads 109 along four sides (e.g., a QFN configuration). In another example, the electronic device 100 has leads 109 along fewer than or more than four sides. In one example, the electronic device 100 has a compact form factor with single-digit millimeter length and width dimensions along respective orthogonal first and second directions X and Y.

[0020] The multi-level packaging substrate 108 includes a conductive metal antenna 110 having a generally rectangular shape, which extends along the top side of the multi-level packaging substrate 108 in the first level L1. Figure 1A As shown, the molded package structure 106 covers a portion of the antenna 110 , and the molded package structure 106 has a thickness T over the antenna 110 along the third direction Z. In one embodiment, the conductive features of the respective levels L1 - L3 are or include copper, such as electroplated copper formed and patterned during fabrication of the multi-level package substrate 108 .

[0021] like Figure 1A and 1EAs shown, the levels L1-L3 each include a respective dielectric layer and a respective patterned conductive feature (e.g., a patterned copper trace layer and copper via features) extending in respective first, second, and third planes (e.g., XY planes) of a first direction X and a second direction Y. The levels L1-L3 are arranged in a stack along a third direction Z orthogonal to the first direction X and the second direction Y, wherein the second level L2 extends between the respective first level L1 and the third level L3 along the third direction Z.

[0022] The first level L1 has a first dielectric layer 121 ( Figures 1A-1C and 1E) and a first patterned conductive feature comprising a first metal trace layer M1 ( Figure 1A and 1B ) and the first metal via layer V1 ( Figure 1A and 1C ) conductive metal (eg, copper) features. The first level L1 includes antenna 110 ( Figure 1-1B ).

[0023] The second level L2 extends along the third direction Z between the first level L1 and the third level L3 and has a second dielectric layer 122 ( Figure 1A 、 1D and 1E) and a second patterned conductive feature in a second XY plane, the second patterned conductive feature comprising a second metal trace layer M2 ( Figure 1A 、 1D and 1E) and the second metal via layer V2 ( Figure 1A and 1E ) conductive metal features. The third level L3 has a third dielectric layer 123 ( Figure 1A and 1E ) and a third patterned conductive feature in a third XY plane, the third patterned conductive feature comprising conductive features of a third metal trace layer M3 and a third via layer V3.

[0024] like Figure 1AAs shown, the first metal trace layer M1 and its features have a thickness 124 along the third direction Z (e.g., 10-30 μm, such as about 20 μm, with an etch-back size of about 0-5 μm), the conductive metal features of the first via layer V1 have a thickness 125 (e.g., about 45 μm) along the third direction Z that is greater than the thickness 124, and the first via layer thickness 125 corresponds to the separation distance between the first metal layer M1 and the second metal layer M2 along the third direction Z. The conductive metal features of the second metal trace layer M2 have a thickness 126 along the third direction Z (e.g., 10-30 μm, such as about 20 μm), and the features of the second via layer V2 have a thickness 127 along the third direction Z (e.g., about 45 μm). The conductive metal features of the third metal trace layer M3 have a thickness 128 (e.g., 25-45 μm, such as approximately 35 μm) along the third direction Z, and the features of the third via layer V3 have a thickness 129 (e.g., approximately 35 μm) along the third direction Z, wherein the etch-back dimension is approximately 0-10 μm. In one example, the pillars 107 of the example multi-level package substrate 108 have a thickness of 15-45 μm, such as approximately 30 μm, along the third direction Z.

[0025] The multi-level package substrate provides a ground structure 112, which is provided at the first level L1 and the second level L2 ( Figures 1A-1D ) provides a partial cover or shield with an open top. Figure 1A and 1B As best shown in FIG, a ground structure 112 is spaced apart from, laterally surrounds, and underlies the antenna 110. The ground structure 112 includes a ground wall GW that is laterally spaced apart from and surrounds the antenna 110 in a first plane. In the example shown, the first via layer V1 includes a first portion of the ground wall GW, and the first trace layer M1 of the first level L1 includes a second portion of the ground wall GW that is laterally spaced apart from and surrounds the antenna 110 in the first plane. In another example (not shown), the ground wall GW is formed entirely in the first via layer V1 of the first level L1. The ground structure 112 also includes a ground plane GP ( Figure 1A and 1D ), the second trace layer is connected to the ground plane GP and is spaced apart from the antenna 110 by a spacing distance 130 ( Figure 1A )(which corresponds to the first via layer thickness 125).

[0026] like Figure 1 、 1B As best shown in FIG1C , antenna 110 includes a generally rectangular main portion and a microstrip feed portion ( Figure 1 and 1B), wherein the antenna 110 has a lateral separation distance 131 (e.g., approximately 25 μm) from the surrounding upper (e.g., second) portion of the ground plane of the ground structure 112. In one example, the rectangular patch antenna 110 has a length 132 (e.g., approximately 375 μm) along the first direction X. The microstrip feed portion in the example shown has a thickness of approximately 20 μm (e.g., along the Figure 1A In the example shown, a 50 ohm microstrip feed line is formed in the top or first metal layer M1 (e.g., a thickness 124 in the third direction Z) and has a width 133 (e.g., approximately 72 μm) along the second direction Y. Furthermore, in this example, the second metal layer M2 ground plane GP has a similar thickness (e.g., approximately 20 μm) and is spaced apart from the antenna 110 along the third direction Z by a spacing distance 130 (e.g., approximately 45 μm below the patch antenna 110). The rectangular patch antenna 110 and the example shown have a width 134 (e.g., approximately 469.2 μm) along the second direction Y.

[0027] The semiconductor die 102 is solder-attached to a first level L1 of a multi-level package substrate 108, for example, using flip-chip surface mount technology, and the package structure 106 includes a molding compound that encloses the semiconductor die 102 and extends over the top side of the antenna 110. The underside of the semiconductor die 102 is spaced apart along a third direction Z by a spacing distance set by the height of the conductive terminals 104 and the thickness of the pillars 107 after flip-chip solder reflow, for example, about 20 to 200 μm, wherein the metal pillars 107 on the first trace level M1 provide antenna and ground wall connections from the semiconductor die 102 to the antenna 110.

[0028] The antenna 110 extends in the top level L1 of the multi-level package substrate and is encapsulated by the molded package structure 106. In one example, a ground wall GW beneath the epoxy molding compound encapsulated by the package structure 106 helps suppress high-order surface wave modes. Additionally, in this example, a ground structure 112 extends laterally around the periphery of the antenna 110 to help isolate the antenna 110 from surrounding metal layers, including a host printed circuit board (e.g., Figure 1A ) metal layer) isolation to improve the directivity and gain of the antenna 110 for wireless communication during operation.

[0029] The operation of the antenna 110 for wireless communication may be facilitated by the dimensional characteristics of the multi-level package substrate and the material and thickness T of the molded package structure 106. In one example, the semiconductor die 102 is configured to enable the antenna 110 to operate at a wavelength λ and a molding compound thickness T (e.g., Figure 1A and 1E), the thickness of the molding material is 0.125λ or greater along the third direction Z above the antenna 110. In this or another example, the thickness T of the molding material is approximately 0.25λ. In another example, the thickness T of the molding material is λ / 4+ / -30%. In another example, the thickness T of the molding material is approximately λ / 4+nλ / 2, where n is a positive integer. As shown below in combination Figure 24 To further describe, the radiation efficiency of the antenna 110 exhibits a local maximum at approximately λ / 4 and at a further thickness increment of λ / 2 (eg, λ / 4+nλ / 2), which may be beneficial to the radiation efficiency of the electronic device 100 .

[0030] The material (e.g., an epoxy-based molding compound) of the molded package structure 106 can be selected to enhance the wireless communication performance of the underlying antenna 110. For example, the dielectric loss tangent (e.g., tan δ) of the material affects the dissipation of electrical energy provided by the antenna 110 due to various physical processes such as dielectric relaxation, dielectric resonance, and losses from nonlinear processes. In one example, the molding compound of the package structure 106 has a loss tangent value less than 0.02. In this or another example, the loss tangent value of the molding compound is approximately greater than or equal to 0.001 and approximately less than or equal to 0.01. In these or the above examples, the local maximum of the radiation efficiency at the molding compound thickness T of λ / 4+nλ / 2 can gradually decrease as the value of n increases because the effect of the dielectric loss tangent value increases with the thickness T of the package structure 106 on the top side of the antenna 110.

[0031] Figure 1E A partial side view of an example system is shown with the illustrated electronic device 100 soldered to a printed circuit board 140. In this example, the top copper layer of the printed circuit board 140 has conductive (e.g., copper) features that can provide a ground plane that then surrounds the electronic device 100, which can help isolate the antenna 110, thereby improving antenna directivity and gain in the millimeter wavelength or terahertz bands.

[0032] Reference Figure 2-22 , Figure 2 A method 200 of manufacturing an electronic device is shown, and Figure 3-22 An electronic device 100 is shown undergoing a manufacturing process according to method 200. Figure 2 At 201 in FIG. 1 , wafer processing is performed to fabricate semiconductor die 102 including conductive terminals 104 and conductive pads 105 as described above. In one example, the fabricated semiconductor die 102 includes a transmitter circuit system (not shown) to provide a radio frequency signal to the antenna 110 relative to a ground or reference voltage of a ground structure 112 during powering operations of the semiconductor die 102. Wafer-level processing at 201 also includes die singulation or separation (not shown) to separate individual semiconductor die 102 from the processed wafer.

[0033] Figure 2 The method 200 further includes fabricating the multi-level package substrate 108 and its levels L1-L3 at 202-232, wherein the conductive leads 109 are in the third level L3 and the patch antenna 110 is in the first level L1. In one example, at 202, the levels L1-L3 are constructed one at a time, starting with depositing a seed copper layer on a metal carrier. Figure 3 An example is shown in which a chemical vapor deposition process 300 is performed to deposit a copper seed layer 302 on a metal carrier 301. In one example, the process 300 deposits the copper seed layer on both the top and bottom sides of the carrier 301 in the illustrated orientation.

[0034] The method 200 continues at 204 by depositing and patterning a first plating mask. Figure 4 An example is shown in which a process 400 is performed in which a first plating mask 402 is deposited on a copper seed layer 302 on the top side of a carrier 301 and patterned. Figure 2 Electroplating of the copper features of the first trace layer continues at 206 . Figure 5 An example is shown in which an electroplating process 500 is performed to deposit copper in the exposed areas of the mask 402 to form copper metal trace features of a first trace layer M1 of a first level L1 on the exposed portion of the copper seed layer 302 on the top side of the carrier 301 (including the antenna 110 and the upper second portion of the ground wall GW). At 208, the first plating mask is removed and a first through-hole plating mask is deposited and patterned. Figure 6 An example is shown in which the process 600 is performed to remove the first plating mask, form and pattern a second plating mask 602 , and perform electroplating to form a first via layer V1 .

[0035] At 210 , the method 200 continues with seed layer etching and compression molding of the dielectric of the first level L1 . Figure 7 An example is shown in which a compression molding process 700 is performed, ie a first dielectric layer 121 of electrically insulating material is compression molded between and over patterned conductive features M1 and V1 of the first level L1. A grinding operation is performed at 212 and a second copper seed layer is deposited. Figure 8 An example is shown in which a grinding process 800 is performed to grind and planarize the top side of the structure. The grinding process 800 removes an upper portion of the compression molded dielectric electrically insulating material to expose an upper portion of the conductive via feature V1 of the first level L1, and the grinding process 800 can continue to reduce the thickness of the conductive copper and dielectric features of the first level L1 along the third direction Z to a desired final thickness, such as Figure 8A second copper seed layer 802 is then deposited on the planarized top side of the first level L1, as shown. Figure 8 shown.

[0036] exist Figure 2 At 214 in FIG. 1 , the same or similar sequence of steps and materials may be used to form a second and subsequent level L2 of another plating mask ( Figure 9-13 ) and L3( Figure 14-18 ) deposition and patterning. Figure 9 An example is shown in which a process 900 is performed in which a second plating mask 902 is deposited on the top side of the seed layer 802 and patterned. Figure 2 Electroplating of the copper features of the second metal trace layer M2 continues at 216 . Figure 10 An example is shown in which an electroplating process 1000 is performed to deposit copper in the exposed areas of mask 902 to form copper metal trace layer features M2 on the exposed portions of first level L1. At 218, the second plating mask is removed, followed by depositing and patterning a second via mask and electroplating a second via copper feature. Figure 11 An example is shown in which the process 1100 is performed to remove the plating mask 902 , form and pattern the plating mask 1102 , and plate the second via layer features V2 of the second level L2 .

[0037] The method 200 continues at 220 with etching the remaining portion of the second seed layer for the second level and compression molding. Figure 12 An example is shown where a process 1200 is performed to etch a seed layer and compression mold a second dielectric layer 122 with electrically insulating material between and over patterned conductive features M2 and V2 of the second level L2. A grinding operation is performed at 222 and a third copper seed layer is deposited. Figure 13 An example is shown in which a grinding process 1300 is performed to grind and planarize the top side of the structure. The grinding process 1300 removes an upper portion of the compression molded dielectric electrically insulating material to expose an upper portion of the conductive via feature V2 of the second level L2, and the grinding process 1300 can continue to reduce the thickness of the conductive copper and dielectric features of the second level L2 along the third direction Z to a desired final thickness, such as Figure 13 As shown. Figure 13 As further shown in FIG, a third copper seed layer 1302 is then deposited on the planarized top side of the second level L2.

[0038] For the illustrated four level example, the third level construction begins at 224 where a third plating mask is deposited on the third seed layer and patterned. Figure 14An example is shown in which a process 1400 is performed in which a third plating mask 1402 is deposited on the top side of the second level L2 and patterned. Figure 2 The copper features of the third trace layer are continued to be electroplated at 226. Figure 15 An example is shown in which an electroplating process 1500 is performed to deposit copper in the exposed areas of mask 1402 to form copper metal trace layer features M3 of a third level L3 on the exposed portions of second level L2. At 228, the third plating mask is removed, a third via mask is deposited and patterned, and the third via features are electroplated. Figure 16 An example is shown in which the process 1600 is performed to remove the third plating mask, deposit and pattern a third via plating mask 1602, and plate a third via layer feature V3.

[0039] The method 200 continues at 230 with compression molding of the third level L3. Figure 17 An example is shown in which a compression molding process 1700 is performed to compression mold the third dielectric layer 123 with electrically insulating material between and over the patterned conductive features of the third level L3. At 232, a grinding operation is performed. Figure 18 An example is shown in which a grinding process 1800 is performed to grind and planarize the top side of the structure. The grinding process 1800 removes the upper portion of the compression molded dielectric insulating material to expose the upper portion of the conductive via feature V3 of the third level L3. The grinding process 1800 can continue to reduce the thickness of the conductive copper and dielectric features of the third level L3 along the third direction Z to a desired final thickness, such as Figure 18 In one example, further processing (not shown) may be used to form conductive pillars 107 on selected portions of the top side of the first level L1, as shown. Figure 18 As shown in .

[0040] exist Figure 2 At 234 , the semiconductor die 102 is attached to the first level L1 of the multi-level package substrate 108 . Figure 19 An example is shown in which a flip chip die attach process 1900 is performed to mount the semiconductor die 102 on the multi-level package substrate 108. The method also includes a thermal treatment for solder reflow or adhesive curing at 236. Figure 20 An example is shown in which a thermal process 2000 is performed to reflow the solder to complete flip-chip mounting of the semiconductor die 102 , wherein the conductive terminals 104 are soldered to electrically couple the conductive terminals to corresponding conductive pads (e.g., pillars 107 ) of the first level L1 of the multi-level package substrate 108 .

[0041] The method 200 includes, at 238 , encapsulation molding. Figure 21An example is shown in which a molding process 2100 is performed to form the molded package structure 106 to a desired thickness T, as described above. The molding process 2100 uses a designed material having the properties shown and described above in conjunction with the electronic device 100, and a mold configured to provide the desired final thickness T according to the above aspects.

[0042] The method 200 also includes package separation at 240 . Figure 22 An example is shown in which a sawing or laser cutting process 2200 is performed to separate individual finished packaged electronic devices 100 from a concurrently processed panel or array structure along lines 2202. The separation process 2200 leaves the sides of the conductive leads 109 exposed along respective coplanar sides of the finished packaged electronic devices 100.

[0043] Figure 23 and 24 The simulated antenna performance results of the electronic device 100 described above are shown. Figure 23 Graph 2300 in shows simulated reflection coefficient S-parameters and peak gain performance as a function of frequency for the antenna 110 in an example embodiment of an encapsulated electronic device 100 with and without an epoxy molding compound having a package structure 106 extending over the antenna 110. Graph 2300 includes a curve 2301 showing a simulated reflection coefficient parameter |S11| of an antenna without epoxy molding compound encapsulation, which has a -10 dB bandwidth BW1 at a resonant frequency λ1, and a curve 2302 showing a simulated reflection coefficient parameter |S11| of an antenna with epoxy molding compound encapsulation, wherein the epoxy molding compound encapsulation has a thickness T of approximately 100 μm, and the curve has a bandwidth BW2 at a corresponding resonant frequency λ2, wherein the antenna uses an epoxy molding compound material having dielectric loss tangent parameters Dk=3.5 and Df=0.013, where the dielectric constant Dk (or relative permittivity, εr) represents the ability of a material to store electrical energy, the dielectric loss represents the energy dissipated as heat in the material when subjected to an electric field, and the loss tangent or tan δ (or dissipation factor, Df) is the ratio of the imaginary part to the real part of the dielectric constant. As an example, a suitable overmolding epoxy-based molding compound for forming the package structure is high-density polyethylene (HDPE), which has a reported relative permittivity of 2.36 and a loss tangent of 0.013 at 500 GHz. Encapsulation with epoxy molding compound to a thickness T of λ / 4 provides a significantly increased -10 dB bandwidth, with BW2 greater than BW1.

[0044] Graph 2300 also shows comparative peak gain performance, including curve 2311 showing peak gain performance of an antenna without epoxy molding compound encapsulation, and curve 2312 showing improved peak gain performance of an antenna encapsulated with epoxy molding compound having a T of approximately 100 μm. As shown in graph 2300, antenna 110 with epoxy molding compound encapsulation has higher peak gain performance at the corresponding resonant frequency (curve 2312), where the simulation results correspond to an angle φ that is not fixed at 0°.

[0045] Figure 24 A graph 2400 is shown with curves showing simulated radiation efficiency of various encapsulation materials as a function of epoxy molding compound thickness. Specifically, efficiency at 300 GHz is plotted against package thickness (μm) for various materials. The effect of package thickness on radiation efficiency for five EMC materials is shown. Example radiation efficiency curves 2401, 2402, 2403, 2404, and 2405 show improvements when the package thickness T is greater than zero, including significant improvements when the thickness T above antenna 110 is 0.125λ or greater. For example, curve 2402 corresponds to an epoxy molding compound material for package structure 106 having Dk = 3.5 and Df = 0.013. Significant improvements in radiation efficiency are observed when the molding compound thickness T is approximately 0.25λ. In other examples, significant improvements in efficiency are observed when the thickness T is λ / 4 + / - 30%, with a local maximum point observed when the molding compound thickness T is approximately λ / 4 + nλ / 2, where n is a positive integer. The simulated radiation efficiency of antenna 110 exhibits local maxima at approximately λ / 4 and at further thickness increments of λ / 2 (e.g., λ / 4+nλ / 2), which can benefit the radiation efficiency of electronic device 100, wherein the efficiency gain may be slightly reduced for larger values ​​of n due to the dielectric tangent loss characteristics of the epoxy molding compound of package structure 106. When the thickness of the encapsulation of package structure 106 above patch antenna 110 is ~λ / 4 in the EMC material corresponding to curve 2402, the illustrated example provides an approximately 18.4% improvement in radiation efficiency (e.g., from 60.8% without epoxy encapsulation to 79.2% efficiency with a 140 μm thick overmolded epoxy encapsulation). In practice, due to the interaction between the dielectric material of first dielectric layer 121 of multi-level package substrate 102 and the epoxy molding compound of package structure 106, the actual maximum efficiency peak may differ slightly from the expected encapsulation thickness optimization points of λ / 4 and λ / 4+λ / 2. Similar beneficial results are expected for different designed operating frequencies and associated wavelengths λ. In the simulation example, the -10 dB|S11| bandwidth of the 300-GHz patch antenna 110 is enclosed by the wavelength corresponding to Figure 24The peak gain of the sample is increased by about 2.5 GHz from 5.85 GHz to 8.55 GHz when the sample is molded into a 100 μm (-λ / 4) thick epoxy molding compound. In addition, the peak gain of the sample with this example overmold increases across the entire operating band.

[0046] Modifications to the described examples are possible and other implementations are possible within the scope of the claims.

Claims

1. An electronic device comprising: A multi-level package substrate comprising a first level, a second level, and a third level, wherein the first level, the second level, and the third level each comprise a respective dielectric layer and a patterned conductive feature, the first level, the second level, and the third level extending in respective first, second, and third planes in a first direction and a second direction orthogonal thereto, the second level being between the first level and the third level along a third direction orthogonal to the first and second directions, the first level comprising a first trace layer comprising an antenna and a first via layer comprising a portion of a ground wall spaced laterally outward from and surrounding the antenna, and the second level comprising a second trace layer comprising a ground plane connected to the ground wall; a semiconductor die attached to the first level of the multi-level package substrate; as well as A packaging structure includes a molding compound enclosing the semiconductor die and extending on one side of the antenna. 2 . The electronic device of claim 1 , wherein the first trace layer includes a second portion of the ground wall that is laterally spaced apart from the antenna in the first plane and surrounds the antenna.

3. The electronic device of claim 1, wherein the multi-level packaging substrate includes metal posts on a first trace level for antennas and ground wall connectors. 4 . The electronic device of claim 1 , wherein the multi-level packaging substrate includes conductive leads in the third level.

5. The electronic device according to claim 1, wherein: The semiconductor die is configured to cause the antenna to operate at a wavelength λ; and The molding compound has a thickness of 0.125λ or greater along the third direction over the antenna. The electronic device according to claim 5 , wherein the thickness of the molding compound is approximately 0.25λ. 7 . The electronic device according to claim 5 , wherein the thickness of the molding compound is approximately λ / 4+nλ / 2, where n is a positive integer. The electronic device according to claim 5 , wherein the thickness of the molding compound is λ / 4+ / −30%. 9 . The electronic device according to claim 1 , wherein the molding compound has a loss tangent value less than 0.

02. 10 . The electronic device according to claim 9 , wherein the loss tangent value of the molding compound is approximately greater than or equal to 0.001 and approximately less than or equal to 0.

01.

11. A system comprising: circuit boards; as well as An electronic device comprising: a multi-level packaging substrate having a first level, a second level, and a third level, the first level, the second level, and the third level each comprising a respective dielectric layer and a respective patterned conductive feature, the first level, the second level, and the third level extending in respective first, second, and third planes in a first direction and a second direction orthogonal thereto, the second level being between the first level and the third level along a third direction orthogonal to the first and second directions, the first level comprising a first trace layer comprising an antenna and a first via layer comprising a portion of a ground wall spaced laterally outward from and surrounding the antenna, the second level comprising a second trace layer comprising a ground plane connected to the ground wall, and the multi-level packaging substrate having conductive leads coupled to the circuit board; a semiconductor die attached to the first level of the multi-level package substrate; and A packaging structure includes a molding compound enclosing the semiconductor die and extending on one side of the antenna.

12. The system of claim 11, wherein the first trace layer includes a second portion of the ground wall that is laterally spaced from the antenna in the first plane and surrounds the antenna.

13. The system of claim 11, wherein: The semiconductor die is configured to cause the antenna to operate at a wavelength λ; and The molding compound has a thickness of 0.125λ or greater along the third direction over the antenna.

14. The system of claim 11, wherein the molding compound has a loss tangent value less than 0.

02.

15. A method of manufacturing an electronic device, the method comprising: Manufacturing a multi-level package substrate, comprising forming a first level, a second level, and a third level, the first level, the second level, and the third level each comprising a respective dielectric layer and a respective patterned conductive feature, the second level being between the first level and the third level, the first level comprising a first trace layer comprising an antenna and a first via layer comprising a portion of a ground wall spaced laterally outward from and surrounding the antenna, and the second level comprising a second trace layer comprising a ground plane connected to the ground wall; flip-chip attaching a semiconductor die to the first level of the multi-level package substrate; as well as A package structure is formed that includes a molding compound enclosing the die and extending over one side of the antenna.

16. The method of claim 15, wherein the first trace layer includes a second portion of the ground wall laterally spaced from and surrounding the antenna.

17. The method of claim 15, wherein: The semiconductor die is configured to cause the antenna to operate at a wavelength λ; and The molding compound has a thickness of 0.125λ or greater over the antenna.

18. The method of claim 17, wherein the thickness of the molding compound is approximately 0.25λ.

19. The method of claim 17, wherein the thickness of the molding compound is approximately λ / 4+nλ / 2, where n is a positive integer.

20. The method of claim 15, wherein the molding compound has a loss tangent value of less than 0.02.

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