Method for manufacturing thin film transistor, sputtering target, and sintered body

Abstract

The purpose of the present invention is to provide a method for manufacturing a thin film transistor capable of improving operational stability. A method for manufacturing a thin film transistor according to one embodiment of the present invention is a method for manufacturing a thin film transistor having at least an oxide semiconductor layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, comprising the following steps: a step of forming the oxide semiconductor layer containing In, Zn and Al as metal elements on the substrate; and a step in which the protective layer containing SiN is formed on the oxide semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a thin film transistor, a sputtering target and a sintered body. Background Art

[0002] Thin-film transistors (TFTs) are becoming increasingly popular as active components used in flat-panel displays such as organic EL (Organic Electro-Luminescence) displays. Known thin-film transistors include top-gate (staggered) and bottom-gate (inversely staggered) transistors.

[0003] Such thin-film transistors are required to have stable operation. A thin-film transistor with improved operational stability by increasing carrier mobility and light stress resistance is known (Japanese Patent Application Laid-Open No. 2020-194945).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-194945 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] The thin film transistor of Patent Document 1 has improved operational stability by having an oxide semiconductor layer containing In, Zn and Fe. SiN is mostly used for the protective layer of the thin film transistor. The protective layer containing SiN has a high hydrogen content, and there is a situation where hydrogen is separated from the protective layer and diffused due to the thermal history during the manufacturing process. When this hydrogen penetrates into the oxide semiconductor layer of the thin film transistor, there is a situation where the Vth shift and other characteristics of the thin film transistor are deteriorated. This deterioration of characteristics has a great impact on thin film transistors with an oxide semiconductor layer with high carrier mobility, and there is a tendency for the operation to become unstable. It is required to reduce the influence of hydrogen and improve the operational stability of thin film transistors with oxide semiconductor layers.

[0009] The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a thin film transistor capable of improving operation stability, and a sputtering target for forming an oxide semiconductor layer and an oxide gas barrier layer of a thin film transistor with high operation stability.

[0010] Means used to solve problems

[0011] A method for manufacturing a thin film transistor according to one embodiment of the present invention is a method for manufacturing a thin film transistor having at least an oxide semiconductor layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, the method comprising: a step of forming the oxide semiconductor layer containing In, Zn, and Al as metal elements on the substrate; and a step of forming the protective layer containing SiN on the oxide semiconductor layer.

[0012] Another embodiment of the present invention provides a method for manufacturing a thin film transistor, which is a method for manufacturing a thin film transistor having at least an oxide semiconductor layer, an oxide gas barrier layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, and includes: a step of forming the oxide semiconductor layer on the substrate; a step of forming the oxide gas barrier layer containing In, Zn, and Al as metal elements on the oxide semiconductor layer; and a step of forming the protective layer containing SiN on the oxide gas barrier layer.

[0013] Another embodiment of the sputtering target of the present invention is a sputtering target for forming at least one of an oxide semiconductor layer and an oxide gas barrier layer used in a thin film transistor, wherein the sputtering target contains In, Zn and Al as metal elements, and the contents of the In, Zn and Al relative to the total of all metal elements contained are: In: 40 atomic % or more and 75 atomic % or less, Zn: 15 atomic % or more and 45 atomic % or less, and Al: 0.5 atomic % or more and 20 atomic % or less.

[0014] Effects of the Invention

[0015] A method for manufacturing a thin film transistor according to one embodiment of the present invention can improve the operational stability of the thin film transistor. A sputtering target according to another embodiment of the present invention can form an oxide semiconductor layer and an oxide gas barrier layer of a thin film transistor with high operational stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic cross-sectional view showing a top-gate thin film transistor according to one embodiment of the present invention.

[0017] Figure 2 Is to express Figure 1 Schematic cross-sectional views of different top-gate thin-film transistors.

[0018] Figure 3 Is to express Figure 1 and Figure 2 Schematic cross-sectional views of different top-gate thin-film transistors.

[0019] Figure 4This is a graph showing the measurement results of the Id-Vg characteristics of the thin-film transistor of Sample 15 having a channel length of 10 μm and including an oxide semiconductor layer containing In and Zn.

[0020] Figure 5 This is a graph showing the measurement results of the Id-Vg characteristics of the thin-film transistor of Sample 16 having a channel length of 10 μm and including an oxide semiconductor layer containing In, Zn, and Al.

[0021] Figure 6 The graph shows the comparison results of the light stress tolerance obtained by the negative gate bias and light irradiation (Negative Bias Temperature Illumination Stress: NBTIS) test, in which the Id-Vg characteristics of the thin film transistor of Sample 15 having a channel length of 10 μm and an oxide semiconductor layer containing In and Zn were measured.

[0022] Figure 7 This graph shows comparison results of light stress tolerance obtained by measuring Id-Vg characteristics of a thin film transistor of Sample 16 having a channel length of 10 μm and an oxide semiconductor layer containing In, Zn, and Al, through an NBTIS test.

[0023] Figure 8 This is a graph showing measurement results of Id-Vg characteristics of thin film transistors with different channel lengths of oxide semiconductor layers containing In and Zn.

[0024] Figure 9 This is a graph showing measurement results of Id-Vg characteristics of thin film transistors with different channel lengths of oxide semiconductor layers containing In, Zn, and Al.

[0025] Figure 10 This is a graph showing the measurement results of the Id-Vg characteristics of the thin-film transistor of Sample 27 having a channel length of 10 μm and including an oxide semiconductor layer containing In, Zn, and Al.

[0026] Figure 11 This is a graph showing measurement results of Id-Vg characteristics of thin film transistors with different channel lengths of oxide semiconductor layers containing In, Zn, and Al. DETAILED DESCRIPTION

[0027] [Description of Embodiments of the Invention]

[0028] First, embodiments of the present invention will be described.

[0029] As described above, hydrogen (H2) that escapes from the protective layer containing SiN and diffuses into the oxide semiconductor layer, or this hydrogen, in the form of water (H2O), infiltrates into the oxide semiconductor layer, potentially deteriorating characteristics such as the Vth shift of the thin-film transistor. The present inventors have conducted extensive research and have discovered that by including indium (In), zinc (Zn), and aluminum (Al) in the oxide semiconductor layer, it is possible to suppress the infiltration of H2 and H2O into the layer, or by providing an oxide gas barrier layer containing In, Zn, and Al in the thin-film transistor, it is possible to suppress the infiltration of H2 and H2O into the oxide semiconductor layer. Furthermore, it has been discovered that Al can suppress the detachment of Zn, which can be released from the layer due to aging, for example.

[0030] (1) A method for manufacturing a thin film transistor according to one embodiment of the present invention is a method for manufacturing a thin film transistor having at least an oxide semiconductor layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, the method comprising: forming the oxide semiconductor layer containing In, Zn, and Al as metal elements on the substrate; and forming the protective layer containing SiN on the oxide semiconductor layer.

[0031] In the method for manufacturing a thin film transistor, since an oxide semiconductor layer containing In, Zn, and Al is formed on a substrate, the infiltration of diffused H2 and H2O into the oxide semiconductor layer can be suppressed, thereby improving the operational stability of the obtained thin film transistor.

[0032] (2) Another embodiment of the present invention is a method for manufacturing a thin film transistor, which is a method for manufacturing a thin film transistor having at least an oxide semiconductor layer, an oxide gas barrier layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, and which comprises: a step of forming the oxide semiconductor layer on the substrate; a step of forming the oxide gas barrier layer containing In, Zn, and Al as metal elements on the oxide semiconductor layer; and a step of forming the protective layer containing SiN on the oxide gas barrier layer.

[0033] The method for manufacturing the thin film transistor can suppress the infiltration of diffused H2 and H2O into the oxide semiconductor layer because an oxide gas barrier layer containing In, Zn, and Al is formed on the oxide semiconductor layer, thereby improving the operational stability of the obtained thin film transistor.

[0034] (3) In (2), the oxide semiconductor layer may contain In, Zn, and Al as metal elements. This can further suppress the diffusion of H 2 and H 2 O into the oxide semiconductor layer.

[0035] (4) In (1), (2), and (3), the total content of the metal elements is: In: 40 atomic % or more and 75 atomic % or less, Zn: 15 atomic % or more and 45 atomic % or less, and Al: 0.5 atomic % or more and 20 atomic % or less. Thus, by keeping the contents of the metal elements In, Zn, and Al within the above ranges, the infiltration of H2 and H2O into the oxide semiconductor layer can be effectively suppressed, and the carrier mobility or threshold voltage of the thin film transistor can be optimized.

[0036] (5) In (1), (2), and (3), the oxide semiconductor layer and the oxide gas barrier layer may be amorphous layers. This can enhance the effect of suppressing the diffusion of H2 and H2O.

[0037] (6) In (1) to (5) above, the oxide semiconductor layer and the oxide gas barrier layer may be formed as a barrier layer against at least one of H 2 and H 2 O. That is, the oxide semiconductor layer itself may be formed as a layer that also serves as a gas barrier layer that suppresses the infiltration of at least one of H 2 and H 2 O.

[0038] (7) In (1) to (6) above, the Al in the oxide semiconductor layer and the oxide gas barrier layer suppresses the release of Zn. That is, the Al may be contained as a metal element that suppresses the release of Zn.

[0039] Another embodiment of the sputtering target of the present invention is a sputtering target for forming at least one of an oxide semiconductor layer and an oxide gas barrier layer used in a thin film transistor, wherein the sputtering target contains In, Zn and Al as metal elements, and the contents of the In, Zn and Al relative to the total of all metal elements contained are: In: 40 atomic % or more and 75 atomic % or less, Zn: 15 atomic % or more and 45 atomic % or less, and Al: 0.5 atomic % or more and 20 atomic % or less.

[0040] This sputtering target can form an oxide semiconductor layer and an oxide gas barrier layer capable of suppressing diffusion of H 2 and H 2 O into the oxide semiconductor layer.

[0041] A sintered body according to another embodiment of the present invention is a sintered body for forming the above-mentioned sputtering target.

[0042] That is, the sputtering target may be formed of a sintered body.

[0043] [Details of the embodiments of the present invention]

[0044] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings as appropriate. Furthermore, regarding the numerical values ​​described in this specification, only one of the upper and lower limits may be used, or any combination of the upper and lower limits may be used. In this specification, all numerical ranges from the upper and lower limits that can be combined are described as preferred ranges.

[0045] [First embodiment]

[0046] exist Figure 1 , a top-gate thin-film transistor 10 (hereinafter, simply referred to as "thin-film transistor 10") is shown as an example of a thin-film transistor obtained by the thin-film transistor manufacturing method (hereinafter, simply referred to as "the manufacturing method"). Thin-film transistor 10 includes an oxide semiconductor layer 12, a protective layer 13, a gate insulating layer 14, a gate electrode 15, a source electrode 16, and a drain electrode 17 on a plate 11. Figure 1 The protective layer 13 of the thin-film transistor 10 includes a first protective layer 131 composed of silicon oxide (SiOx) and a second protective layer 132 composed of silicon nitride (SiN) stacked on the first protective layer 131. The gate insulating layer 14 and the gate electrode 15 are disposed within the protective layer 13 (first protective layer 131). The gate insulating layer 14 is stacked on the oxide semiconductor layer 12, and the gate electrode 15 is stacked on the gate insulating layer 14. The source electrode 16 and the drain electrode 17 are disposed so that portions of them are in contact with the conductive S / D regions of the oxide semiconductor layer 12. The region of the oxide semiconductor layer 12 where the gate insulating layer 14 is stacked serves as a non-conductive channel region.

[0047] The thin film transistor 10 can be obtained by the following manufacturing method, which includes: forming an oxide semiconductor layer 12 containing In, Zn, and Al as metal elements on a substrate 11; and forming a protective layer 13 containing SiN on the oxide semiconductor layer 12. Between these two steps, the manufacturing method includes: forming a gate insulating layer 14 on the oxide semiconductor layer 12; and forming a gate electrode 15 on the gate insulating layer 14. Furthermore, the manufacturing method includes forming a source electrode 16 and a drain electrode 17 after the step of forming the protective layer 13.

[0048] [Step of forming an oxide semiconductor layer]

[0049] In the step of forming the oxide semiconductor layer 12 , the oxide semiconductor layer 12 containing In, Zn, and Al as metal elements is formed on the substrate 11 .

[0050] (Substrate)

[0051] The substrate 11 is not particularly limited, and examples thereof include a glass substrate and a silicon substrate. Examples of glass used in the glass substrate include alkali-free glass, high strain point glass, and soda-lime glass. Alternatively, a metal substrate such as a stainless steel sheet or a resin substrate such as a polyethylene terephthalate (PET) film may be used as the substrate 11.

[0052] From the viewpoint of processability, the average thickness of the substrate 11 is preferably 0.001 mm or more and 10 mm or less. The size and shape of the substrate 11 can be set according to the size of the display and the like.

[0053] (Oxide semiconductor layer)

[0054] The oxide semiconductor layer 12 contains In, Zn, and Al as metal elements. By including these metal elements, the oxide semiconductor layer 12 can suppress the infiltration of H₂ diffused from the second protective layer 132 (described later) containing SiN. Furthermore, the oxide semiconductor layer 12 can also suppress the infiltration of the diffused H₂ into the interior as H₂O by combining with oxygen. In other words, the oxide semiconductor layer 12 functions as a barrier layer for H₂ and H₂O gases.

[0055] <In>

[0056] In is an element that suppresses the infiltration of H2 and H2O into the oxide semiconductor layer 12 and also contributes to improving electrical conductivity. A higher In content improves the electrical conductivity of the oxide semiconductor layer 12, and also improves the carrier density and carrier mobility.

[0057] The lower limit of the In content relative to the total amount of metal elements in the oxide semiconductor layer 12 is preferably 40 atomic %. The upper limit of the content is preferably 75 atomic %, and more preferably 65 atomic %. By setting the In content within the above range, the reliability of the effect of suppressing the infiltration of H 2 and H 2 O into the oxide semiconductor layer 12 can be improved, and carrier mobility and the like can be made sufficient.

[0058] <Zn>

[0059] Zn is an element that suppresses the penetration of H 2 and H 2 O into the oxide semiconductor layer 12 and also affects the processing characteristics of the oxide semiconductor layer 12 .

[0060] The lower limit of the Zn content relative to the total amount of metal elements in the oxide semiconductor layer 12 is preferably 15 atomic%, more preferably 25 atomic%. The upper limit of the Zn content is preferably 45 atomic%, more preferably 35 atomic%. By setting the Zn content within the above range, the reliability of the effect of suppressing the infiltration of H2 and H2O into the oxide semiconductor layer 12 can be improved, and the processability, uniformity, etc. of the oxide semiconductor layer 12 can be easily ensured.

[0061] <Al>

[0062] Al is an element that inhibits the infiltration of H2 and H2O into the oxide semiconductor layer 12 and inhibits the release of Zn from the oxide semiconductor layer 12. Specifically, Zn can be released from the oxide semiconductor layer 12 due to aging, etc. The inclusion of Al can inhibit this Zn release. In addition, the inclusion of Al in the oxide semiconductor layer 12 can improve the light stress resistance of the thin film transistor 10.

[0063] The lower limit of the Al content relative to the total amount of metal elements in the oxide semiconductor layer 12 is preferably 0.5 atomic %, more preferably 1.5 atomic %. The upper limit of the content is preferably 20 atomic %, more preferably 10 atomic %. By setting the Al content within the above range, the reliability of the effect of suppressing the infiltration of H2 and H2O into the oxide semiconductor layer 12 can be improved, and the reliability of the effect of suppressing the desorption of Zn can be improved.

[0064] The reason why Al can suppress Zn detachment is believed to be as follows. It is known that Zn in an oxide layer detaches after H₂ or H₂O contained in the oxide layer is released. When Al is added, the oxide layer not only acquires the function of suppressing the infiltration of H₂ or H₂O into the oxide layer (a gas barrier function), but also acquires the function of suppressing the release of H₂ or H₂O from the oxide layer. Therefore, it is believed that the addition of Al to the oxide layer can suppress Zn detachment in the oxide layer.

[0065] In the oxide semiconductor layer 12, the elements other than those mentioned above are O (oxygen) and inevitable impurities. Inevitable impurities may be present due to factors such as raw materials, materials, and manufacturing equipment. Examples of such inevitable impurities include Pb, Si, Fe, Ni, Ti, Mg, Cr, and Zr. The content of inevitable impurities in the oxide semiconductor layer 12 is preferably 1% by mass or less of each element, and more preferably 500 ppm by mass or less. Furthermore, in the above structure, the content of In, Zn, and Al in the oxide semiconductor layer 12 can also be referred to as the proportion of all elements other than O.

[0066] The average thickness of the oxide semiconductor layer 12 can be determined based on the conditions that allow the drain current to be turned off when used as a switching element. The lower limit of the average thickness of the oxide semiconductor layer 12 is preferably 10 nm, and more preferably 15 nm. On the other hand, the upper limit of the average thickness is preferably 60 nm, and more preferably 50 nm. In this specification, the term "average thickness" refers to the average value of the thicknesses at any five points.

[0067] The oxide semiconductor layer 12 is preferably an amorphous layer. Alternatively, it is preferably at least partially formed as an amorphous layer. In other words, the oxide forming the oxide semiconductor layer 12 is preferably amorphous, or at least partially amorphous. Even when the oxide semiconductor layer 12 has such a structure, carrier mobility can be substantially improved compared to conventional amorphous silicon. Furthermore, such a structure can easily and reliably increase the optical band gap.

[0068] Generally speaking, the higher the density of the oxide layer, the higher the gas barrier function. Compared with the case where the oxide layer is composed of a polycrystalline material with a large number of grain boundaries, the oxide layer can improve its density by being composed of an amorphous material. In oxide has a gas barrier function, but there is a tendency to crystallize the oxide layer. On the other hand, by adding Zn, the amorphization of the oxide layer can be promoted. Al partially becomes Al oxide by reacting with H2O, and there is a tendency to partially crystallize it, but as Al, it can promote the amorphization of the oxide layer. Therefore, it is believed that the oxide layer promotes amorphization by containing In, Zn and Al, and can play a better gas barrier function against H2 or H2O.

[0069] The oxide semiconductor layer 12 can be formed into an amorphous layer by controlling the gas pressure to be within a range of 1 mTorr to 5 mTorr, for example, and performing surface treatment with plasma or reducing gas after film formation.

[0070] The upper limit of the sheet resistance of the oxide semiconductor layer 12 (sheet resistance of the S / D regions after surface treatment) is preferably 1.0 kΩ / □, and more preferably 0.5 kΩ / □. When the sheet resistance of the oxide semiconductor layer 12 after surface treatment is below this upper limit, the S / D regions can be easily and reliably made conductive. The sheet resistance can be measured using a four-probe resistance meter.

[0071] The oxide semiconductor layer 12 is formed by sputtering using a sputtering target. After the oxide semiconductor layer 12 is formed, it is patterned by photolithography or the like. Immediately after the patterning, a heat treatment (pre-annealing treatment) is preferably performed to improve the film quality.

[0072] Sputtering Target

[0073] The oxide semiconductor layer 12 can be formed using a sputtering target containing In, Zn, and Al as metal elements, wherein the contents of In, Zn, and Al relative to the total of all metal elements contained are: In: 40 atomic % to 75 atomic %, Zn: 15 atomic % to 45 atomic %, and Al: 0.5 atomic % to 20 atomic %. Elements other than those mentioned above in the sputtering target are unavoidable impurities. The contents of each element in the sputtering target can be set to the same ranges as those described for the oxide semiconductor layer 12.

[0074] The sputtering target material formed into the above-mentioned sputtering target can be used to form the oxide semiconductor layer 12 and can also be used to form the oxide gas barrier layer described later. The sputtering target material contains the same metal element as the above-mentioned sputtering target and its content is also substantially the same, so it can have a gas barrier function against H2 and H2O.

[0075] Sintered Body

[0076] The sputtering target is formed of a sintered body.

[0077] [Step of forming a gate insulating layer]

[0078] In the step of forming the gate insulating layer 14, the gate insulating layer 14 is formed on the oxide semiconductor layer 12. The gate insulating layer 14 is formed on the oxide semiconductor layer 12 after the pre-annealing process.

[0079] Examples of the gate insulating layer 14 include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a metal oxide layer such as Al2O3 or Y2O3. The gate insulating layer 14 can be formed using a CVD method or a PECVD method. The gate insulating layer 14 can be a single layer or a multilayer structure of two or more layers. When the gate insulating layer 14 is a multilayer structure of two or more layers, the first layer and the second and subsequent layers preferably have different compositions.

[0080] The lower limit of the average thickness of the gate insulating layer 14 is preferably 50 nm, and more preferably 100 nm. On the other hand, the upper limit of the average thickness of the gate insulating layer 14 is preferably 300 nm, and more preferably 250 nm. If the average thickness does not meet the lower limit, the withstand voltage of the gate insulating layer 14 may become insufficient. On the contrary, if the average thickness exceeds the upper limit, the capacity of the capacitor formed between the gate electrode 15 and the oxide semiconductor layer 12 is insufficient, and the drain current may become insufficient. In addition, in the case where the gate insulating layer 14 is multi-layered, the so-called "average thickness of the gate insulating layer" refers to the average thickness of the gate insulating layer as a whole.

[0081] [Step of forming a gate electrode]

[0082] In the process of forming the gate electrode 15, the gate electrode 15 is formed on the gate insulating layer 14. After the gate electrode 15 is formed, the gate insulating layer 14 and the gate electrode 15 are patterned by photolithography or the like.

[0083] (Gate electrode)

[0084] The gate electrode 15 is conductive. The gate electrode 15 is formed, for example, by forming the gate insulating layer 14 and then subjecting the oxide semiconductor layer 12 to a heat treatment (annealing). The gate electrode 15 is not particularly limited, and alloys of metals with low resistivity, such as Al and Cu, or high-melting-point metals with high heat resistance, such as Mo, Cr, and Ti, can be used.

[0085] The lower limit of the average thickness of the gate electrode 15 is preferably 50 nm, and more preferably 80 nm. By setting the average thickness to be greater than the lower limit, an increase in the resistance of the gate electrode 15 can be suppressed, and an increase in power consumption in the gate electrode 15 can be suppressed. On the other hand, from the perspective of processability, the upper limit of the average thickness of the gate electrode 15 is preferably 500 nm, and more preferably 400 nm.

[0086] [Protective layer formation process]

[0087] In the step of forming the protective layer 13, the protective layer 13 composed of SiN is formed on the oxide semiconductor layer 12. This step in the present embodiment includes: forming a first protective layer 131 composed of SiOx on the oxide semiconductor layer 12 so as to cover the gate insulating layer 14 and the gate electrode 15; and forming a second protective layer 132 composed of SiN on the first protective layer 131.

[0088] The first protective layer 131 is formed after patterning the gate insulating layer 14 and the gate electrode 15 and performing surface treatment on the oxide semiconductor layer 12. The surface treatment of the oxide semiconductor layer 12 is performed to make the S / D regions conductive, and can be performed, for example, by ion implantation, element diffusion, reduction using a reducing gas, plasma treatment, or the like.

[0089] The first protective layer 131 and the second protective layer 132 can be formed by CVD or PECVD. After the film formation, contact holes for arranging the source electrode 16 and the drain electrode 17 are formed by photolithography or the like.

[0090] The first protective layer 131 includes SiOx, and the second protective layer 132 includes SiN. That is, the first protective layer 131 is a silicon oxide layer, and the second protective layer 132 is a silicon nitride layer.

[0091] By providing the protective layer 13, the influence of the external environment on the oxide semiconductor layer 12 or the gate electrode 15 can be reduced. The second protective layer 132 comprising SiN is suitable for reducing the influence of H2O and the like. On the other hand, since the second protective layer 132 comprising SiN contains a large amount of H2, the H2 is sometimes released due to the thermal history during the manufacturing process. If the released H2 penetrates into the oxide semiconductor layer 12, the electrical characteristics of the thin film transistor 10 may be reduced. Since the first protective layer 131 comprising SiOx can suppress the infiltration of H2, it is configured between the oxide semiconductor layer 12 and the second protective layer 132, and thus the H2 released from the second protective layer 132 can be suppressed from directly penetrating into the oxide semiconductor layer 12. Since the thin film transistor 10 also includes an oxide semiconductor layer 12 having a gas barrier function, the infiltration of H2 into the oxide semiconductor layer 12 can be further suppressed.

[0092] [Electrode Formation Process]

[0093] In the electrode formation step, the source electrode 16 and the drain electrode 17 are formed. Specifically, the source electrode 16 and the drain electrode 17 are formed in the contact hole so that a portion thereof contacts the S / D region of the oxide semiconductor layer 12. After being formed, the source electrode 16 and the drain electrode 17 are patterned by photolithography or the like.

[0094] The source electrode 16 and the drain electrode 17 are conductive and are not particularly limited to metals with low resistivity such as Al and Cu, high melting point metals with high heat resistance such as Mo, Cr, and Ti, or alloys thereof.

[0095] The source electrode 16 and the drain electrode 17 cover a portion of the protective layer 13 and fill the contact hole. In this way, the source electrode 16 and the drain electrode 17 are electrically connected to the oxide semiconductor layer 12 at both ends of the channel region of the thin film transistor 10.

[0096] The lower limit of the average thickness of the source electrode 16 and the drain electrode 17 is preferably 100 nm, more preferably 150 nm. By setting the average thickness to be greater than this lower limit, an increase in the resistance of the source electrode 16 and the drain electrode 17 can be suppressed, and an increase in power consumption can be suppressed. The upper limit of the average thickness of the source electrode 16 and the drain electrode 17 is preferably greater than the combined thickness of the gate insulating layer 14 and the gate electrode 15, and is preferably 1000 μm, more preferably 800 μm, for example.

[0097] Advantages

[0098] The manufacturing method includes the following steps: forming an oxide semiconductor layer 12 containing In, Zn, and Al as metal elements on a substrate 11; and forming a protective layer 13 containing SiN on the oxide semiconductor layer 12. This method prevents H2, which diffuses from the protective layer 13 due to thermal history during the manufacturing process, from penetrating into the oxide semiconductor layer 12. As a result, the resulting thin film transistor 10 has high carrier mobility and excellent operational stability.

[0099] The sputtering target is suitable for manufacturing the oxide semiconductor layer 12 .

[0100] [Second embodiment]

[0101] Hereinafter, another embodiment of the method for manufacturing the thin film transistor will be described. Components identical to those in the first embodiment are denoted by the same reference numerals and their description will be omitted.

[0102] Figure 2 FIG2 shows a top-gate thin-film transistor 20 (hereinafter referred to as "thin-film transistor 20") obtained by the thin-film transistor manufacturing method (hereinafter referred to as "the manufacturing method"). Thin-film transistor 20 comprises an oxide semiconductor layer 22, an oxide gas barrier layer 27, a protective layer 13, a gate insulating layer 14, a gate electrode 15, a source electrode 16, and a drain electrode 17 on a substrate 11. Protective layer 13 includes a first protective layer 131 composed of SiOx and a second protective layer 132 composed of SiN stacked on the first protective layer 131.

[0103] The thin film transistor 20 includes the following steps: forming an oxide semiconductor layer 22 on a substrate 11; forming an oxide gas barrier layer 27 containing In, Zn, and Al as metal elements on the oxide semiconductor layer 22; and forming a protective layer 13 containing SiN on the oxide gas barrier layer 27. Between the steps of forming the oxide semiconductor layer and the oxide gas barrier layer, the manufacturing method includes the following steps: forming a gate insulating layer 14 on the oxide semiconductor layer 22; and forming a gate electrode 15 on the gate insulating layer 14. Furthermore, after forming the protective layer 13, the manufacturing method includes forming a source electrode 16 and a drain electrode 17.

[0104] [Step of forming an oxide semiconductor layer]

[0105] In the step of forming the oxide semiconductor layer, the oxide semiconductor layer 22 is formed on the substrate 11. The metal element contained in the oxide semiconductor layer 22 is not particularly limited, and the oxide semiconductor layer 22 may not contain any or all of In, Zn, and Al.

[0106] Next, the gate insulating layer 14 and the gate electrode 15 are formed on the oxide semiconductor layer 22 .

[0107] [Step of forming an oxide gas barrier layer]

[0108] In the step of forming the oxide gas barrier layer, the oxide gas barrier layer 27 containing In, Zn, and Al as metal elements is formed on the oxide semiconductor layer 22. Specifically, the oxide gas barrier layer 27 is formed to cover the gate insulating layer 14 and the gate electrode 15 formed on the oxide semiconductor layer 22.

[0109] The oxide gas barrier layer 27 contains In, Zn, and Al as metal elements. The respective contents of In, Zn, and Al relative to the total of these metal elements can be the same as those of the oxide semiconductor layer 12 described in the first embodiment. The oxide gas barrier layer 27 is preferably an amorphous layer. Alternatively, at least a portion thereof is preferably formed as an amorphous layer. The oxide gas barrier layer 27 functions as a barrier layer for H2 and H2O gases. The Al inhibits the Zn from escaping from the oxide gas barrier layer 27.

[0110] [Protective layer formation process]

[0111] In the step of forming the protective layer 13, the protective layer 13 composed of SiN is formed on the oxide gas barrier layer 27. This step in the present embodiment includes: forming a first protective layer 131 composed of SiOx on the oxide gas barrier layer 27; and forming a second protective layer 132 composed of SiN on the first protective layer 131.

[0112] After the protective layer 13 is formed, contact holes are formed, and the source electrode 16 and the drain electrode 17 are formed in the contact holes.

[0113] Advantages

[0114] This manufacturing method includes the following steps: forming an oxide semiconductor layer 22 on a substrate 11; forming an oxide gas barrier layer 27 containing In, Zn, and Al as metal elements on the oxide semiconductor layer 22; and forming a protective layer 13 containing SiN on the oxide gas barrier layer 27. Specifically, this manufacturing method provides a thin film transistor 20 having an oxide gas barrier layer 27 containing In, Zn, and Al formed between the oxide semiconductor layer 22 and the protective layer 13 containing SiN. Consequently, H2 diffused from the protective layer 13 due to thermal history during the manufacturing process can be suppressed from penetrating into the oxide semiconductor layer 22.

[0115] [Other embodiments]

[0116] The embodiments described above do not limit the structure of the present invention. Therefore, the embodiments described above may omit, replace, or add components of each part of the embodiments described above based on the description of this specification and common technical knowledge, and all of these contents should be interpreted as falling within the scope of the present invention.

[0117] The oxide semiconductor layer of the thin film transistor having an oxide gas barrier layer (second embodiment) may contain In, Zn, and Al. Figure 3 As shown, when the oxide semiconductor layer 12 containing In, Zn, and Al is used, the oxide gas barrier layer 27 of the thin film transistor 30 may be disposed within the protective layer 13 (between the first protective layer 131 and the second protective layer 132 ).

[0118] The specific structure of the thin film transistor is not limited to Figure 1 、 Figure 2 and Figure 3 For example, the protective layer may be a protective layer containing only SiN. In addition, the thin film transistor may also be a bottom gate type.

[0119] In the thin film transistor, another layer such as a buffer layer for improving bonding or serving as a buffer material may be provided between the substrate and the oxide semiconductor layer.

[0120] Example

[0121] Hereinafter, the present invention will be described in detail based on Examples, but the present invention is not to be construed as being limited based on the description of the Examples.

[0122] Samples 1 to 14 were prepared to evaluate the gas barrier properties of oxide layers containing In, Zn, and Al against H2 and H2O. For each sample, a 150 nm thick second protective layer (containing SiN) was formed on a 525 μm thick silicon substrate. A 200 nm thick first protective layer (containing SiO) was formed on this second protective layer. An oxide layer with varying In, Zn, and Al contents was then formed on this first protective layer.

[0123] The film formation conditions and thickness (film thickness) of the oxide layer of each sample are shown below.

[0124] (1) Samples 1 to 12

[0125] Film forming method: DC (direct current) sputtering

[0126] Device: CS200 manufactured by Ulvac Co., Ltd.

[0127] Film forming temperature: room temperature

[0128] Air pressure: 1mTorr

[0129] Carrier gas: Ar

[0130] Oxygen partial pressure: 100×O2 / (Ar+O2)=4 volume%

[0131] Film forming power density: 2.55W / cm 2

[0132] Film thickness: 15nm

[0133] (2) Sample 13 and Sample 14

[0134] Film forming method: DC (direct current) sputtering

[0135] Device: CS200 manufactured by Ulvac Co., Ltd.

[0136] Film forming temperature: room temperature

[0137] Air pressure: 1mTorr

[0138] Carrier gas: Ar

[0139] Oxygen partial pressure (first partial pressure): 100×O2 / (Ar+O2)=0 volume%

[0140] Oxygen partial pressure (second partial pressure): 100×O2 / (Ar+O2)=4 volume%

[0141] Film forming power density: 2.55W / cm 2

[0142] Film thickness: 10 nm at the first partial pressure, then 15 nm at the second partial pressure (total 25 nm)

[0143] The gas barrier resistance of each sample was determined based on the amounts of H 2 and H 2 O measured by TDS (Therm Al Desorption Spectrometry) analysis.

[0144] The evaluation of gas barrier resistance by TDS analysis was performed as follows.

[0145] (1) H2:

[0146] The evaluation is graded A, B, or C based on whether the ion current [A] below is exceeded within the temperature range of 300°C to 450°C. "A" indicates good H2 gas barrier resistance, "C" indicates poor H2 gas barrier resistance, and "B" indicates an intermediate rating between A and C.

[0147] More than 1E -9 [A]:C

[0148] More than 5E -10[A]:B

[0149] 5E -10 [A] Below: A

[0150] (2) H2O:

[0151] The following relationship between the temperature range and the ion current [A] was used to determine whether the sample was rated A, B, or C. "A" indicates good H2O gas barrier resistance, "C" indicates poor H2O gas barrier resistance, and "B" indicates an intermediate rating between A and C.

[0152] More than 1E -9 The temperature of [A] is 300°C or higher and lower than 350°C: C

[0153] More than 1E -9 The temperature of [A] is 350°C or higher and lower than 400°C: B

[0154] More than 1E -9 The temperature of [A] is 400°C or higher and lower than 450°C: A

[0155] After TDS analysis, the resistance value of the oxide layer of each sample was measured. A resistance value of less than 100 Ωcm was designated "A," and a resistance value of 100 Ωcm or more was designated "B."

[0156] An oxide layer judged as "B" is considered difficult to use as a semiconductor layer.

[0157] The measurement was performed as follows.

[0158] (1) Determination of ion current

[0159] Analyzer: TDS1200II (manufactured by Electronic Science Co., Ltd.)

[0160] Temperature conditions: set temperature USC temperature RT-500℃ (60℃ / min)

[0161] Sample stage: Quartz stage

[0162] Quadrupole Mass Spectrometer

[0163] Ionization method: electron ionization

[0164] Measurement mode: SIM mode (selected ion monitoring mode)

[0165] (2) Resistance measurement

[0166] Analytical device: MCP-HT450 (manufactured by Nitto Seiko Analytical Technology Co., Ltd.)

[0167] Measurement method: constant voltage application, leakage current measurement method

[0168] The contents of In, Zn, and Al of each sample and the measurement results are shown in Table 1. In Table 1, the numerical values ​​are the contents of In, Zn, and Al, and "-" indicates that In, Zn, and Al are not contained.

[0169] [Table 1]

[0170]

[0171] As can be seen from Table 1, all the results of Sample 8, Sample 9, Sample 10, and Sample 14 were rated high.

[0172] Next, a thin film transistor (Sample 15) including an oxide semiconductor layer containing 65 atomic percent In, 35 atomic percent Zn, and 0 atomic percent Al was fabricated; a thin film transistor (Sample 16) including an oxide semiconductor layer containing 65 atomic percent In, 28 atomic percent Zn, and 7 atomic percent Al was fabricated; and a thin film transistor (Sample 27) including an oxide semiconductor layer containing 64 atomic percent In, 35 atomic percent Zn, and 0.7 atomic percent Al was fabricated. The Id-Vg characteristics of Samples 15, 16, and 27 were compared, and the light stress tolerance of Samples 15 and 16 was compared. The results are shown in FIG. Figures 4 to 11 .

[0173] The channel length of Samples 15, 16, and 27 was set to 10 μm, and the Id-Vg characteristics (drain current (Id) - gate voltage (Vg) characteristics) were compared. The Id-Vg characteristics were measured three times for each sample. The results of Sample 15 are shown in Figure 4 The results of sample 16 are shown in Figure 5 The results of sample 27 are shown in Figure 10 .

[0174] When the right Figure 4 、 Figure 5 and Figure 10 When compared, near Vg0[V], the slope is as follows Figure 4 (Sample 15), Figure 10 (Sample 27), Figure 5 (Sample 16) and becomes smaller (approaching parallel to the vertical axis). This suggests that the inclusion of Al and the increase in the Al content improve the transfer characteristics (Id-Vg characteristics).

[0175] Next, the light stress tolerance of Samples 15 and 16 was compared. To evaluate light stress tolerance, each sample (thin-film transistor: TFT) was subjected to a stress test (NBTIS test) in which a negative bias voltage was continuously applied to the gate electrode while irradiating the sample with light (white light) to simulate the actual environment (stress) encountered during LCD panel operation. The change in threshold voltage (Vth) before and after stress application (threshold voltage shift: ΔVth) was used as an indicator of light stress tolerance in TFT characteristics. Light stress tolerance is a key characteristic in driving LCDs.

[0176] The NBTIS test was performed under the following conditions.

[0177] Gate voltage: -20V

[0178] Source-drain voltage: 10V

[0179] Substrate temperature: 60°C

[0180] Stress application time: 2 hours

[0181] Light intensity during light stress: 25000nit

[0182] Light source for light stress: White light emitting diode (LED)

[0183] The ΔVth of sample 15 was 3.0 [V], and the ΔVth of sample 16 was 1.8 [V]. The results of the light stress resistance of sample 15 are shown in FIG. Figure 6 The results of light stress resistance of sample 16 are shown in Figure 7 When Figure 6 and Figure 7 In comparison, near Vg0 [V], Sample 15 has a larger deviation in the horizontal axis direction and a larger slope (angle) relative to the vertical axis. Sample 16 has a smaller deviation in the horizontal axis direction and a smaller slope relative to the vertical axis. This indicates that the inclusion of Al improves light stress resistance. Figure 6 and Figure 7 The numerical value on the left of ) indicates the application time of the light stress. 0 sec indicates the start of light stress application, and the measurement is performed 30 sec after application. Then, the measurement is performed 100 sec later, and further measurements are performed after 300 sec, 1000 sec, 3600 sec, and 7200 sec, respectively.

[0184] Samples with different channel lengths (length of the channel region) were produced using a thin film transistor including an oxide semiconductor layer containing 65 atomic % In, 35 atomic % Zn, and 0 atomic % Al, a thin film transistor including an oxide semiconductor layer containing 65 atomic % In, 28 atomic % Zn, and 7 atomic % Al, and a thin film transistor including an oxide semiconductor layer containing 64 atomic % In, 35 atomic % Zn, and 0.7 atomic % Al. The correlation between the channel lengths was compared. The metal elements contained and the channel lengths for each sample number are shown in Table 2. Sample 15 is the same as Sample 19 in Table 2, Sample 16 is the same as Sample 24 in Table 2, and Sample 27 is the same as Sample 30 in Table 2.

[0185] [Table 2]

[0186]

[0187] The transmission characteristics of samples 17 to 26 and samples 28 to 32 were measured and compared. The results of samples 17 to 21 are shown in FIG. Figure 8 The results of samples 22 to 26 are shown in Figure 9 The results of samples 28 to 32 are shown in Figure 11 .

[0188] When the right Figure 8 、 Figure 9 and Figure 11 In comparison, in samples with a channel length of 8 μm or more, the slope is as follows near Vg0 [V]. Figure 8 、 Figure 11 and Figure 9 The values ​​of Vd and Vg decrease in the order of Vg0 [V] (approaching parallel to the vertical axis). This suggests that the inclusion of Al and an increase in the Al content improve the transfer characteristics (Id-Vg characteristics). Furthermore, when comparing Samples 17, 22, and 28, all of which have a channel length of 5 μm, Sample 17 exhibits a large shift (deviation) in the horizontal axis near Vg0 [V], whereas Samples 22 and 28 exhibit a smaller shift. This suggests that the inclusion of Al in the oxide semiconductor layer contributes to miniaturization of thin-film transistors.

[0189] Industrial Application Possibilities

[0190] As described above, the method for manufacturing a thin-film transistor according to one embodiment of the present invention can obtain a thin-film transistor that has high operational stability and is suitable for an organic EL display or the like.

[0191] Description of Reference Signs

[0192] 10, 20, 30: Thin-film transistors

[0193] 11:Substrate

[0194] 12, 22: oxide semiconductor layer

[0195] 13: Protective layer

[0196] 131: First protective layer

[0197] 132: Second protective layer

[0198] 14: Gate insulation layer

[0199] 15: Gate electrode

[0200] 16: Source electrode

[0201] 17: Drain electrode

[0202] 27: Oxide gas barrier layer

Claims

1. A method for manufacturing a thin film transistor, characterized in that: A method for manufacturing a thin film transistor having at least an oxide semiconductor layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, comprising the following steps: forming the oxide semiconductor layer containing In, Zn, and Al as metal elements on the substrate; and forming the protective layer including SiN on the oxide semiconductor layer.

2. A method for manufacturing a thin film transistor, characterized in that: A method for manufacturing a thin film transistor having at least an oxide semiconductor layer, an oxide gas barrier layer, a protective layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode on a substrate, wherein the method comprises the following steps: forming the oxide semiconductor layer on the substrate; forming the oxide gas barrier layer containing In, Zn, and Al as metal elements on the oxide semiconductor layer; and forming the protective layer including SiN on the oxide gas barrier layer.

3. The method for manufacturing a thin film transistor according to claim 2, wherein: The oxide semiconductor layer contains In, Zn, and Al as metal elements.

4. The method for manufacturing a thin film transistor according to claim 1, claim 2 or claim 3, wherein: The content ratio relative to the total of the above metal elements is, In: 40 atomic % or more and 75 atomic % or less, Zn: 15 atomic % or more and 45 atomic % or less, and Al: 0.5 atomic % or more and 20 atomic % or less.

5. The method for manufacturing a thin film transistor according to claim 1, wherein: The oxide semiconductor layer is an amorphous layer.

6. The method for manufacturing a thin film transistor according to claim 3, wherein: At least one of the oxide semiconductor layer and the oxide gas barrier layer is an amorphous layer.

7. The method for manufacturing a thin film transistor according to claim 1 or claim 3, wherein: The oxide semiconductor layer is formed as a barrier layer for at least one of H 2 and H 2 O.

8. The method for manufacturing a thin film transistor according to claim 2 or claim 3, wherein: The oxide gas barrier layer is formed as a barrier layer for at least one of H 2 and H 2 O.

9. A sputtering target for forming at least one of an oxide semiconductor layer and an oxide gas barrier layer used in a thin film transistor, wherein: In, Zn, and Al are contained as metal elements, and the contents of the In, Zn, and Al relative to the total of all metal elements contained are, In: 40 atomic % or more and 75 atomic % or less, Zn: 15 atomic % or more and 45 atomic % or less, and Al: 0.5 atomic % or more and 20 atomic % or less. 10 . A sintered body for forming the sputtering target according to claim 9 .

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