Miniaturized monolithic integration method of geomagnetic sensor and MCU

Abstract

The application discloses a kind of geomagnetic sensor and the miniaturization monolithic integration method of MCU.The method includes the following steps: (1) low-temperature CMOS circuit layer preparation, (2) TSV three-dimensional interconnection structure processing, (3) no magnetic core planar coil production, (4) low-temperature electromagnetic shielding layer integration, (5) structure release and vacuum packaging.The application eliminates the process conflict and hysteresis error introduced by ferromagnetic material through no magnetic core design, and uses TSV (through silicon via) three-dimensional interconnection technology to replace traditional plane wiring, compresses module volume to millimeter level, integrates wideband electromagnetic shielding layer at the same time, ensures that signal-to-noise ratio is greater than or equal to 30dB in weak magnetic field (<1 μT) detection scene.The low-temperature compatibility with CMOS process can be realized, and the mass production feasibility needs to be adapted to standard semiconductor production line, the monolithic cost is reduced by more than 30%, and is suitable for navigation equipment, consumer electronics and industrial sensing system.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) and semiconductor integration technology, specifically relating to a miniaturized monolithic integration method for a geomagnetic sensor and a microcontroller unit (MCU). Background Technology

[0002] Traditional integration solutions for geomagnetic sensors and MCUs have long faced multiple challenges related to size, power consumption, and process compatibility. Existing technologies often employ discrete packaging or high-temperature processes to integrate the sensor and circuitry, resulting in large sensor modules (typically exceeding 5×5mm). 2 This makes it difficult to meet the compact space requirements of wearable devices, micro navigation modules, and other similar applications. Furthermore, high-temperature processing steps (such as annealing temperatures exceeding 600°C) can easily damage the metal interconnect layers (such as aluminum or copper) in CMOS circuits, resulting in low yields (typically below 80%) and high costs.

[0003] Meanwhile, the integrated signal crosstalk problem is particularly prominent. The design of geomagnetic sensors, which rely on ferromagnetic materials (such as NiFe alloys), further limits the miniaturization potential. Furthermore, MCU circuit noise is coupled to the sensor through a shared substrate, resulting in a signal-to-noise ratio (SNR) of less than 10dB in weak magnetic field (<1μT) detection scenarios, severely restricting detection accuracy. Although some solutions attempt to optimize size through multi-chip packaging (SiP) or planar stacking, their process complexity and cost increase significantly, making it difficult to meet the combined demands of miniaturization, low power consumption, and high reliability for consumer electronics and industrial IoT.

[0004] The first paper (Design and Measurement of Microelectromechanical Three-AxisMagnetic Field Sensors Based on the CMOS Technique, doi:10.3390 / mi14051038.) designs a three-axis magnetic field sensor with a magnetotransistor structure using TSMC's 0.18μm CMOS process. The CMOS front-end temperature is approximately 350-400℃. This design uses magnetotransistors but does not employ TSV three-dimensional interconnects, resulting in a 2D interconnect structure. It lacks vacuum packaging and a magnetic shielding layer design; it does not address hysteresis error and anti-interference issues; and it does not integrate MCU functionality. The second paper (Design, Fabrication, Characterization and Reliability Study of CMOS-MEMS Lorentz-Force Magnetometers, doi:10.48550 / arXiv.2109.10980.) fabricates a Lorentz force magnetometer based on CMOS technology, but it is only a single-layer coil design; it lacks TSV interconnects, making vertical high-density integration impossible; it does not introduce a magnetic shielding layer or a structure release packaging design; and it does not provide a clearly defined single-chip solution compatible with MCUs. The literature (S. Tumanski, Thin Film Magnetoresistive Sensors. Bristol, UK: IOP Publishing, 2007.) uses ferromagnetic materials such as NiFe to construct AMR / GMR magnetoresistive sensors, which are heavily dependent on ferromagnetic materials and suffer from hysteresis and temperature drift problems; the discrete packaging structure has low integration density; there is no packaging optimization and three-dimensional interconnection, so it cannot be used in weak magnetic field scenarios; and it is incompatible with standard CMOS logic circuits.

[0005] To address the aforementioned issues, there is an urgent need for a low-temperature compatible, highly integrated, and interference-resistant geomagnetic sensor and MCU monolithic integration solution to overcome the dependence of traditional technologies on ferromagnetic materials and the limitations of high-temperature processes. Summary of the Invention

[0006] To address the problems of large size, high power consumption, process incompatibility, and severe hysteresis errors in traditional geomagnetic sensor and MCU integration solutions, this invention proposes a miniaturized monolithic integration method for geomagnetic sensors and MCUs. This invention is the first to systematically differentiate a three-stage temperature control strategy in the integration of a magnetic sensor and an MCU on a single chip, ensuring low-temperature compatibility throughout the entire process and avoiding electromigration and thermal failure of metal interconnects. This invention employs a multi-layer coreless spiral coil structure, TSV three-dimensional interconnection, and a low-temperature magnetic shielding composite layer.

[0007] The method of this invention employs a coreless design and vertical three-dimensional interconnect technology, breaking through the size limitations of traditional discrete packaging and ultimately achieving a millimeter-level size (2.5×2.5×0.4mm). 3 A single-chip magnetic sensor module with low power consumption (≤295μW), high signal-to-noise ratio (≥30dB) and yield of >95% significantly improves the detection accuracy of weak magnetic fields and the efficiency of integrated manufacturing.

[0008] The present invention adopts the following technical solution:

[0009] A method for miniaturized monolithic integration of a geomagnetic sensor and an MCU includes the following steps:

[0010] (a) An MCU circuit layer is formed on a silicon substrate using CMOS-MEMS technology, the MCU circuit layer comprising a signal amplification module, a digital processing unit and a communication interface;

[0011] (b) Fabricate a coreless planar coil of the Lorentz force geomagnetic sensor on the MCU circuit layer and vertically interconnect it with the MCU circuit layer through a vertical via TSV.

[0012] (c) Deposit a tantalum nitride (TaN) composite electromagnetic shielding layer between the MCU circuit layer and the planar coil;

[0013] (d) The suspended support structure of the planar coil is released through an etching process. Subsequent structure release and packaging processes utilize non-magnetic vacuum packaging materials. The packaging process employs a bonding temperature of 250-300℃ and a vacuum degree of <10. - 3Pa.

[0014] Further, the vertical through-hole TSV in step (b) has a diameter of 3-5 μm and a depth-to-width ratio of 8:1-12:1.

[0015] Furthermore, the maximum temperature of the front-end process of the CMOS-MEMS process is controlled at 350-400℃, the metal interconnect layer is a copper double damask structure, and the process yield is >95%.

[0016] Furthermore, the planar coil has a multi-layer stacked structure with a linewidth ≤ 2 μm, an interlayer spacing ≥ 3 times the linewidth, a total thickness of 0.4-0.5 mm, and a chip area of ​​2.5 × 2.5-3 × 3 mm. 2 .

[0017] Furthermore, the diameter of the TSV via is 3-5 μm, the filling material is copper or polycrystalline silicon, and the sidewall of the via is covered with a titanium nitride (TiN) diffusion barrier layer.

[0018] Furthermore, the TSV via resistance is 40-50mΩ, the parasitic capacitance is ≤0.1pF, and the signal transmission delay is <10ps.

[0019] Furthermore, the electromagnetic shielding layer is a composite material of tantalum nitride (TaN) and Fe3O4 nanoparticles, with a thickness of 100-500 nm, a Fe3O4 doping ratio of 1-5 wt%, and a noise attenuation capability of ≥25 dB.

[0020] Furthermore, the magnetic permeability of the non-magnetic vacuum packaging material described in step (d) is ≥95%.

[0021] As a preferred embodiment of the present invention, the present invention provides a method for miniaturized monolithic integration of a geomagnetic sensor and an MCU, the method comprising the following steps:

[0022] (1) Fabrication of low-temperature CMOS circuit layers

[0023] The MCU circuit layer was fabricated on a silicon substrate using a 180nm CMOS process, with the highest front-end process temperature strictly controlled between 350℃ and 400℃. PMOS / NMOS transistors were formed by ion implantation and photolithography, with a gate oxide layer thickness of 3.2nm. The metal interconnect adopted a double damask copper interconnect structure, and the dielectric layer was deposited using PECVD with SiO2 deposition at a temperature controlled between 200-300℃, resulting in a dielectric layer thickness of 0.5μm. Finally, a 0.5μm thick silicon nitride (SiN) passivation layer was deposited as a protective layer.

[0024] This low-temperature process enables copper interconnect resistivity ≤2.2μΩ·cm, yield >95%, and integrates a low-noise amplifier (noise figure <1dB) with a 24-bit ADC to support weak signal processing.

[0025] (2) Fabrication of TSV three-dimensional interconnection structure

[0026] A 1.2 μm thick SiO2 insulating layer was deposited on the surface of the MCU circuit layer using PECVD at a controlled temperature of 200-300℃. TSV vias (3-5 μm in diameter, aspect ratio 8:1-10:1) were etched using Bosch process. A 5 nm thick TiN diffusion barrier layer was deposited on the inner wall of the vias using ALD, followed by copper plating and chemical mechanical polishing (CMP) to achieve a surface roughness ≤5 nm.

[0027] TSV via resistance is 40-50mΩ, parasitic capacitance is reduced to 0.1pF (compared to 0.5pF for traditional planar wiring), and signal transmission delay is shortened to less than 10ps.

[0028] (3) Fabrication of a coreless planar coil

[0029] High-density planar coils were fabricated using a quasi-heterogeneous integration multilayer stacking process, with a linewidth ≤2μm and a spacing ≥6μm. After sputtering a Ti / Cu seed layer, a spiral coil pattern was defined by deep ultraviolet (DUV) lithography, copper was electroplated to a thickness of 2μm, and a 0.5μm thick SiO2 insulating layer was deposited between the layers by PECVD. After stacking 30 layers, the total thickness was controlled at 0.4-0.5mm.

[0030] The Z-axis coil is directly connected to the MCU analog front end via TSV, with an inductance value of 25-35μH (compared to 50μH for traditional magnetic core solutions), resulting in an 80% reduction in size. It supports triaxial magnetic field detection (X / Y / Z) with sensitivity deviation of <5% for each axis.

[0031] The specific process flow of the quasi-heterogeneous integration multilayer stacking process described in step (3) is as follows:

[0032] First, a Ti / 300nm Cu seed layer with a thickness of 20nm is deposited on the CMOS circuit layer with the completed TSV interconnect structure using magnetron sputtering. Then, a spiral coil pattern is defined using deep ultraviolet (DUV) lithography (exposure wavelength 193nm, resolution <0.5μm), and copper is electroplated in an electrolytic cell to a single layer thickness of about 2μm to form a single-layer wire structure.

[0033] To achieve interlayer insulation, after each conductor structure is completed, a 500 nm thick SiO2 layer is deposited at 200–250 °C using PECVD to ensure dielectric strength and low parasitic capacitance. Chemical mechanical polishing (CMP) is then performed to ensure interlayer flatness, resulting in a surface roughness Ra < 5 nm. This process is repeated for 30 layers, with the total thickness controlled at 0.4–0.5 mm.

[0034] To ensure the continuity of the vertical interconnect path, the Z-axis coil layers are connected vertically through a local TSV structure, and the wafer-level structure release process (HF vapor phase etching) is used to reduce the accumulation of mechanical stress while maintaining structural stability.

[0035] (4) Low-temperature electromagnetic shielding layer integration

[0036] A TaN-Fe3O4 composite shielding layer with a thickness of 100-500 nm and a Fe3O4 doping ratio of 1-5 wt% is magnetron sputtered between the MCU circuit layer and the planar coil (temperature 250℃-300℃). This composite film effectively shields against electromagnetic interference generated by the CMOS circuit. The patterning process employs reactive ion etching (RIE) using a Cl2 / BCl3 gas combination, covering the MCU digital circuit area. This shielding layer exhibits noise attenuation ≥25 dB in the 1-10 MHz frequency band, and the baseline noise of the geomagnetic sensor is ≤0.05 nT / √Hz.

[0037] (5) Structure release and vacuum packaging

[0038] The sacrificial layer beneath the coil was removed using HF vapor phase etching (etching rate 1 μm / min), resulting in a 1 μm suspension height after release and a mechanical resonant frequency ≥10 kHz. Vacuum encapsulation was achieved via glass-silicon anode bonding (250-300℃, 5 kN pressure), achieving a vacuum level <10. - 3Pa, magnetic permeability ≥95%, total chip thickness 0.4mm-0.5mm.

[0039] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0040] (1) This invention completely eliminates traditional ferromagnetic materials such as NiFe in the sensor's sensitive structure through a coreless design, and instead uses a high-density planar multilayer spiral coil to construct a triaxial sensing unit, avoiding magnetic hysteresis error and damage to CMOS circuits caused by high-temperature magnetic annealing process, thereby achieving improved stability of magnetoelectric properties and low-temperature compatibility throughout the process.

[0041] (2) This invention is the first to vertically interconnect the coil structure and MCU logic circuit within the same wafer using TSV (Through Silicon Via) technology. Through-holes with diameters of 3-5 μm and aspect ratios of 8:1-12:1 are used to achieve short-circuit signal paths, effectively compressing the module size to the millimeter level ([2.5×2.5, 3×3] mm). 2 ×[0.4,0.5]mm), and far surpasses traditional planar interconnect methods in terms of integration density and interconnection efficiency. This integration method is an important technical means of this invention, which significantly reduces volume and improves interconnection quality while ensuring triaxial magnetic response function.

[0042] (3) To address the coupling interference problem between the MCU digital circuit and the analog magnetic induction unit in single-chip integration, this invention introduces a tantalum nitride (TaN) composite shielding layer doped with Fe3O4 nanoparticles between them. This shielding layer is optimized within the parameter space of thickness (100-500nm) and doping ratio (1-5wt%), exhibiting good magnetic field transparency and high-frequency noise attenuation performance. In actual testing, the noise suppression capability in the 1-10MHz frequency band reaches more than 25dB, thereby improving the overall system signal-to-noise ratio to ≥30dB in weak magnetic field (<1μT) detection scenarios. This shielding method is structurally layered and embedded with the sensitive area, and functionally balances signal fidelity and interference suppression, representing a unique composite shielding implementation path of this invention.

[0043] (4) This invention constructs a full-process low-temperature process system, controlling the temperature of key processes to ≤400℃ (as shown in Table 1 below). The CMOS front-end process temperature is in the range of 350-400℃. The aim is to ensure transistor performance and dielectric quality while avoiding thermal damage to copper interconnects, dielectric layers, and subsequent MEMS structures caused by high-temperature annealing. This replaces traditional high-temperature processes (>600℃), thus ensuring compatibility with subsequent low-temperature integration processes and improving overall yield and packaging reliability. PECVD deposition and packaging bonding are both limited to the range of 250-300℃, effectively avoiding thermal damage to the copper interconnect structure, dielectric layer, and suspended structure caused by high-temperature processing, achieving a process yield of >95%. Simultaneously, the packaging stage uses a vacuum degree <10... - The non-magnetic glass-silicon anode bonding encapsulation method with 3Pa and magnetic permeability ≥95% ensures stable operation of the magnetically sensitive structure and further improves product reliability.

[0044] Table 1

[0045]

[0046] In summary, this invention systematically solves the problems of traditional magnetic sensor integration schemes that cannot balance size, accuracy, power consumption and manufacturing adaptability through the integrated and synergistic innovation of a coreless sensing structure, TSV three-dimensional interconnection, nanocomposite shielding layer and low-temperature full-process technology. It forms a single-chip integration method with structural originality, parameter controllability and process transformation feasibility. Attached Figure Description

[0047] Figure 1 This is a flowchart illustrating the manufacturing process of the miniaturized monolithic integration method of the geomagnetic sensor and MCU of the present invention.

[0048] Figure 2 This is a schematic diagram of the cross-sectional structure of an integrated wafer, where 1-borosilicate glass cover, 2-vacuum layer, 3-electromagnetic shielding layer, 4-insulating layer, 5-TSV interconnect structure, 6-coreless planar coil, 7-SiO2 dielectric layer, 8-copper interconnect layer, 9-transistor region, and 10-silicon substrate. Detailed Implementation

[0049] To better illustrate the technical solutions and advantages of the present invention, the present invention will be further explained and described below in conjunction with specific embodiments. The described embodiments are some, but not all, of the embodiments of the present invention.

[0050] Figure 1The manufacturing process flow diagram of the miniaturized monolithic integration method of the geomagnetic sensor and MCU of the present invention includes five steps: (1) low-temperature CMOS circuit layer preparation, (2) TSV three-dimensional interconnect structure processing, (3) coreless planar coil fabrication, (4) low-temperature electromagnetic shielding layer integration, and (5) structure release and vacuum packaging.

[0051] Figure 2 This is a schematic diagram of the cross-sectional structure of an integrated wafer, which includes the following parts:

[0052] 1) Borosilicate glass cover: Located on the top layer of the device, it is used as the upper packaging material for anodic bonding. It has high magnetic permeability (≥95%) and excellent sealing performance, ensuring the stability and long-term airtightness of the packaging cavity.

[0053] 2) Vacuum layer: Formed between the cover plate and the functional layer of the device, it provides a working environment for the suspended structure, with the vacuum level controlled at <10. - 3Pa effectively improves the mechanical Q value and vibration resistance of the coil, and reduces the influence of air damping.

[0054] 3) Electromagnetic shielding layer: deposited at the interface between the induction structure and the CMOS circuit. The shielding layer is a tantalum nitride (TaN) composite material doped with Fe3O4 nanoparticles, with a thickness ranging from 100 to 500 nm and a doping ratio of 1 to 5 wt%. It is used to suppress electromagnetic interference from digital circuits to the magnetic induction structure and improve the signal-to-noise ratio under weak magnetic fields.

[0055] 4) Insulating layer: It acts as a buffer and interface transition between the shielding layer and other layers, and can be made of silicon nitride or SiO2 material.

[0056] 5) TSV Interconnect Structure: A vertical silicon via structure connecting the coreless planar coil to the MCU analog front end below. The via diameter is 3-5μm, the aspect ratio is 8:1-12:1, the filling material is copper or polycrystalline silicon, and the sidewall is covered with a titanium nitride (TiN) diffusion barrier layer to achieve low resistance and high density interconnection. The resistance is controlled at 40-50mΩ, and the parasitic capacitance is ≤0.1pF. Figure 2 The diagram shows the TSV interconnect structure, which is actually an array-style distribution.

[0057] 6) Coreless planar coil: This is the key induction structure of the present invention. It adopts multi-layer spiral stacked wiring with a line width ≤2μm. The layers are isolated by SiO2 dielectric material. The number of stacked layers is 30, and the total thickness is about 0.4-0.5mm, forming a triaxial magnetic field detection structure (X / Y / Z axis). It is coupled to the analog circuit through TSV.

[0058] 7) SiO2 dielectric layer: As a dielectric layer between stacked coils and between the coils and the underlying circuit structure, it is deposited using PECVD and has a thickness of about 0.5 μm to ensure electrical insulation performance and low dielectric loss.

[0059] 8) Copper interconnect layer: It is a multi-layer metal wiring layer that uses a double damask structure to achieve high-density signal interconnection. The metal used is copper, and the dielectric layer is SiO2 deposited by PECVD. The maximum temperature does not exceed 400℃.

[0060] 9) Transistor region: Located above the silicon substrate, it is the area for the core logic units, analog amplifiers, ADCs and communication circuits of the MCU built according to the 180nm CMOS process, and has low noise and low power consumption characteristics.

[0061] 10) Silicon substrate: Provides the mechanical support base for the entire chip and forms the lower boundary of the package cavity through anodic bonding with the glass cover.

[0062] Example 1: Fabrication and Integration Verification of Miniaturized Geomagnetic Sensing Chip

[0063] On an 8-inch SOI silicon wafer, the following process operations are performed:

[0064] 1. Fabrication of CMOS circuit layers

[0065] Using a 180nm low-temperature CMOS process, the MCU logic unit, ADC module, and communication interface are integrated within a front-end process temperature range of 350-400℃. The fabricated circuit chip area is approximately 2.5×2.5mm. 2 .

[0066] 2. Fabrication of TSV 3D Interconnects

[0067] A TSV with a diameter of 5μm and an aspect ratio of 10:1 was prepared by deep silicon etching and copper plating to achieve low-resistance interconnection between a planar coil and an MCU. Test results show that the average resistance of the TSV is 46.3mΩ with a standard deviation of <3%.

[0068] 3. Integration of coreless planar coils

[0069] A triaxial spiral coil was fabricated using a multi-layer stacking method, with a single layer thickness of 2 μm, a total of 30 layers, and a total height of approximately 0.45 mm. A TSV was used to achieve a short-path connection with the MCU analog front end. The coil inductance was measured as follows: X-axis 28.4 μH, Y-axis 29.7 μH, and Z-axis 30.1 μH, with an inter-axis deviation of <5%.

[0070] 4. Electromagnetic shielding layer integration

[0071] A 300 nm thick TaN-Fe3O4 composite material with a 3% Fe3O4 doping ratio was deposited above the MCU circuit layer, with a shielding layer coverage area of ​​1.8 × 1.8 mm. 2 After shielding, the noise coupling of the digital circuit area to the magnetic sensor is reduced by 25-30 dB.

[0072] 5. Structure release and encapsulation

[0073] The sacrificial layer was released using HF vapor phase etching to form a 1μm thick suspended structure. The chip was then packaged using anodic bonding at 300℃ through a borosilicate glass cover, resulting in a final module size of 2.9×2.9×0.48mm. 3 .

[0074] Example 2: Verification of Enhanced Packaging Reliability for Larger Area Packages

[0075] 1. Fabrication of CMOS circuit layers

[0076] The MCU core circuit was fabricated and passivated using a 180nm CMOS process at 370℃. The integrated circuit module includes a signal amplifier, ADC, and digital communication interface. The chip area was increased to 3.0×3.0mm. 2 To accommodate larger electromagnetic shielding structures.

[0077] 2. TSV three-dimensional interconnection structure processing

[0078] TSV vias were fabricated on the surface of the MCU circuit layer. The via structure had a diameter of 4 μm and a depth-to-width ratio of 12:1. The vias were filled with copper and the sidewalls were covered with a titanium nitride (TiN) diffusion barrier layer. After chemical mechanical polishing (CMP), an average interconnect resistance of 43.8 mΩ was obtained.

[0079] 3. Integration of coreless planar coils

[0080] A triaxial spiral coil is formed by stacking 28 layers using a single-layer thickness of 2μm, a linewidth of ≤2μm, and a line spacing of 7μm, with the total thickness controlled at 0.44mm. The measured inductance values ​​for each axis are: X-axis 27.1μH, Y-axis 28.6μH, and Z-axis 30.0μH, with the inter-axis deviation controlled within ±5%.

[0081] 4. Electromagnetic shielding layer integration

[0082] A 400 nm thick TaN composite shielding layer with 4% Fe3O4 doping was deposited between the sensing structure and the MCU circuit, and the MCU digital area was covered by patterned etching. The measured shielding gain was approximately 28 dB, demonstrating excellent performance in the mid-to-low frequency range.

[0083] 5. Structure release and encapsulation

[0084] HF vapor phase etching was used to release the sacrificial layer, forming a 1μm high suspended structure. Encapsulation was performed using anodized bonding at 280℃ with a vacuum level <5×10⁻⁶. -4 Pa, using a borosilicate glass cover. The final module thickness is 0.49 mm, and the packaging reliability was verified through 1500 thermal cycle tests.

[0085] Example 3: Verification of the low-power optimized version

[0086] On an 8-inch SOI silicon wafer, the following process operations are performed:

[0087] 1. Fabrication of CMOS circuit layers

[0088] The MCU core circuit and ADC module were optimized under low-temperature process conditions of 350℃, with particular attention paid to transistor parameter adjustments for the standby current path to achieve low power consumption. The chip area is 2.7×2.7mm. 2 The overall power consumption is controlled to not exceed 295μW in low load mode.

[0089] 2. TSV three-dimensional interconnection structure processing

[0090] The TSV via design has a diameter of 3μm, an aspect ratio of 9:1, and is filled with copper. A TiN diffusion barrier layer is formed on the sidewall. The interconnect resistance after CMP is 48.9mΩ, maintaining interconnect integrity and conductivity.

[0091] 3. Integration of coreless planar coils

[0092] A coil structure with a linewidth of 1.8μm and a pitch of ≥6μm is used, stacked in 30 layers, with a total thickness of approximately 0.43mm. The measured triaxial inductance values ​​are: X-axis 26.0μH, Y-axis 27.4μH, and Z-axis 28.9μH, meeting the requirements for high-sensitivity magnetic field sensing.

[0093] 4. Electromagnetic shielding layer integration

[0094] The shielding layer material is a 200nm thick TaN-based composite layer with 2% Fe3O4 doping. This shielding layer focuses on optimizing the noise attenuation performance in the mid-frequency band (2-6MHz), with a suppression capability of over 25dB.

[0095] 5. Structure release and encapsulation

[0096] The sacrificial layer beneath the release coil is etched using HF vapor phase etching to create a 1μm suspension height. The packaging process employs anodic bonding at 250℃ with a vacuum level <10. - 3Pa. The final module thickness was controlled at 0.45mm, and power consumption was reduced by more than 22% compared to traditional solutions.

[0097] The structural and performance indicators of the above embodiments 1-3 and the traditional integrated solution are compared in Table 2 below. The power consumption and enclosure performance indicators of the above embodiments 1-3 and the traditional integrated solution are compared in Table 3 below.

[0098] As shown in Table 2, the embodiments of the present invention are significantly superior to traditional integrated solutions in terms of structural size, inductance characteristics, noise shielding capability, and interconnection performance. Traditional solutions typically have chip areas larger than 5.0 × 5.0 mm. 2 Furthermore, the chip size in all embodiments of the present invention is compressed to 3.0 × 3.0 mm. 2 The volume reduction reaches 67%-75%, making it more suitable for micro-embedded systems. Meanwhile, traditional packages are generally over 1.2mm thick, while this invention achieves an overall thickness of 0.45-0.49mm through structural stacking optimization and floating release, a thickness reduction of over 60%. Regarding inductance performance, Examples 1-3 maintain deviation control within ±5% under a triaxial structure, and the inductance density per unit volume is superior to traditional magnetic core solutions. Especially in noise suppression, traditional solutions, lacking an effective shielding structure, have noise shielding capabilities below 10dB, while this invention, by introducing a Fe3O4-TaN composite shielding layer, improves noise attenuation to 25-30dB, significantly improving the accuracy of geomagnetic signal detection. Furthermore, TSV interconnect technology achieves low impedance (<50mΩ) and low parasitic capacitance (<0.1pF) performance in all three examples, greatly optimizing the signal transmission path and crosstalk immunity, supporting high-speed, high-precision system operation.

[0099] As shown in Table 3, this invention also excels in power consumption control and packaging reliability. Traditional solutions typically consume over 850μW per chip, making it difficult to meet the low-power requirements of wearable devices and other similar applications. However, this invention, through low-temperature CMOS technology and low-bias amplification structure optimization, controls power consumption within the range of 295-410μW. The lowest power consumption version (Example 3) represents a reduction of over 65% compared to traditional solutions, significantly extending system battery life. Regarding packaging, traditional methods only achieve a vacuum level of 10... - At the 2Pa level, it is difficult to maintain magnetic induction stability for a long time. However, this invention uses anodic bonding to form a vacuum cavity, increasing the vacuum level to <10. - 3Pa or even <5×10 -4 Pa significantly improves the purity of the magnetic environment. The packaging temperature is reduced from the traditional ≥350℃ to 250-300℃, effectively preventing high-temperature damage to the circuit structure; the packaging yield is stably improved to over 95%, far superior to the traditional ≤80%. In terms of manufacturing costs, this invention, through process integration and area reduction, lowers the cost per chip to $0.68-0.72, a 30-40% reduction compared to traditional solutions, laying the foundation for large-scale industrial application.

[0100] Table 2 Comparison of Structural and Electrical Performance Indicators

[0101]

[0102] Table 3 Comparison of Power Consumption and Enclosure Performance Indicators

[0103]

[0104]

Claims

1. A method for miniaturized monolithic integration of a geomagnetic sensor and an MCU, characterized in that: Includes the following steps: (a) An MCU circuit layer is formed on a silicon substrate using CMOS-MEMS technology, the MCU circuit layer comprising a signal amplification module, a digital processing unit and a communication interface; (b) Fabricate a coreless planar coil of the Lorentz force geomagnetic sensor on the MCU circuit layer and vertically interconnect it with the MCU circuit layer through a vertical via TSV. (c) Deposit a tantalum nitride (TaN) composite electromagnetic shielding layer between the MCU circuit layer and the planar coil; (d) The suspended support structure of the planar coil is released through an etching process. Subsequent structure release and packaging processes utilize non-magnetic vacuum packaging materials. The packaging process employs a bonding temperature of 250-300℃ and a vacuum degree of <10. - 3Pa.

2. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The vertical through-hole TSV in step (b) has a diameter of 3-5 μm and a depth-to-width ratio of 8:1-12:

1.

3. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The maximum temperature of the front-end process of the CMOS-MEMS process is controlled at 350-400℃, and the metal interconnect layer is a copper double damask structure.

4. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The planar coil has a multi-layer stacked structure with a linewidth ≤ 2μm, an interlayer spacing ≥ 3 times the linewidth, a total thickness of 0.4-0.5mm, and a chip area of ​​2.5×2.5-3×3mm. 2 .

5. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The diameter of the TSV vias is 3-5 μm, and the filling material is copper or polycrystalline silicon. The sidewalls of the vias are covered with a titanium nitride (TiN) diffusion barrier layer.

6. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The resistance of the TSV via is 40-50mΩ, the parasitic capacitance is ≤0.1pF, and the signal transmission delay is <10ps.

7. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The tantalum nitride (TaN) composite electromagnetic shielding layer is a composite material of tantalum nitride (TaN) and Fe3O4 nanoparticles.

8. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 7, characterized in that: The thickness of the tantalum nitride (TaN) composite electromagnetic shielding layer is 100-500 nm, the Fe3O4 doping ratio is 1-5 wt%, and the noise attenuation capability is ≥25 dB.

9. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to claim 1, characterized in that: The non-magnetic vacuum packaging material described in step (d) has a magnetic permeability of ≥95%.

10. The method for miniaturized monolithic integration of a geomagnetic sensor and an MCU according to any one of claims 1-9, characterized in that: The geomagnetic sensor has good magnetic field transparency and high-frequency noise attenuation performance. Its noise suppression capability is above 25dB in the 1-10MHz frequency band, and the overall system signal-to-noise ratio is improved to ≥30dB in the weak magnetic field <1μT detection scenario.

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