Heterogeneous integrated structure and preparation method thereof

Abstract

The invention discloses a heterogeneous integrated structure and a preparation method thereof, and the structure comprises a substrate which is provided with a first surface and a second surface which are arranged oppositely, and the first surface comprises a first region and a second region which are arranged at an interval; the dielectric layer is formed on the first surface of the first region; the photonic crystal layer is formed on the first surface of the second area and the dielectric layer and comprises a plurality of photonic crystal units which are periodically arranged; the nucleation layer comprises a plurality of nucleation units located on the surfaces of the photonic crystal units; the epitaxial layer is stacked on the nucleation layer and covers the first surface. The photonic crystal layer has a special optical function in a near-infrared band and a longer wavelength, the nanoscale periodic structure can also be used for relaxation of thermal mismatch between the substrate and the epitaxial layer, and the mechanical deformation of the substrate after epitaxial growth is reduced. According to the invention, the size of the compound composite wafer can be expanded to more than 8 inches by using the large-size silicon substrate.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor process technology, and in particular relates to a heterogeneous integrated structure and a preparation method thereof. Background Art

[0002] III-V compound semiconductors are the foundation of many photonic and optoelectronic applications. For example, GaAs, the most intensively studied material, has been fabricated into lasers and radio frequency devices due to its direct bandgap and high mobility, finding widespread application in high-speed, high-power optical networking and communications.

[0003] The high density of dislocations caused by the lattice mismatch between the Si substrate and the epitaxial layer often negatively impacts the optical and electrical properties of the epitaxial layer. The difference in thermal expansion coefficients between the Si substrate and the epitaxial layer (GaAs / Si ≈ 123%) can also lead to wafer bowing and cracking in the epitaxial layer. Despite decades of research, heterogeneous monolithic integration of compound semiconductors and Si remains challenging. Furthermore, photonic and optoelectronic applications require the manipulation of photons, which are far more difficult to manipulate than electrons due to their weak interaction with matter.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a heterogeneous integrated structure and a preparation method thereof. Summary of the Invention

[0005] The object of the present invention is to provide a heterogeneous integrated structure and a preparation method thereof, which can utilize a large-size silicon substrate to expand the size of a compound composite wafer to more than 8 inches.

[0006] In order to achieve the above object, a specific embodiment of the present invention provides the following technical solutions:

[0007] A heterogeneous integrated structure comprising:

[0008] a substrate having a first surface and a second surface disposed opposite to each other, wherein the first surface includes a first region and a second region disposed at intervals;

[0009] a dielectric layer formed on the first surface of the first region;

[0010] a photonic crystal layer, formed on the first surface of the second region and the dielectric layer, comprising a plurality of periodically spaced photonic crystal units;

[0011] a nucleation layer comprising a plurality of nucleation units located on the surface of the photonic crystal unit;

[0012] An epitaxial layer is stacked on the nucleation layer and covers the first surface.

[0013] In one or more embodiments of the present application, the photonic crystal layer has a third surface opposite to the first surface, the photonic crystal units extend downward from the third surface, the thickness of the photonic crystal units above the first surface of the first region is less than or equal to the distance between the third surface and the surface of the dielectric layer, and the thickness of the photonic crystal units above the first surface of the second region is less than or equal to the distance between the third surface and the first surface.

[0014] In one or more embodiments of the present application, the nucleation layer includes a plurality of periodically arranged nucleation units, the arrangement period of the nucleation units is the same as the arrangement period of the photonic crystal units, and the duty cycle of the nucleation layer is the same as the duty cycle of the photonic crystal layer.

[0015] In one or more embodiments of the present application, the arrangement period of the photonic crystal units is 200 nm to 5 μm, and the duty cycle of the photonic crystal layer is 0.1 to 0.9.

[0016] In one or more embodiments of the present application, the substrate is a single crystal silicon substrate or a single crystal-buried oxygen layer composite silicon substrate.

[0017] In one or more embodiments of the present application, the width of the first surface of the second region in the second direction is less than or equal to 1000 nm, and the width of the first surface of the first region in the second direction is 1 μm to 50 μm, wherein the second direction is a <100> crystal direction or a <110> crystal direction perpendicular to the

[001] crystal direction.

[0018] In one or more embodiments of the present application, the dielectric layer includes one of silicon oxide, aluminum oxide, gallium oxide, silicon nitride, and aluminum nitride.

[0019] In one or more embodiments of the present application, the thickness of the dielectric layer is 20 nm to 1000 nm.

[0020] In one or more embodiments of the present application, the crystal structure of the photonic crystal layer is a cubic crystal system diamond structure or a zinc blende structure.

[0021] In one or more embodiments of the present application, the room temperature lattice parameter of the photonic crystal layer ranges from 5.4 Å to 5.7 Å, and the doping concentration of the photonic crystal layer is less than 1E18 cm -3 .

[0022] In one or more embodiments of the present application, the thickness of the photonic crystal units is 10 nm to 10 μm, and / or the roughness of the side surface of the photonic crystal units is less than or equal to 10 nm.

[0023] In one or more embodiments of the present invention, the photonic crystal unit is a single-layer structure or a multi-layer structure; and / or the nucleation layer is a single-layer structure or a multi-layer structure, and the material of the epitaxial layer is the same as the material of the top layer of the nucleation layer.

[0024] In one or more embodiments of the present invention, the crystal structure of the nucleation layer is a sphalerite structure, and the thickness of the nucleation layer is 10 nm to 300 nm.

[0025] In one or more embodiments of the present invention, the doping type of the photonic crystal layer, nucleation layer and epitaxial layer is the same as the doping type of the substrate; and / or the crystal structure of the epitaxial layer is a zinc blende structure, and the thickness of the epitaxial layer is 100 nm ~ 1000 nm.

[0026] Another specific embodiment of the present invention provides a method for preparing a heterogeneous integrated structure, comprising:

[0027] Providing a substrate, the substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals;

[0028] forming a dielectric layer on the first surface, wherein the dielectric layer covers the first area and the second area;

[0029] removing the dielectric layer on the first surface of the second region to expose the second region;

[0030] forming a buffer layer on the dielectric layer and the second region;

[0031] forming a nucleation layer on the buffer layer, and using the nucleation layer as a mask to remove a portion of the buffer layer to form a photonic crystal layer;

[0032] An epitaxial layer is formed on the nucleation layer, wherein the epitaxial layer covers the first surface.

[0033] In one or more embodiments of the present invention, forming a nucleation layer above the buffer layer, and using the nucleation layer as a mask to remove a portion of the buffer layer to form a photonic crystal layer includes:

[0034] forming a nucleation layer on the buffer layer, wherein the nucleation layer covers the buffer layer;

[0035] removing a portion of the nucleation layer and exposing a portion of the buffer layer to form a plurality of periodically arranged nucleation units;

[0036] The periodically arranged nucleation units are used as a mask to remove a portion of the buffer layer to form a photonic crystal layer.

[0037] In one or more embodiments of the present invention, forming a buffer layer on the dielectric layer and the second region includes:

[0038] A single or multiple buffer layer is epitaxially grown on the dielectric layer and the second region by physical or chemical vapor deposition, wherein the ratio of the growth rate of the buffer layer along the first direction to the growth rate along the second direction is greater than or equal to 1.5, wherein the first direction is a

[001] crystal direction and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

[0039] In one or more embodiments of the present invention, after forming a buffer layer on the dielectric layer and the second region, the surface of the buffer layer is polished until the root mean square roughness of the surface of the buffer layer is less than or equal to 1 nm.

[0040] In one or more embodiments of the present invention, the nucleation layer is used as a mask and an etching process is adopted to remove part of the buffer layer to form a photonic crystal layer, wherein the etching selectivity ratio of the nucleation layer to the buffer layer is greater than or equal to 10; and / or the resonant wavelength of the photonic crystal layer is greater than or equal to 800 nm.

[0041] In one or more embodiments of the present invention, forming an epitaxial layer above the nucleation layer, wherein the epitaxial layer covers the first surface, includes:

[0042] An epitaxial layer is epitaxially grown on the surface of the nucleation layer by a physical or chemical vapor deposition method, wherein the doping type of the epitaxial layer is consistent with the doping type of the substrate, and the ratio of the growth rate of the epitaxial layer along the first direction to the growth rate along the second direction is greater than or equal to 2, wherein the first direction is a

[001] crystal direction and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

[0043] Compared to existing technologies, the heterogeneous integrated structure and its fabrication method of the present invention utilizes epitaxial lateral growth of a buffer layer on a substrate, a nucleation layer grown on the planarized buffer layer, and a photonic crystal layer formed using the nucleation layer as a mask. The resulting microcrystal array then grows laterally, paving and merging to form an epitaxial layer suspended above the photonic crystal structure. This heterogeneous integrated structure can utilize large-scale silicon substrates, expanding the size of compound wafers to over 8 inches.

[0044] The suspended epitaxial layer in the present invention can be used to grow higher quality and more complex compound semiconductor films on large-scale silicon substrates. The photonic crystal layer below the epitaxial layer has special optical functions in the near-infrared band and at longer wavelengths, such as high reflection, low reflection, wavelength selection and optical waveguide. The nanoscale periodic structure can also be used to relax the thermal mismatch between the substrate and the epitaxial layer, reducing the mechanical deformation of the substrate after epitaxial growth. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic structural diagram of a heterogeneous integrated structure according to one embodiment of the present invention;

[0047] Figure 2 A schematic structural diagram of a heterogeneous integrated structure in another embodiment of the present invention;

[0048] Figure 3 A schematic structural diagram of a heterogeneous integrated structure in yet another embodiment of the present invention;

[0049] Figure 4 A flow chart of a method for preparing a heterogeneous integrated structure according to an embodiment of the present invention;

[0050] Figures 5a-5f Schematic diagram of structural changes in a method for preparing a heterogeneous integrated structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0052] As mentioned in the background, to combine the optoelectronic properties of III-V compound semiconductors with silicon-based microelectronics technology to realize monolithic integration, it is necessary to directly epitaxially grow compound semiconductor single crystal materials such as GaAs on the

[001] crystal direction of the Si substrate. The high-density dislocations generated by the lattice mismatch between the Si substrate and the epitaxial layer will usually have a negative impact on the optical and electrical properties of the epitaxial layer. In addition, the difference in the coefficient of thermal expansion between the Si substrate and the epitaxial layer, GaAs / Si≈123%, will also cause the epitaxial layer to exhibit wafer warping and cracking. Despite decades of research, the hetero-monolithic integration of compound semiconductors with Si remains challenging.

[0053] On the other hand, photonic and optoelectronic applications require the manipulation of photons, which are much more difficult to manipulate than electrons due to their weak interaction with matter. Photonic crystals are a method of manipulating light using the spatial periodic distribution of materials, and by adjusting the photonic crystal structure, the dispersion relationship of light and the conduction or radiation modes can be artificially customized. The period of the photonic crystal is in the range of the wavelength of the photon, and the lattice constant of the photonic crystal structure in the near-infrared and visible light bands is usually on the order of hundreds of nanometers. Silicon and germanium material systems compatible with silicon-based CMOS are more suitable for the fabrication of high-precision and high-aspect-ratio nanostructures.

[0054] In order to facilitate the understanding of the technical solutions of the present application, the technical terms that may appear in the present application will be explained in detail below.

[0055] III-V compound: a binary or multi-component compound semiconductor material composed of elements from group III (group 13) and group V (group 15) of the periodic table. Common III-V compounds are composed of Al, Ga, In and N, P, As, Sb (e.g. GaAs, InP, AlN, InGaAs, AlGaAsSb, etc.).

[0056] <100> crystal direction: a family of crystal directions in the diamond and zinc blende structure where the nearest neighbor atomic spacing is equal to the lattice constant, including

[100] crystal direction,

[010] crystal direction,

[001] crystal direction, [-100] crystal direction, [0-10] crystal direction, [00-1] crystal direction;

[0057] <110> crystal direction: a family of crystal directions in the diamond and zinc blende structure where the nearest neighbor atomic spacing is equal to / 2 times the lattice constant, including

[110] crystal direction, [-1-10] crystal direction,

[101] crystal direction, [-10-1] crystal direction,

[011] crystal direction, [0-1-1] crystal direction, [1-10] crystal direction, [-110] crystal direction, [10-1] crystal direction, [-101] crystal direction, [01-1] crystal direction, [0-11] crystal direction.

[0058] Referring toFigure 1 As shown, a heterogeneous integrated structure in the present invention includes:

[0059] The substrate 10 has a first surface and a second surface disposed opposite to each other, and the first surface includes a first region and a second region spaced apart. The first region and the second region are spaced apart in sequence along a second direction. The first direction is a longitudinal

[001] crystal direction (i.e., the first direction is perpendicular to the first surface), and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> The crystal direction, ie, the second direction, is parallel to the first surface and perpendicular to the first direction.

[0060] It can be understood that the first region and the second region can constitute the entire first surface of the substrate 10, or can constitute part of the first surface of the substrate 10, that is, the first surface of the substrate 10 can also include other regions, such as the third region or the fourth region, and this application does not limit this.

[0061] a dielectric layer 21 formed on the first surface of the first region;

[0062] The photonic crystal layer 40 is formed on the first surface of the second region b and the dielectric layer 21 and includes a plurality of periodically spaced photonic crystal units 41;

[0063] The nucleation layer 50 includes a plurality of nucleation units 51 located on the surface of the photonic crystal unit 41;

[0064] The epitaxial layer 60 is stacked on the nucleation layer 50 and covers the first surface.

[0065] In one embodiment, the substrate 10 is a single crystal silicon substrate or a single crystal-buried oxide layer composite silicon substrate, and the doping type of the substrate 10 is N-type doping or P-type doping.

[0066] In one embodiment, the single crystal-buried oxide layer composite silicon substrate 10 includes a stacked top single crystal silicon (Device Layer), a buried oxide layer (BOX), and a silicon substrate (Handle Wafer). The buried oxide layer is typically silicon dioxide, and the silicon substrate is typically single crystal silicon.

[0067] In one embodiment, the substrate 10 is a conductive substrate.

[0068] In one embodiment, the dielectric layer 21 comprises one of silicon oxide (SiO2), silicon nitride (SiNx), gallium oxide (Ga2O3), aluminum nitride (AlN), and aluminum oxide (Al2O3). The thickness of the dielectric layer 21 (i.e., the dimension of the dielectric layer along the first direction) is 20 nm to 1000 nm. It will be appreciated that the width of the dielectric layer 21 along the second direction corresponds to the first region.

[0069] CombineFigures 5a-5b As shown, for a first region a located between two second regions b: the width of the first surface of the first region a in the second direction (i.e., the lateral dimension) is 1 μm to 50 μm. For a second region b located between two first regions a: the width of the first surface of the second region b in the second direction is less than or equal to 1000 nm. It should be noted that Figures 5a-5b Only a portion of the substrate is shown, and thus the width of the first region a or the second region b located at the edge of the substrate 10 in the second direction may not be limited thereto.

[0070] It is understood that when the first region a and the second region b are sequentially spaced apart along the transverse

[100] crystal direction, the width of the dielectric layer is the dimension along the

[100] crystal direction. Alternatively, when the first region a and the second region b are sequentially spaced apart along the

[110] crystal direction, the width of the dielectric layer 21 is the dimension along the

[110] crystal direction.

[0071] In one embodiment, the crystal structure of the photonic crystal layer 40 is a cubic diamond structure or a zinc blende structure. The room temperature lattice parameter of the photonic crystal layer 40 ranges from 5.4 Å to 5.7 Å. The doping concentration of the photonic crystal layer 40 is less than 1E18 cm -3 , and the doping type of the photonic crystal layer 40 is the same as the doping type of the substrate 10 .

[0072] In one embodiment, the photonic crystal layer 40 has a third surface 401, which is disposed opposite the first surface. Photonic crystal units 41 extend downward from the third surface 401, and the periodically spaced photonic crystal units 41 form a photonic crystal structure. The thickness of the photonic crystal units 41 located above the first region is less than or equal to the distance between the third surface 401 and the surface of the dielectric layer 21. The thickness of the photonic crystal units 41 located above the second region is less than or equal to the distance between the third surface 401 and the first surface.

[0073] In a specific embodiment, the periodically arranged photonic crystal units 41 of the photonic crystal layer 40 are formed by etching, photolithography, etc. Therefore, the thickness of the photonic crystal unit 41 (i.e., the etching depth) can be set according to needs, as illustrated below with reference to the accompanying drawings:

[0074] Ginseng Figure 1 As shown, in a specific embodiment, the thickness of the photonic crystal unit 41 located above the first region and the photonic crystal unit 41 located above the second region are both equal to the distance between the third surface 401 and the surface of the dielectric layer 21, that is, the photonic crystal unit 41 extends from the third surface 401 to the plane where the surface of the dielectric layer 21 is located.

[0075] In this case, the photonic crystal layer 40 can be considered as comprising a first buffer layer 31 and a photonic crystal structure layer, wherein the first buffer layer 31 is formed on the first surface of the second region, and the photonic crystal structure layer comprises a plurality of photonic crystal units 41 periodically arranged on the first buffer layer 31 and on the dielectric layer 21. Furthermore, in this case, the material of the photonic crystal units 41 is the same as the material of the top layer of the first buffer layer 31. For example, if the first buffer layer 31 comprises an AlP film and a GaP film stacked in sequence, and the top layer of the first buffer layer 31 is a GaP film, then the material of the photonic crystal units is GaP.

[0076] Ginseng Figure 2 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 located above the first region and the photonic crystal unit 41 located above the second region are both smaller than the distance between the third surface 401 and the surface of the dielectric layer 21, that is, the photonic crystal unit extends from the third surface 401 to the plane located above the dielectric layer 21.

[0077] In this case, the photonic crystal layer 40 can be considered as comprising a first buffer layer 31, a second buffer layer 32, and a photonic crystal structure layer. The first buffer layer 31 is formed on the first surface of the second region b, the second buffer layer 32 covers the dielectric layer 21 and the first buffer layer 31, and the photonic crystal structure layer comprises a plurality of photonic crystal units 41 periodically arranged on the second buffer layer 32. Furthermore, in this case, the material of the photonic crystal units 41 is the same as the material of the top layer of the second buffer layer 32. For example, if the second buffer layer 32 comprises an AlP thin film and a GaP thin film stacked in sequence, and the top layer of the second buffer layer 32 is a GaP thin film, then the material of the photonic crystal units is GaP.

[0078] Ginseng Figure 3 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 located above the first region is equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal unit 41 located above the second region is equal to the distance between the third surface 401 and the first surface. In other words, the photonic crystal unit extends from the third surface 401 to the surface of the dielectric layer 21 and the first surface of the second region.

[0079] Furthermore, the photonic crystal layer 40 can be considered as comprising a photonic crystal structure layer, which comprises a plurality of photonic crystal units 41 periodically arranged on the first surface of the second region and on the dielectric layer 21 .

[0080] Furthermore, the photonic crystal unit 41 is a single-layer structure or a multi-layer structure.

[0081] In a specific embodiment, the photonic crystal unit 41 is a single-layer structure, and the photonic crystal unit 41 includes a Ge thin film, or the photonic crystal unit 41 includes GaAs.

[0082] In another specific embodiment, the photonic crystal unit 41 is a multi-layer structure, including an AlP film and a GaP film stacked in sequence, or the photonic crystal unit 41 is a repeatedly stacked superlattice structure including GaAs-AlGaAs.

[0083] In one embodiment, the thickness of each photonic crystal unit 41 is 10 nm to 10 μm, and the roughness of the side surface of the photonic crystal unit 41 is less than or equal to 10 nm.

[0084] In one embodiment, the resonant wavelength of the photonic crystal layer 40 is greater than or equal to 800 nm.

[0085] In one embodiment, the arrangement period of the photonic crystal units 41 is 200 nm to 5 μm, and the duty cycle of the photonic crystal layer 40 is 0.1 to 0.9 (the ratio of the width of the photonic crystal units 41 within one arrangement period to the arrangement period is 0.1 to 0.9). That is, the photonic crystal units 41 of the photonic crystal layer 40 are arranged periodically, and the sum of the width of a photonic crystal unit 41 and the width of an interval is 200 nm to 5 μm, of which the ratio of the width of the photonic crystal unit 41 is 0.1 to 0.9, that is, the width of the photonic crystal unit 41 is 20 nm to 4.5 μm.

[0086] It should be noted that the periodic arrangement direction of the photonic crystal units 41 is the same as the spacing direction of the first region and the second region, that is, the periodic arrangement direction of the photonic crystal units 41 is the second direction. For example, when the first region a and the second region b are sequentially spaced along the second direction (e.g., the transverse

[100] crystal direction), the periodic arrangement direction of the photonic crystal units 41 is along the

[100] crystal direction; or when the first region a and the second region b are sequentially spaced along the second direction (e.g., the transverse

[110] crystal direction), the photonic crystal units 41 are periodically arranged along the transverse

[110] crystal direction.

[0087] In one embodiment, the nucleation layer 50 includes a plurality of periodically arranged nucleation units 51. The arrangement period of the nucleation units 51 in the nucleation layer 50 is the same as the period of the photonic crystal units 41 in the photonic crystal layer 40, and the duty cycle of the nucleation layer 50 is the same as the duty cycle of the photonic crystal layer 40. That is, the period of the nucleation layer 50 is 200 nm to 5 μm, and the duty cycle of the nucleation layer 50 is 0.1 to 0.9. Similarly, the periodic arrangement direction of the nucleation units 51 is the same as the periodic arrangement direction of the photonic crystal units 41. It will be understood that each nucleation unit 51 exactly covers the surface of one photonic crystal unit 41.

[0088] In one embodiment, the crystal structure of the nucleation layer 50 is a zinc blende structure, such as GaInP, GaAs, InP, etc. The thickness of the nucleation layer 50 is 10 nm to 300 nm.

[0089] In one embodiment, the nucleation layer 50 has a single-layer structure or a multi-layer structure. "Single-layer structure or multi-layer structure" refers to the material type of the nucleation layer 50. For example, in one embodiment, the nucleation layer 50 has a single-layer structure and includes InP. In another embodiment, the nucleation layer 50 has a multi-layer structure and includes GaInP and GaAs stacked in sequence.

[0090] In one embodiment, the doping type of the nucleation layer 50 is the same as the doping type of the substrate 10 .

[0091] In one embodiment, the material of the epitaxial layer 60 is the same as the material of the top layer of the nucleation layer 50 .

[0092] In one embodiment, the doping type of the epitaxial layer 60 is the same as the doping type of the substrate 10 , and the thickness of the epitaxial layer 60 is 100 nm to 1000 nm.

[0093] Ginseng Figure 4 As shown, the present invention also provides a method for preparing a heterogeneous integrated structure, which is used to prepare the heterogeneous integrated structure in any of the above embodiments.

[0094] Combine Figures 5a-5f As shown, the preparation method of the heterogeneous integrated structure specifically includes:

[0095] S201, providing a substrate 10, the substrate 10 having a first surface and a second surface disposed opposite to each other, the first surface comprising a first region a and a second region b spaced apart. The first region and the second region are spaced apart in sequence along a second direction. The first direction is a longitudinal

[001] crystal direction (i.e., the first direction is perpendicular to the first surface), and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> The crystal direction, ie, the second direction, is parallel to the first surface and perpendicular to the first direction.

[0096] For the first region a located between the two second regions b: the width of the first surface of the first region a in the second direction (i.e., the lateral dimension) is 1 μm to 50 μm. For the second region b located between the two first regions a: the width of the first surface of the second region b in the second direction is less than or equal to 1000 nm. It should be noted that, Figure 5a Only a portion of the substrate is shown, and thus the width of the first region a or the second region b located at the edge of the substrate 10 may not be limited thereto.

[0097] It can be understood that the first region a and the second region b can constitute the entire first surface of the substrate 10; they can also constitute part of the first surface of the substrate 10, that is, the first surface of the substrate 10 can also include other regions, such as the third region or the fourth region, and this application does not impose any restrictions on this.

[0098] In one embodiment, the substrate 10 is a single crystal silicon substrate or a single crystal-buried oxide layer composite silicon substrate.

[0099] S202 , forming a dielectric layer 21 on the first surface. At this time, the dielectric layer 21 covers the first area a and the second area b.

[0100] Ginseng Figure 5a As shown, the dielectric layer 21 includes one of silicon oxide (SiO2), silicon nitride (SiNx), gallium oxide (Ga2O3), aluminum nitride (AlN) and aluminum oxide (Al2O3), and the thickness of the dielectric layer 21 (i.e., the dimension of the dielectric layer along the

[001] crystal direction) is 20nm~1000nm.

[0101] S203 , removing the dielectric layer 21 on the first surface of the second region b to expose the second region b.

[0102] Ginseng Figure 5b As shown, using micromachining processes such as photolithography and etching, part of the dielectric layer 21 is removed until the first surface of the substrate 10 is completely exposed, and the dielectric layer 21 is grooved along the second direction. The groove width is less than or equal to 1000 nm, and the width of the dielectric layer 21 not removed on both sides of the groove is 1 μm to 50 μm.

[0103] At this time, the dielectric layer 21 is retained on the first surface of the first region a, and the width of the dielectric layer 21 along the second direction on the first region a is 1 μm to 50 μm (that is, the width of the retained dielectric layer 21 corresponds to the width of the first region a, and the width of the removed dielectric layer 21 corresponds to the width of the second region b).

[0104] S204 , forming a buffer layer 30 on the dielectric layer 21 and the second region.

[0105] Combine Figure 5c As shown, in one specific implementation, S204 specifically includes:

[0106] S2041, using a fluorine-containing chemical solution to remove native oxide on the exposed first surface of the substrate 10, and cleaning to remove etching byproducts on the surface;

[0107] S2042, epitaxially growing a single or multi-layer buffer layer 30 on the dielectric layer 21 and the second region by physical or chemical vapor deposition, wherein the ratio of the growth rate of the buffer layer 30 along the first direction to the growth rate along the second direction is greater than or equal to 1.5, wherein the first direction is the

[001] crystal direction, and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

[0108] It can be understood that the lateral growth rate is greater than the longitudinal growth rate, which can ensure that the buffer layer compound grows laterally on different dielectric layers and merges to form a continuous thin film.

[0109] In one embodiment, the buffer layer 30 needs to have a crystal structure of diamond or zinc blende, a room temperature lattice parameter range of 5.4 Å to 5.7 Å, and a doping type of the buffer layer 30 that is consistent with the doping type of the substrate 10, with a doping concentration less than 1E18 cm -3 .

[0110] S2043, polishing the surface of the buffer layer 30 until the root mean square roughness of the surface of the buffer layer 30 is less than or equal to 1 nm. Further, the buffer layer 30 is thinned and polished to a target thickness, and the surface of the buffer layer 30 is cleaned and dried.

[0111] It is understood that the buffer layer 30, after being thinned and polished to the target thickness in this embodiment, can be considered to include a first buffer layer 31 and a second buffer layer 32, wherein the first buffer layer 31 is located on the first surface of the second region, and the thickness of the first buffer layer 31 is consistent with the thickness of the dielectric layer 21. The second buffer layer 32 covers the dielectric layer 21 and the first buffer layer 31, and the thickness of the second buffer layer 32 is 10nm-10μm. It should be noted that the division of the first buffer layer 31 and the second buffer layer 32 here is for the convenience of distinguishing them in subsequent steps. In the actual preparation process, the first buffer layer 31 and the second buffer layer 32 are grown and prepared together (i.e., serve as the buffer layer 30).

[0112] S205 , forming a nucleation layer 50 on the buffer layer 30 , and using the nucleation layer 50 as a mask to remove a portion of the buffer layer 30 to form a photonic crystal layer 40 .

[0113] Combine Figure 5d and Figure 5e As shown, in one specific implementation, S205 specifically includes:

[0114] S2051, forming a nucleation layer 50 on the buffer layer 30, wherein the nucleation layer 50 completely covers the surface of the buffer layer 30;

[0115] In one specific embodiment, a physical or chemical vapor deposition method is used to epitaxially grow a nucleation layer 50 having a sphalerite crystal structure, wherein the nucleation layer 50 is a single layer or a multilayer, and the nucleation layer 50 film needs to completely cover the surface of the buffer layer 30, and the doping type of the nucleation layer 50 is consistent with the doping type of the substrate 10.

[0116] S2052, removing a portion of the nucleation layer 50 and exposing a portion of the buffer layer 30 to form a plurality of periodically arranged nucleation units 51;

[0117] In one embodiment, a periodically arranged nucleation unit 51 is formed on the nucleation layer 50 by photolithography and etching. It is understood that the multiple nucleation units 51 serve as a mask pattern with a period of 200 nm to 5 μm and a duty cycle of 0.1 to 0.9.

[0118] S2053 , using the periodically arranged nucleation units 51 as a mask, a portion of the buffer layer 30 is removed to form a photonic crystal layer 40 .

[0119] In one specific embodiment, the nucleation layer 50 is used as a mask to form the photonic crystal layer 40 by etching to remove a portion of the buffer layer 30. The etching selectivity ratio between the nucleation layer 50 and the buffer layer 30 is greater than or equal to 10, the resonant wavelength of the photonic crystal layer 40 is greater than or equal to 800 nm, the etching depth of the second buffer layer 32 is between 10 nm and 10 μm, and the sidewall roughness is less than or equal to 10 nm (i.e., the roughness of the side surface of the photonic crystal unit 41 is less than or equal to 10 nm).

[0120] In one specific embodiment, the photonic crystal layer 40 has a third surface 401, which is arranged opposite to the first surface. The photonic crystal unit 41 extends downward from the third surface 401. The thickness of the photonic crystal unit 41 located above the first area is less than or equal to the distance between the third surface 401 and the surface of the dielectric layer 21. The thickness of the photonic crystal unit 41 located above the second area is less than or equal to the distance between the third surface 401 and the first surface.

[0121] It is understandable that the etching depth can be set according to needs, and the following is an example with reference to the accompanying drawings:

[0122] Ginseng Figure 1 As shown, in a specific embodiment, the thickness of the photonic crystal unit 41 located above the first region and the photonic crystal unit 41 located above the second region are both equal to the distance between the third surface 401 and the surface of the dielectric layer 21, that is, the photonic crystal unit 41 extends from the third surface 401 to the plane where the surface of the dielectric layer 21 is located.

[0123] Furthermore, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31 and a photonic crystal structure layer, the first buffer layer 31 is formed on the first surface of the second region, and the photonic crystal structure layer includes a plurality of photonic crystal units 41 periodically arranged on the first buffer layer 31 and on the dielectric layer 21.

[0124] Ginseng Figure 2 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 located above the first region and the photonic crystal unit 41 located above the second region are both smaller than the distance between the third surface 401 and the surface of the dielectric layer 21, that is, the photonic crystal unit 41 extends from the third surface 401 to the plane located above the dielectric layer 21.

[0125] Furthermore, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31, a second buffer layer 32 and a photonic crystal structure layer, the first buffer layer 31 is formed on the first surface of the second region b, the second buffer layer 32 covers the dielectric layer 21 and the first buffer layer 31, and the photonic crystal structure layer includes a plurality of photonic crystal units 41 periodically arranged on the second buffer layer 32.

[0126] Ginseng Figure 3 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 located above the first region is equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal unit 41 located above the second region is equal to the distance between the third surface 401 and the first surface. In other words, the photonic crystal unit 41 extends from the third surface 401 to the surface of the dielectric layer 21 and the first surface of the second region.

[0127] Furthermore, the photonic crystal layer 40 can be considered as comprising a photonic crystal structure layer, which comprises a plurality of photonic crystal units 41 periodically arranged on the first surface of the second region and on the dielectric layer 21 .

[0128] S206 , forming an epitaxial layer 60 on the nucleation layer 50 , wherein the epitaxial layer 60 covers the first surface.

[0129] Ginseng Figure 5f As shown, in one embodiment, the photonic crystal layer 40 is chemically cleaned and surface treated, and an epitaxial layer 60 is epitaxially grown on the surface of the nucleation layer 50 by a physical or chemical vapor deposition method.

[0130] The doping type of the epitaxial layer 60 is consistent with the doping type of the substrate 10, and the ratio of the growth rate of the epitaxial layer 60 along the first direction to the growth rate along the second direction is greater than or equal to 2, wherein the first direction is the

[001] crystal direction and the second direction is perpendicular to the

[001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

[0131] It can be understood that the lateral rate of epitaxial growth is 2 times or more higher than the longitudinal growth rate, so that the epitaxial layer 60 grows and merges to form a continuous thin film. The thickness of the epitaxial layer 60 is 100nm ~ 1000nm, and the material of the epitaxial layer 60 is the same as the material of the top layer of the nucleation layer 50.

[0132] The present invention will be further described below with reference to specific embodiments.

[0133] Example 1:

[0134] This embodiment provides a method for preparing a heterogeneous integrated structure, which specifically includes:

[0135] On an 8-inch N-type Si substrate, a SiO2 layer (dielectric layer) is formed by oxidation along the longitudinal

[001] crystal direction, wherein the thickness of the SiO2 layer is 600 nm;

[0136] A deep ultraviolet (DUV) lithography machine and reactive ion etching (RIE) were used to create a dielectric mask (i.e., the dielectric layer on the first surface of the second region was removed to expose the second region). Specifically, a hole was etched in the SiO2 layer. The width of the hole along the

[110] crystal orientation was 300 nm, and the width of the unetched SiO2 layer (dielectric layer) was 12 μm.

[0137] A Ge film (buffer layer) was grown on the dielectric mask along the

[001] crystal orientation using reduced pressure chemical vapor deposition (RPCVD). The concentration of the Ge film was 5E17 cm -3 , the doping type of the Ge film is N-type, the thickness of the Ge film is 3 μm, and the Ge film covers the dielectric mask and the substrate;

[0138] Chemical mechanical polishing (CMP) was used to polish the surface roughness of the Ge film to 0.5 nm;

[0139] After chemical cleaning and drying on the surface of Ge film, metal organic chemical vapor deposition (MOCVD) was used for surface pretreatment and 50nm thick Ga film was grown. 0.51 In 0.49 P, and then grow a 200nm thick N-type GaAs layer. That is, the untreated nucleation layer of this embodiment includes a 50nm thick GaAs layer. 0.51 In 0.49 P and 200nm thick N-type GaAs layer.

[0140] A periodic mask pattern (i.e., periodically arranged nucleation units are prepared based on the nucleation layer) is produced by photolithography using a stepper lithography machine and inductively coupled plasma etching (ICP). The opening area of ​​the periodic mask pattern completely exposes the surface of the Ge film underneath. The period of the periodic mask pattern is 1 μm and the duty cycle is 0.4 (the opening width in this embodiment is 400 nm).

[0141] Based on a periodic mask pattern, an ICP tool was used to etch a 1.2μm-deep Ge thin film using a CF4 / O2 / He gas combination to form a periodic photonic crystal structure (photonic crystal layer) with a resonant wavelength of 2000nm. The sidewall roughness of the photonic crystal structure was 5nm. Furthermore, the ICP tool achieved an etch selectivity ratio of 12 when etching the periodic mask pattern of the nucleation layer relative to the buffer layer (i.e., the Ge thin film).

[0142] After surface cleaning, an N-type GaAs layer (epilayer) is grown epitaxially on the photonic crystal structure using MOCVD. The lateral growth rate of the N-type GaAs layer is three times the vertical growth rate, so that the surface of the N-type GaAs layer merges into a uniform thin film and completely covers the underlying photonic crystal structure, forming a suspended GaAs structure. In this embodiment, the thickness of the N-type GaAs layer is 600 nm.

[0143] This embodiment also provides a heterogeneous integrated structure, which is obtained based on the above-mentioned method for preparing the heterogeneous integrated structure.

[0144] Example 2:

[0145] This embodiment provides a method for preparing a heterogeneous integrated structure, which specifically includes:

[0146] A 200 nm thick SiN layer was deposited on a 6-inch P-type Si

[001] substrate. X layer (dielectric layer);

[0147] A deep ultraviolet (DUV) lithography machine and reactive ion etching (RIE) are used to make a dielectric mask (ie, the dielectric layer on the first surface of the second region is removed to expose the second region). X The hole is etched in the layer, and the width of the hole along the

[110] crystal direction is 300nm. X The width of the layer (dielectric layer) is 1.5 μm;

[0148] A 30nm thick AlP film and a 500nm thick P-type GaP film were grown on a dielectric mask along the

[001] crystal orientation using MOCVD. The GaP film surface was polished using CMP to a surface roughness of 0.3nm. The buffer layer in this embodiment has a multilayer structure, comprising sequentially stacked AlP and GaP films.

[0149] After chemical cleaning and drying on the surface of the GaP film, MOCVD is used for surface pretreatment and a 150nm thick InP layer (nucleation layer) is grown.

[0150] Electron beam lithography (EBL) and reactive ion etching (RIE) were used to produce a periodic mask pattern with a period of 220 nm and a duty cycle of 0.4. The opening area completely exposed the GaP film surface underneath.

[0151] Using a periodic InP layer (i.e., periodically arranged nucleation units) as a mask pattern, an ICP device was used to etch a GaP thin film using a BCl3 / Cl2 / N2 gas combination to form a periodic photonic crystal structure (photonic crystal layer) with a resonant wavelength of 900 nm. The sidewall roughness of the photonic crystal structure was 3 nm (i.e., the side surface roughness of the photonic crystal unit was 3 nm). In this embodiment, the etching selectivity between the InP layer and the GaP thin film was 10, and the etching depth of the GaP thin film was 180 nm (i.e., the thickness of the photonic crystal unit in this embodiment was 180 nm).

[0152] After cleaning the surface, an InP layer is epitaxially grown on the periodic InP layer using MOCVD. The lateral growth rate of the InP layer is twice the vertical growth rate. After growing a 1000nm thick P-type InP layer, the surface of the InP layer merges into a uniform film, completely covering the underlying photonic crystal, forming a suspended InP structure.

[0153] Compared to existing technologies, this invention monolithically integrates compound semiconductors on a silicon substrate. This involves lateral epitaxial growth of a buffer layer with a similar crystal structure or lattice constant on the substrate. After flattening the buffer layer, a compound semiconductor nucleation layer is grown. Subsequently, a photonic crystal structure with optical functionality is fabricated. The lateral growth of the microcrystal array is then flattened and combined to form an epitaxial layer suspended above the photonic crystal structure. This heterogeneous integrated structure can utilize large-scale silicon substrates, expanding the size of compound composite wafers to over 8 inches.

[0154] Suspended compound semiconductor epitaxial layers can be used to grow higher quality and more complex compound semiconductor films on large-scale silicon substrates. The photonic crystal layer beneath the epitaxial layer has special optical functions in the near-infrared band and at longer wavelengths, such as high reflection, low reflection, wavelength selection, and optical waveguides. The nanoscale periodic structure can also be used to relax the thermal mismatch between the substrate and the epitaxial layer, reducing the mechanical deformation of the substrate after epitaxial growth.

[0155] It will be apparent to those skilled in the art that the disclosure is not limited to the details of the above-exemplified embodiments and that the disclosure can be implemented in other particular forms without departing from the spirit or essential characteristics of the disclosure. The presently disclosed embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the disclosure being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No feature of the claims is to be construed as limiting the claims to the exact nature of the features described therein.

[0156] Furthermore, it should be understood that although the description is made on the basis of the embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that those skilled in the art can understand.

Claims

1. A heterogeneous integrated structure, characterized in that: include: a substrate having a first surface and a second surface disposed opposite to each other, wherein the first surface includes a first region and a second region disposed at intervals; a dielectric layer formed on the first surface of the first region; a photonic crystal layer, formed on the first surface of the second region and the dielectric layer, comprising a plurality of periodically spaced photonic crystal units; a nucleation layer comprising a plurality of nucleation units located on the surface of the photonic crystal unit; An epitaxial layer is stacked on the nucleation layer and covers the first surface.

2. The heterogeneous integrated structure according to claim 1, characterized in that: The photonic crystal layer has a third surface, which is arranged opposite to the first surface. The photonic crystal unit extends downward from the third surface. The thickness of the photonic crystal unit located above the first surface of the first region is less than or equal to the distance between the third surface and the surface of the dielectric layer. The thickness of the photonic crystal unit located above the first surface of the second region is less than or equal to the distance between the third surface and the first surface.

3. The heterogeneous integrated structure according to claim 1, characterized in that: The nucleation layer comprises a plurality of periodically arranged nucleation units, the arrangement period of the nucleation units is the same as the arrangement period of the photonic crystal units, and the duty cycle of the nucleation layer is the same as the duty cycle of the photonic crystal layer; and / or, The arrangement period of the photonic crystal units is 200 nm to 5 μm, and the duty cycle of the photonic crystal layer is 0.1 to 0.

9.

4. The heterogeneous integrated structure according to claim 1, characterized in that: The substrate is a single crystal silicon substrate or a single crystal-buried oxide layer composite silicon substrate; and / or, The width of the first surface of the second region in the second direction is less than or equal to 1000 nm, and the width of the first surface of the first region in the second direction is 1 μm to 50 μm, wherein the second direction is perpendicular to the [001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

5. The heterogeneous integrated structure according to claim 1, characterized in that: The dielectric layer comprises one of silicon oxide, aluminum oxide, gallium oxide, silicon nitride and aluminum nitride; and / or, The thickness of the dielectric layer is 20 nm to 1000 nm.

6. The heterogeneous integrated structure according to claim 1, characterized in that: The crystal structure of the photonic crystal layer is a cubic diamond structure or a zinc blende structure; and / or, The room temperature lattice parameter range of the photonic crystal layer is 5.4 Å to 5.7 Å; and / or, The doping concentration of the photonic crystal layer is less than 1E18 cm -3 .

7. The heterogeneous integrated structure according to claim 1, characterized in that: The thickness of the photonic crystal unit is 10 nm to 10 μm; and / or, The roughness of the side surface of the photonic crystal unit is less than or equal to 10 nm.

8. The heterogeneous integrated structure according to claim 1, characterized in that: The photonic crystal unit is a single-layer structure or a multi-layer structure; and / or, The nucleation layer is a single-layer structure or a multi-layer structure, and the material of the epitaxial layer is the same as the material of the top layer of the nucleation layer; and / or, The crystal structure of the nucleation layer is a sphalerite structure, and the thickness of the nucleation layer is 10 nm to 300 nm.

9. The heterogeneous integrated structure according to claim 1, characterized in that: The doping type of the photonic crystal layer, the nucleation layer and the epitaxial layer is the same as the doping type of the substrate; and / or, The crystal structure of the epitaxial layer is a zinc blende structure, and the thickness of the epitaxial layer is 100 nm to 1000 nm.

10. A method for preparing a heterogeneous integrated structure, characterized in that: include: Providing a substrate, the substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals; forming a dielectric layer on the first surface, wherein the dielectric layer covers the first area and the second area; removing the dielectric layer on the first surface of the second region to expose the second region; forming a buffer layer on the dielectric layer and the second region; forming a nucleation layer on the buffer layer, and using the nucleation layer as a mask to remove a portion of the buffer layer to form a photonic crystal layer; An epitaxial layer is formed on the nucleation layer, wherein the epitaxial layer covers the first surface.

11. The method for preparing a heterogeneous integrated structure according to claim 10, wherein: Forming a nucleation layer above the buffer layer, and using the nucleation layer as a mask to remove a portion of the buffer layer to form a photonic crystal layer, comprising: forming a nucleation layer on the buffer layer, wherein the nucleation layer covers the buffer layer; removing a portion of the nucleation layer and exposing a portion of the buffer layer to form a plurality of periodically arranged nucleation units; The periodically arranged nucleation units are used as a mask to remove a portion of the buffer layer to form a photonic crystal layer.

12. The method for preparing a heterogeneous integrated structure according to claim 10, wherein: forming a buffer layer on the dielectric layer and the second region, comprising: A single or multiple buffer layer is epitaxially grown on the dielectric layer and the second region by physical or chemical vapor deposition, wherein the ratio of the growth rate of the buffer layer along the first direction to the growth rate along the second direction is greater than or equal to 1.5, wherein the first direction is a [001] crystal direction and the second direction is perpendicular to the [001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

13. The method for preparing a heterogeneous integrated structure according to claim 12, wherein: After forming a buffer layer on the dielectric layer and the second region, polishing the surface of the buffer layer until the root mean square roughness of the surface of the buffer layer is less than or equal to 1 nm.

14. The method for preparing a heterogeneous integrated structure according to claim 10, wherein: Using the nucleation layer as a mask, an etching process is used to remove a portion of the buffer layer to form a photonic crystal layer, wherein the etching selectivity ratio of the nucleation layer to the buffer layer is greater than or equal to 10; and / or, The resonant wavelength of the photonic crystal layer is greater than or equal to 800 nm.

15. The method for preparing a heterogeneous integrated structure according to claim 10, wherein: forming an epitaxial layer on the nucleation layer, wherein the epitaxial layer covers the first surface, comprising: An epitaxial layer is epitaxially grown on the surface of the nucleation layer by a physical or chemical vapor deposition method, wherein the doping type of the epitaxial layer is consistent with the doping type of the substrate, and the ratio of the growth rate of the epitaxial layer along the first direction to the growth rate along the second direction is greater than or equal to 2, wherein the first direction is a [001] crystal direction and the second direction is perpendicular to the [001] crystal direction. <100> Crystal orientation or <110> Crystal direction.

Images