Heterogeneous integrated structures and their preparation methods

Abstract

This invention discloses a heterogeneous integrated structure and its fabrication method. The heterogeneous integrated structure includes: a substrate having a first surface and a second surface arranged opposite to each other, the first surface including a first region and a second region spaced apart; a dielectric layer formed on the first surface of the first region; a photonic crystal layer formed on the first surface of the second region and the dielectric layer, including a plurality of periodically arranged photonic crystal units; a nucleation layer including a plurality of nucleation units located on the surface of the photonic crystal units; and an epitaxial layer stacked on top of the nucleation layer and covering the first surface. The photonic crystal layer of this invention has special optical functions in the near-infrared band and at longer wavelengths. The nanoscale periodic structure can also be used to relax the thermal mismatch between the substrate and the epitaxial layer, reducing the mechanical deformation of the substrate after epitaxial growth. This invention can utilize large-size silicon substrates to extend the size of compound composite wafers to 8 inches or more.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor process technology, specifically relating to a heterogeneous integrated structure and its fabrication method. Background Technology

[0002] III-V compound semiconductors are fundamental to many photonics and optoelectronic applications. Taking GaAs, the most extensively studied material, as an example, its direct bandgap and high mobility have led to its use in lasers and radio frequency devices, widely applied in high-speed and high-power optical networks and communications.

[0003] The high-density dislocations resulting from lattice mismatch between the Si substrate and the epitaxial layer typically negatively impact the optical and electrical properties of the epitaxial layer. The difference in thermal expansion coefficients between the Si substrate and the epitaxial layer (GaAs / Si ≈ 123%) also leads to wafer bending and cracking in the epitaxial layer. Despite decades of research, heterogeneous monolithic integration of compound semiconductors with Si remains challenging. Furthermore, photonic and optoelectronic applications require the manipulation of photons, which are far more difficult to manipulate than electrons due to their weak interaction with matter.

[0004] Therefore, in order to address the above-mentioned technical problems, it is necessary to provide a heterogeneous integrated structure and its preparation method. Summary of the Invention

[0005] The purpose of this invention is to provide a heterogeneous integrated structure and its fabrication method, which can utilize a large-size silicon substrate to extend the size of the compound composite wafer to more than 8 inches.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A heterogeneous integrated structure, comprising:

[0008] A substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals;

[0009] A dielectric layer is formed on the first surface of the first region;

[0010] A photonic crystal layer, formed on the first surface of the second region and the dielectric layer, comprises a plurality of periodically spaced photonic crystal units;

[0011] The nucleation layer includes a plurality of nucleation units located on the surface of the photonic crystal unit;

[0012] An epitaxial layer is stacked on top of the nucleation layer and covers the first surface.

[0013] In one or more embodiments of the present invention, the photonic crystal layer has a third surface disposed opposite to the first surface, the photonic crystal unit extends downward from the third surface, the thickness of the photonic crystal unit located above the first surface in the first region is less than or equal to the distance between the third surface and the surface of the dielectric layer, and the thickness of the photonic crystal unit located above the first surface in the second region is less than or equal to the distance between the third surface and the first surface.

[0014] In one or more embodiments of the present invention, the nucleation layer includes a plurality of periodically arranged nucleation units, the arrangement period of the nucleation units is the same as the arrangement period of the photonic crystal units, and the duty cycle of the nucleation layer is the same as the duty cycle of the photonic crystal layer.

[0015] In one or more embodiments of the present invention, the arrangement period of the photonic crystal unit is 200 nm to 5 μm, and the duty cycle of the photonic crystal layer is 0.1 to 0.9.

[0016] In one or more embodiments of the present invention, the substrate is a single-crystal silicon substrate or a single-crystal-buried oxide composite silicon substrate.

[0017] In one or more embodiments of the present invention, the width of the first surface of the second region in the second direction is less than or equal to 1000 nm, and the width of the first surface of the first region in the second direction is 1 μm to 50 μm, wherein the second direction is perpendicular to the

[001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

[0018] In one or more embodiments of the present invention, the dielectric layer comprises one of silicon oxide, aluminum oxide, gallium oxide, silicon nitride, and aluminum nitride.

[0019] In one or more embodiments of the present invention, the thickness of the dielectric layer is 20 nm to 1000 nm.

[0020] In one or more embodiments of the present invention, the crystal structure of the photonic crystal layer is a cubic diamond structure or a zincblende structure.

[0021] In one or more embodiments of the present invention, the room-temperature lattice parameter of the photonic crystal layer ranges from 5.4 Å to 5.7 Å. The doping concentration of the photonic crystal layer is less than 1E18 cm⁻¹. -3 .

[0022] In one or more embodiments of the present invention, the thickness of the photonic crystal unit is 10 nm to 10 μm; and / or, the roughness of the side surface of the photonic crystal unit is less than or equal to 10 nm.

[0023] In one or more embodiments of the present invention, the photonic crystal unit is a single-layer structure or a multi-layer structure; and / or, the nucleation layer is a single-layer structure or a multi-layer structure, and the material of the epitaxial layer is the same as the material of the top layer of the nucleation layer.

[0024] In one or more embodiments of the present invention, the crystal structure of the nucleation layer is a zincblende structure, and the thickness of the nucleation layer is 10 nm to 300 nm.

[0025] In one or more embodiments of the present invention, the doping type of the photonic crystal layer, nucleation layer and epitaxial layer is the same as the doping type of the substrate; and / or, the crystal structure of the epitaxial layer is a zincblende structure, and the thickness of the epitaxial layer is 100 nm to 1000 nm.

[0026] Another specific embodiment of the present invention provides a method for preparing a heterogeneous integrated structure, comprising:

[0027] A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals;

[0028] A dielectric layer is formed on the first surface, the dielectric layer covering the first region and the second region;

[0029] Remove the dielectric layer on the first surface of the second region to expose the second region;

[0030] A buffer layer is formed on the dielectric layer and the second region;

[0031] A nucleation layer is formed above the buffer layer, and the nucleation layer is used as a mask to remove part of the buffer layer to form a photonic crystal layer;

[0032] An epitaxial layer is formed above the nucleation layer, and the epitaxial layer covers the first surface.

[0033] In one or more embodiments of the present invention, a nucleation layer is formed above the buffer layer, and the nucleation layer is used as a mask to remove a portion of the buffer layer to form a photonic crystal layer, including:

[0034] A nucleation layer is formed on the buffer layer, and the nucleation layer covers the buffer layer;

[0035] Part of the nucleation layer is removed and part of the buffer layer is exposed to form a plurality of periodically arranged nucleation units;

[0036] Using the periodically arranged nucleation units as a mask, a portion of the buffer layer is removed to form a photonic crystal layer.

[0037] In one or more embodiments of the present invention, a buffer layer is formed on the dielectric layer and the second region, including:

[0038] A single or multiple buffer layer is epitaxially grown on the dielectric layer and the second region using physical or chemical vapor deposition. The ratio of the growth rate of the buffer layer along a first direction to the growth rate along a second direction is greater than or equal to 1.5, wherein the first direction is the

[001] crystal orientation, and the second direction is perpendicular to the

[001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

[0039] In one or more embodiments of the present invention, after a buffer layer is formed on the dielectric layer and the second region, the surface of the buffer layer is polished until the root mean square roughness of the surface of the buffer layer is less than or equal to 1 nm.

[0040] In one or more embodiments of the present invention, the nucleation layer is used as a mask, and a portion of the buffer layer is removed by an etching process to form a photonic crystal layer, wherein the etching selectivity ratio of the nucleation layer to the buffer layer is greater than or equal to 10; and / or the resonant wavelength of the photonic crystal layer is greater than or equal to 800 nm.

[0041] In one or more embodiments of the present invention, an epitaxial layer is formed above the nucleation layer, the epitaxial layer covering the first surface, including:

[0042] An epitaxial layer is epitaxially grown on the surface of the nucleation layer using physical or chemical vapor deposition. The doping type of the epitaxial layer is consistent with the doping type of the substrate. The ratio of the growth rate of the epitaxial layer along a first direction to the growth rate along a second direction is greater than or equal to 2, wherein the first direction is the

[001] crystal orientation, and the second direction is perpendicular to the

[001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

[0043] Compared with existing technologies, the heterogeneous integrated structure and its fabrication method of the present invention involve growing a buffer layer laterally on a substrate, growing a nucleation layer on the planarized buffer layer, using the nucleation layer as a mask to prepare a photonic crystal layer with optical functions, and then using the lateral growth of a microcrystal array to lay and merge the layers to form an epitaxial layer suspended above the photonic crystal structure. The heterogeneous integrated structure of the present invention can utilize large-size silicon substrates, extending the size of compound composite wafers to over 8 inches.

[0044] The suspended epitaxial layer in this invention can be used to grow higher quality and more complex compound semiconductor thin films on large-size silicon substrates. The photonic crystal layer under the epitaxial layer has special optical functions in the near-infrared band and longer wavelengths, such as high reflection, low reflection, wavelength selectivity and optical waveguide. The nanoscale periodic structure can also be used to relax the thermal mismatch between the substrate and the epitaxial layer and reduce the mechanical deformation of the substrate after epitaxial growth. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of a heterogeneous integrated structure according to one embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of a heterogeneous integrated structure according to another embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the heterogeneous integrated structure in another embodiment of the present invention;

[0049] Figure 4 This is a flowchart of a method for preparing a heterogeneous integrated structure according to an embodiment of the present invention;

[0050] Figures 5a-5f This is a schematic diagram illustrating the structural changes in the preparation method of the heterogeneous integrated structure according to one embodiment of the present invention. Detailed Implementation

[0051] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0052] As mentioned in the background art, to combine the optoelectronic properties of III-V compound semiconductors with silicon-based microelectronic technology and achieve monolithic integration, it is necessary to directly epitaxially grow single crystal materials of compound semiconductors such as GaAs on the

[001] crystal orientation of a Si substrate. The high-density dislocations generated by the lattice mismatch between the Si substrate and the epitaxial layer usually have a negative impact on the optical and electrical properties of the epitaxial layer. In addition, the difference in the coefficient of thermal expansion between the Si substrate and the epitaxial layer, GaAs / Si≈123%, will also cause wafer bending and cracking in the epitaxial layer. Despite decades of research, the heterogeneous monolithic integration of compound semiconductors and Si remains challenging.

[0053] On the other hand, photonics and optoelectronic applications require the manipulation of photons. Due to the weak interaction between photons and matter, photons are much more difficult to manipulate than electrons. Photonic crystals are a method of manipulating light using the spatial periodic distribution of materials. By adjusting the photonic crystal structure, the dispersion relation and conduction or radiation modes of light can be artificially customized. The period of photonic crystals is within the photon wavelength range. For photonic crystal structures in the near-infrared and visible light bands, the lattice constant is usually on the order of a few hundred nanometers. Silicon and germanium material systems compatible with silicon-based CMOS are more suitable for fabricating nanostructures with high precision and high aspect ratio.

[0054] To facilitate the understanding of the technical solutions of this application, the following first provides a detailed explanation of the technical terms that may appear in this invention.

[0055] III-V compound: A binary or multi-element compound semiconductor material composed of elements in Group III (Group 13) and Group V (Group 15) of the periodic table. Common III-V compounds are composed of combinations of Al, Ga, In and N, P, As, Sb (such as GaAs, InP, AlN, InGaAs, AlGaAsSb, etc.).

[0056] <100> crystal orientation: The crystal orientation family in the diamond and zinc blende structures where the nearest-neighbor atomic spacing is equal to the lattice constant, including the

[100] crystal orientation,

[010] crystal orientation,

[001] crystal orientation, [-100] crystal orientation, [0-10] crystal orientation, [00-1] crystal orientation;

[0057] <110> crystal orientation: The crystal orientation family in the diamond and zinc blende structures where the nearest-neighbor atomic spacing is equal to √2 times the lattice constant, including the

[110] crystal orientation, [-1-10] crystal orientation,

[101] crystal orientation, [-10-1] crystal orientation,

[011] crystal orientation, [0-1-1] crystal orientation, [1-10] crystal orientation, [-110] crystal orientation, [10-1] crystal orientation, [-101] crystal orientation, [01-1] crystal orientation, [0-11] crystal orientation.

[0058] See Figure 1 As shown, a heterogeneous integrated structure of the present invention includes:

[0059] Substrate 10 has a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region disposed at intervals. The first region and the second region are sequentially spaced apart along a second direction. The first direction is a longitudinal

[001] crystal orientation (i.e., the first direction is perpendicular to the first surface), and the second direction is perpendicular to the

[001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation, that is, the second direction is parallel to the first surface and perpendicular to the first direction.

[0060] It is understood that the first region and the second region can constitute the entire first surface of the substrate 10, or they can constitute a part of the first surface of the substrate 10. That is, the first surface of the substrate 10 can also include other regions, such as the third region or the fourth region. This application does not limit this.

[0061] Dielectric layer 21 is formed on the first surface of the first region;

[0062] A photonic crystal layer 40 is formed on the first surface of the second region b and on the dielectric layer 21, and includes a plurality of periodically spaced photonic crystal units 41.

[0063] The nucleation layer 50 includes a plurality of nucleation units 51 located on the surface of the photonic crystal unit 41;

[0064] An epitaxial layer 60 is stacked above the nucleation layer 50 and covers the first surface.

[0065] In one embodiment, the substrate 10 is either a single-crystal silicon substrate or a single-crystal-buried oxide composite silicon substrate, and the doping type of the substrate 10 is either N-type doping or P-type doping.

[0066] In one embodiment, the single-crystal-buried oxide composite silicon substrate 10 includes a top single-crystal silicon (Device Layer), a buried oxide layer (BOX), and a silicon substrate (Handle Wafer) stacked together. The buried oxide layer is typically silicon dioxide, and the silicon substrate is typically single-crystal silicon.

[0067] In one embodiment, the substrate 10 is a conductive substrate.

[0068] In one embodiment, the dielectric layer 21 comprises one of silicon oxide (SiO2), silicon nitride (SiNx), gallium oxide (Ga2O3), aluminum nitride (AlN), and aluminum oxide (Al2O3). The thickness of the dielectric layer 21 (i.e., the dimension of the dielectric layer along the first direction) is 20 nm to 1000 nm. It is understood that the width of the dielectric layer 21 in the second direction corresponds to the first region.

[0069] Combination Figures 5a-5b As shown, for the first region a located between two second regions b: the width (i.e., the lateral dimension) of the first surface of the first region a in the second direction is 1 μm to 50 μm. For the second region b located between two first regions a: the width of the first surface of the second region b in the second direction is less than or equal to 1000 nm. It should be noted that Figures 5a-5b Only a part of the substrate is shown, so the width of the first region a or the second region b located at the edge of the substrate 10 in the second direction may not be limited by this.

[0070] It can be understood that when the first region a and the second region b are arranged at intervals in the

[100] crystal direction in the lateral direction, the width of the dielectric layer is the dimension in the

[100] crystal direction. Or, when the first region a and the second region b are arranged at intervals in the

[110] crystal direction, the width of the dielectric layer 21 is the dimension in the

[110] crystal direction.

[0071] In one embodiment, the crystal structure of the photonic crystal layer 40 is a diamond structure or a zinc blende structure of the cubic crystal system. The room-temperature lattice parameter range of the photonic crystal layer 40 is 5.4 Å to 5.7 Å. The doping concentration of the photonic crystal layer 40 is less than 1E18 cm -3 , and the doping type of the photonic crystal layer 40 is the same as the doping type of the substrate 10.

[0072] In one embodiment, the photonic crystal layer 40 has a third surface 401, and the third surface 401 is arranged opposite to the first surface. The photonic crystal units 41 extend downward from the third surface 401, and the periodically arranged and spaced photonic crystal units 41 constitute the photonic crystal structure. The thickness of the photonic crystal units 41 located above the first region is less than or equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal units 41 located above the second region is less than or equal to the distance between the third surface 401 and the first surface.

[0073] In a specific embodiment, the periodically arranged photonic crystal units 41 of the photonic crystal layer 40 are formed by etching, photolithography, etc. Therefore, the thickness (i.e., the etching depth) of the photonic crystal units 41 can be set according to requirements. The following is an example with reference to the drawings:

[0074] Refer Figure 1 As shown, in a specific embodiment, the thicknesses of the photonic crystal units 41 located above the first region and the photonic crystal units 41 located above the second region are both equal to the distance between the third surface 401 and the surface of the dielectric layer 21. That is, the photonic crystal units 41 extend from the third surface 401 to the plane where the surface of the dielectric layer 21 is located.

[0075] At this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31 and a photonic crystal structure layer. The first buffer layer 31 is formed on the first surface of the second region. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically on the first buffer layer 31 and above the dielectric layer 21. Further, at this time, the material of the photonic crystal unit 41 is the same as the material of the top layer of the first buffer layer 31. For example, if the first buffer layer 31 includes an AlP thin film and a GaP thin film stacked in sequence, the top layer of the first buffer layer 31 is the GaP thin film, and the material of the photonic crystal unit is GaP.

[0076] Refer Figure 2 As shown, in another specific embodiment, the thicknesses of the photonic crystal units 41 above the first region and the photonic crystal units 41 above the second region are both less than the distance between the third surface 401 and the surface of the dielectric layer 21. That is, the photonic crystal units extend from the third surface 401 to a plane above the dielectric layer 21.

[0077] At this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31, a second buffer layer 32 and a photonic crystal structure layer. The first buffer layer 31 is formed on the first surface of the second region b. The second buffer layer 32 covers the dielectric layer 21 and the first buffer layer 31. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically above the second buffer layer 32. Further, at this time, the material of the photonic crystal unit 41 is the same as the material of the top layer of the second buffer layer 32. For example, if the second buffer layer 32 includes an AlP thin film and a GaP thin film stacked in sequence, the top layer of the second buffer layer 32 is the GaP thin film, and the material of the photonic crystal unit is GaP.

[0078] Refer Figure 3 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 above the first region is equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal unit 41 above the second region is equal to the distance between the third surface 401 and the first surface. That is, the photonic crystal units extend from the third surface 401 to the surface of the dielectric layer 21 and the first surface of the second region.

[0079] Further, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a photonic crystal structure layer. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically on the first surface of the second region and above the dielectric layer 21.

[0080] Further, the photonic crystal unit 41 is a single-layer structure or a multi-layer structure.

[0081] In one specific embodiment, the photonic crystal unit 41 is a single-layer structure, and the photonic crystal unit 41 includes a Ge thin film, or the photonic crystal unit 41 includes GaAs.

[0082] In another specific embodiment, the photonic crystal unit 41 is a multilayer structure, which includes AlP thin films and GaP thin films stacked sequentially, or the photonic crystal unit 41 is a repeating superlattice structure including GaAs-AlGaAs.

[0083] In one embodiment, the thickness of each photonic crystal unit 41 is 10 nm to 10 μm, and the roughness of the side surface of the photonic crystal unit 41 is less than or equal to 10 nm.

[0084] In one embodiment, the resonant wavelength of the photonic crystal layer 40 is greater than or equal to 800 nm.

[0085] In one embodiment, the arrangement period of the photonic crystal units 41 is 200 nm to 5 μm, and the duty cycle of the photonic crystal layer 40 is 0.1 to 0.9 (the ratio of the width of the photonic crystal unit 41 to the arrangement period within one arrangement period is 0.1 to 0.9). That is, the photonic crystal units 41 of the photonic crystal layer 40 are arranged periodically, and the sum of the width of one photonic crystal unit 41 and the width of one interval is 200 nm to 5 μm, wherein the proportion of the width of the photonic crystal unit 41 is 0.1 to 0.9, that is, the width of the photonic crystal unit 41 is 20 nm to 4.5 μm.

[0086] It should be noted that the periodic arrangement direction of the photonic crystal unit 41 is the same as the spacing direction of the first region and the second region, that is, the periodic arrangement direction of the photonic crystal unit 41 is the second direction. For example, when the first region a and the second region b are arranged alternately along the second direction (e.g., the transverse

[100] crystal direction), the periodic arrangement direction of the photonic crystal unit 41 is along the

[100] crystal direction, or when the first region a and the second region b are arranged alternately along the second direction (e.g., the transverse

[110] crystal direction), the photonic crystal unit 41 is periodically arranged along the transverse

[110] crystal direction.

[0087] In one embodiment, the nucleation layer 50 includes a plurality of periodically arranged nucleation units 51. The arrangement period of the nucleation units 51 in the nucleation layer 50 is the same as the period of the photonic crystal units 41 in the photonic crystal layer 40, and the duty cycle of the nucleation layer 50 is the same as that of the photonic crystal layer 40. That is, the period of the nucleation layer 50 is 200 nm to 5 μm, and the duty cycle of the nucleation layer 50 is 0.1 to 0.9. Similarly, the periodic arrangement direction of the nucleation units 51 is the same as the periodic arrangement direction of the photonic crystal units 41. It can be understood that each nucleation unit 51 exactly covers the surface of one photonic crystal unit 41.

[0088] In one embodiment, the crystal structure of the nucleation layer 50 is a zinc blende structure, such as GaInP, GaAs, InP, etc. The thickness of the nucleation layer 50 is 10 nm to 300 nm.

[0089] In one embodiment, the nucleation layer 50 is a single-layer structure or a multi-layer structure. "Single-layer structure or multi-layer structure" refers to the type of material of the nucleation layer 50. For example: in a specific embodiment, the nucleation layer 50 is a single-layer structure, and the nucleation layer 50 includes InP. In another specific embodiment, the nucleation layer 50 is a multi-layer structure, and the nucleation layer 50 includes GaInP and GaAs stacked in sequence.

[0090] In one embodiment, the doping type of the nucleation layer 50 is the same as the doping type of the substrate 10.

[0091] In one embodiment, the material of the epitaxial layer 60 is the same as the material of the top layer of the nucleation layer 50.

[0092] In one embodiment, the doping type of the epitaxial layer 60 is the same as the doping type of the substrate 10, and the thickness of the epitaxial layer 60 is 100 nm to 1000 nm.

[0093] Refer Figure 4 As shown, the present invention also provides a method for preparing a heterogeneous integration structure for preparing the heterogeneous integration structure in any of the above embodiments.

[0094] Combined Figures 5a-5f As shown, the method for preparing the heterogeneous integration structure specifically includes:

[0095] S201, providing a substrate 10, the substrate 10 having a first surface and a second surface disposed opposite to each other, the first surface including a first region a and a second region b disposed at intervals. Among them, the first region and the second region are sequentially spaced along the second direction. Among them, the first direction is the longitudinal

[001] crystal direction (i.e., the first direction is perpendicular to the first surface), and the second direction is the <100> crystal direction or the <110> crystal direction perpendicular to the

[001] crystal direction, that is, the second direction is parallel to the first surface and perpendicular to the first direction.

[0096] For the first region a located between two second regions b: the width of the first surface of the first region a in the second direction (i.e., the lateral dimension) is 1 μm to 50 μm. For the second region b located between two first regions a: the width of the first surface of the second region b in the second direction is less than or equal to 1000 nm. It should be noted that Figure 5a Only a part of the substrate is shown, so the width of the first region a or the second region b at the edge of the substrate 10 may not be limited by this.

[0097] It can be understood that the first region a and the second region b can constitute the entire first surface of the substrate 10; or they can constitute a part of the first surface of the substrate 10, that is, the first surface of the substrate 10 can also include other regions, such as a third region or a fourth region, and the present application does not limit this.

[0098] In one embodiment, the substrate 10 is one of a single-crystal silicon substrate or a single-crystal-buried oxide layer composite silicon substrate.

[0099] S202, form a dielectric layer 21 on the first surface. At this time, the dielectric layer 21 covers the first region a and the second region b.

[0100] Refer Figure 5a As shown, the dielectric layer 21 includes one of silicon oxide (SiO2), silicon nitride (SiNx), gallium oxide (Ga2O3), aluminum nitride (AlN), and aluminum oxide (Al2O3). The thickness of the dielectric layer 21 (that is, the dimension of the dielectric layer along the

[001] crystal direction) is 20 nm to 1000 nm.

[0101] S203, remove the dielectric layer 21 on the first surface of the second region b to expose the second region b.

[0102] Refer Figure 5b As shown, using microfabrication processes such as photolithography and etching, remove part of the dielectric layer 21 until the first surface of the substrate 10 is completely exposed. The dielectric layer 21 is grooved along the second direction, the groove width dimension is less than or equal to 1000 nm, and the width of the dielectric layer 21 that is not removed on both sides of the groove is 1 μm to 50 μm.

[0103] At this time, the dielectric layer 21 remains on the first surface of the first region a. The width of the dielectric layer 21 along the second direction on the first region a is 1 μm to 50 μm (that is, the width of the remaining dielectric layer 21 corresponds to the width of the first region a, and the width of the removed dielectric layer 21 corresponds to the width of the second region b).

[0104] S204, form a buffer layer 30 on the dielectric layer 21 and the second region.

[0105] Combined Figure 5c As shown, in a specific embodiment, S204 specifically includes:

[0106] S2041, use a fluorine-containing chemical solution to remove the native oxide on the exposed first surface of the substrate 10, and clean and remove the etching by-products on the surface;

[0107] S2042, using physical or chemical vapor deposition, a single or multiple buffer layer 30 is epitaxially grown on the dielectric layer 21 and the second region. The ratio of the growth rate of the buffer layer 30 along the first direction to the growth rate along the second direction is greater than or equal to 1.5, wherein the first direction is the

[001] crystal orientation, and the second direction is perpendicular to the

[001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

[0108] It is understandable that the lateral growth rate is greater than the longitudinal growth rate, which ensures that the buffer layer compound grows laterally on different dielectric layers and merges to form a continuous film.

[0109] In one specific embodiment, the buffer layer 30 needs to satisfy the following requirements: the crystal structure is diamond or zincblende, the room temperature lattice parameter range is 5.4 Å to 5.7 Å, the doping type of the buffer layer 30 is consistent with the doping type of the substrate 10, and the doping concentration is less than 1E18cm⁻¹. -3 .

[0110] S2043, polish the surface of the buffer layer 30 until the root mean square roughness of the buffer layer 30 surface is less than or equal to 1 nm. Further, thin the buffer layer 30 and polish it to the target thickness, clean the surface of the buffer layer 30 and dry it.

[0111] It is understood that, in this embodiment, the buffer layer 30, after being thinned and polished to the target thickness, can be considered to include a first buffer layer 31 and a second buffer layer 32. The first buffer layer 31 is located on the first surface of the second region, and its thickness is the same as that of the dielectric layer 21. The second buffer layer 32 covers both the dielectric layer 21 and the first buffer layer 31, and its thickness is 10 nm to 10 μm. It should be noted that the distinction between the first buffer layer 31 and the second buffer layer 32 is for ease of differentiation in subsequent steps. In actual fabrication, the first buffer layer 31 and the second buffer layer 32 are grown and fabricated together (i.e., as buffer layer 30).

[0112] S205, a nucleation layer 50 is formed above the buffer layer 30, and the nucleation layer 50 is used as a mask to remove part of the buffer layer 30 to form a photonic crystal layer 40.

[0113] Combination Figure 5d and Figure 5e As shown, in one specific embodiment, S205 specifically includes:

[0114] S2051, a nucleation layer 50 is formed on the buffer layer 30, and the nucleation layer 50 completely covers the surface of the buffer layer 30.

[0115] In a specific embodiment, a nucleation layer 50 with a zinc blende crystal structure is epitaxially grown by physical or chemical vapor deposition. The nucleation layer 50 is a single layer or multiple layers. The nucleation layer 50 film needs to completely cover the surface of the buffer layer 30, and the doping type of the nucleation layer 50 is the same as that of the substrate 10.

[0116] S2052, Remove part of the nucleation layer 50 to expose part of the buffer layer 30 to form a plurality of periodically arranged nucleation units 51.

[0117] In a specific embodiment, periodic nucleation units 51 are fabricated on the nucleation layer 50 film through photolithography and etching processes. It can be understood that, taking the plurality of nucleation units 51 as a mask pattern, the period of the mask pattern is 200 nm to 5 μm, and the duty cycle is 0.1 to 0.9.

[0118] S2053, Using the periodically arranged nucleation units 51 as a mask, remove part of the buffer layer 30 to form the photonic crystal layer 40.

[0119] In a specific embodiment, taking the nucleation layer 50 as a mask, part of the buffer layer 30 is removed by etching to form the photonic crystal layer 40. Among them, the etching selectivity between the nucleation layer 50 and the buffer layer 30 is greater than or equal to 10. The resonant wavelength of the photonic crystal layer 40 is greater than or equal to 800 nm, the etching depth of the second buffer layer 32 is 10 nm to 10 μm, and the sidewall roughness is less than or equal to 10 nm (that is, the roughness of the side surface of the photonic crystal unit 41 is less than or equal to 10 nm).

[0120] In a specific embodiment, the photonic crystal layer 40 has a third surface 401, and the third surface 401 is disposed opposite to the first surface. The photonic crystal unit 41 extends downward from the third surface 401. The thickness of the photonic crystal unit 41 above the first region is less than or equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal unit 41 above the second region is less than or equal to the distance between the third surface 401 and the first surface.

[0121] It can be understood that the etching depth can be set according to requirements. The following is an example in combination with the drawings:

[0122] As shown in Figure 1 In a specific embodiment, the thicknesses of the photonic crystal units 41 above the first region and the photonic crystal units 41 above the second region are both equal to the distance between the third surface 401 and the surface of the dielectric layer 21. That is, the photonic crystal unit 41 extends from the third surface 401 to the plane where the surface of the dielectric layer 21 is located.

[0123] Furthermore, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31 and a photonic crystal structure layer. The first buffer layer 31 is formed on the first surface of the second region. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically on the first buffer layer 31 and above the dielectric layer 21.

[0124] Refer to Figure 2 As shown, in another specific embodiment, the thicknesses of the photonic crystal units 41 above the first region and the photonic crystal units 41 above the second region are both smaller than the distance between the third surface 401 and the surface of the dielectric layer 21. That is, the photonic crystal units 41 extend from the third surface 401 to a plane above the dielectric layer 21.

[0125] Furthermore, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a first buffer layer 31, a second buffer layer 32 and a photonic crystal structure layer. The first buffer layer 31 is formed on the first surface of the second region b. The second buffer layer 32 covers the dielectric layer 21 and the first buffer layer 31. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically above the second buffer layer 32.

[0126] Refer to Figure 3 As shown, in another specific embodiment, the thickness of the photonic crystal unit 41 above the first region is equal to the distance between the third surface 401 and the surface of the dielectric layer 21, and the thickness of the photonic crystal unit 41 above the second region is equal to the distance between the third surface 401 and the first surface. That is, the photonic crystal units 41 extend from the third surface 401 to the surface of the dielectric layer 21 and the first surface of the second region.

[0127] Furthermore, at this time, the photonic crystal layer 40 can be regarded as: the photonic crystal layer 40 includes a photonic crystal structure layer. The photonic crystal structure layer includes a plurality of photonic crystal units 41 arranged periodically on the first surface of the second region and above the dielectric layer 21.

[0128] S206. An epitaxial layer 60 is formed above the nucleation layer 50. The epitaxial layer 60 covers the first surface.

[0129] Refer to Figure 5f As shown, in a specific embodiment, the photonic crystal layer 40 is chemically cleaned and surface-treated, and the epitaxial layer 60 is epitaxially grown on the surface of the nucleation layer 50 by physical or chemical vapor deposition.

[0130] The doping type of the epitaxial layer 60 is the same as that of the substrate 10. The growth rate ratio of the epitaxial layer 60 along the first direction to the growth rate along the second direction is greater than or equal to 2, where the first direction is the

[001] crystal direction, and the second direction is the <100> crystal direction or the <110> crystal direction perpendicular to the

[001] crystal direction.

[0131] It is understandable that the lateral growth rate of epitaxial growth is more than twice the longitudinal growth rate, so that the epitaxial layer 60 grows and merges to form a continuous thin film. The thickness of the epitaxial layer 60 is 100nm~1000nm, and the material of the epitaxial layer 60 is the same as the material of the top layer of the nucleation layer 50.

[0132] The present invention will be further described below with reference to specific embodiments.

[0133] Example 1:

[0134] This embodiment provides a method for preparing a heterogeneous integrated structure, specifically including:

[0135] On an 8-inch N-type Si substrate, a SiO2 layer (dielectric layer) is formed by oxidation along the longitudinal

[001] crystal orientation, wherein the thickness of the SiO2 layer is 600 nm;

[0136] A dielectric mask was fabricated using a deep ultraviolet (DUV) lithography machine and reactive ion etching (RIE) (i.e., removing the dielectric layer on the first surface of the second region to expose the second region). Specifically, openings were etched in the SiO2 layer, with an opening width of 300 nm along the

[110] crystal orientation, and the width of the unetched SiO2 layer (dielectric layer) was 12 μm.

[0137] A Ge thin film (buffer layer) was grown on a dielectric mask along the

[001] crystal orientation using reduced pressure chemical vapor deposition (RPCVD), wherein the concentration of the Ge thin film was 5E17 cm⁻¹. -3 The Ge thin film is N-type doped and has a thickness of 3 μm. The Ge thin film covers both the dielectric mask and the substrate.

[0138] The surface roughness of the Ge thin film was polished to 0.5 nm using chemical mechanical polishing (CMP).

[0139] After chemical cleaning and drying of the Ge thin film surface, surface pretreatment was performed using metal-organic chemical vapor deposition (MOCVD), and a 50 nm thick Ga film was grown. 0.51 In 0.49 P, followed by the growth of a 200 nm thick N-type GaAs layer. That is, the untreated nucleation layer in this embodiment includes a 50 nm thick Ga... 0.51 In 0.49 P and a 200nm thick N-type GaAs layer.

[0140] Periodic mask patterns (i.e., periodically arranged nucleation units based on nucleation layers) are fabricated using stepper lithography and inductively coupled plasma etching (ICP). The opening areas of the periodic mask patterns completely expose the surface of the underlying Ge thin film. The period of the periodic mask patterns is 1 μm and the duty cycle is 0.4 (the opening width is 400 nm in this embodiment).

[0141] Based on a periodic mask pattern, an ICP device was used to etch a 1.2 μm deep Ge thin film with a CF4 / O2 / He gas combination to form a periodic photonic crystal structure (photonic crystal layer) with a resonant wavelength of 2000 nm. The sidewall roughness of the photonic crystal structure was 5 nm. Furthermore, the etching selectivity ratio between the periodic mask pattern formed by the nucleation layer and the buffer layer (i.e., the Ge thin film) was 12 when the ICP device etched the nucleation layer.

[0142] After surface cleaning, an N-type GaAs layer (epitaxy layer) is epitaxially grown on the photonic crystal structure using MOCVD. The lateral growth rate of the N-type GaAs layer is three times the longitudinal growth rate, so that the surface of the N-type GaAs layer merges into a uniform thin film and completely covers the underlying photonic crystal structure, forming a suspended GaAs structure. In this embodiment, the thickness of the N-type GaAs layer is 600 nm.

[0143] This embodiment also provides a heterogeneous integrated structure, which is obtained based on the above-described method for preparing a heterogeneous integrated structure.

[0144] Example 2:

[0145] This embodiment provides a method for preparing a heterogeneous integrated structure, specifically including:

[0146] A 200 nm thick SiN layer was deposited on a 6-inch P-type Si

[001] substrate. X Layer (dielectric layer);

[0147] A dielectric mask is fabricated using deep ultraviolet (DUV) lithography and reactive ion etching (RIE) (i.e., removing the dielectric layer on the first surface of the second region to expose the second region). Specifically, on SiN... X Layer etching creates openings with a width of 300 nm along the

[110] crystal orientation. Unetched SiN X The width of the layer (dielectric layer) is 1.5 μm;

[0148] MOCVD was used to grow a 30 nm thick AlP film and a 500 nm thick P-type GaP film on a dielectric mask along the

[001] crystal orientation. The surface of the GaP film was polished using CMP to achieve a surface roughness of 0.3 nm. That is, the buffer layer in this embodiment is a multilayer structure, including AlP films and GaP films stacked sequentially.

[0149] After chemical cleaning and drying of the GaP thin film surface, MOCVD was used for surface pretreatment and a 150 nm thick InP layer (nucleation layer) was grown.

[0150] A periodic mask pattern with a period of 220 nm and a duty cycle of 0.4 was fabricated using electron beam lithography (EBL) and reactive ion etching (RIE), with the opening area completely exposing the underlying GaP thin film surface.

[0151] Using a periodic InP layer (i.e., periodically arranged nucleation units) as a mask pattern, an ICP device is used to etch a GaP thin film with a BCl3 / Cl2 / N2 gas combination to form a periodic photonic crystal structure (photonic crystal layer) with a resonant wavelength of 900 nm. The sidewall roughness of the photonic crystal structure is 3 nm (i.e., the side surface roughness of the photonic crystal unit is 3 nm). In this embodiment, the etching selectivity ratio of the InP layer and the GaP thin film is 10, and the etching depth of the GaP thin film is 180 nm (i.e., the thickness of the photonic crystal unit in this embodiment is 180 nm).

[0152] After surface cleaning, InP layers were epitaxially grown on periodic InP layers using MOCVD, with the lateral growth rate of the InP layers being twice the longitudinal growth rate. After growing a 1000 nm thick P-type InP layer, the InP layer surface merged into a uniform thin film, completely covering the underlying photonic crystal, forming a suspended InP structure.

[0153] Compared with existing technologies, this invention monolithically integrates compound semiconductors on a silicon substrate. It involves laterally epitaxially growing a crystal structure or a buffer layer with a similar lattice constant on the substrate, planarizing the buffer layer, and then growing a compound semiconductor nucleation layer. Subsequently, a photonic crystal structure with optical functions is fabricated. The epitaxial layer, suspended above the photonic crystal structure, is then formed by laterally growing and merging microcrystal arrays. The heterogeneous integration structure in this invention can utilize large-size silicon substrates, extending the size of the compound semiconductor wafer to over 8 inches.

[0154] Suspended compound semiconductor epitaxial layers can be used to grow higher quality and more complex compound semiconductor thin films on large-size silicon substrates. The photonic crystal layer under the epitaxial layer has special optical functions in the near-infrared band and longer wavelengths, such as high reflection, low reflection, wavelength selectivity and optical waveguide. The nanoscale periodic structure can also be used to relax the thermal mismatch between the substrate and the epitaxial layer and reduce the mechanical deformation of the substrate after epitaxial growth.

[0155] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0156] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A heterogeneous integrated structure, characterized in that, include: The substrate has a first surface and a second surface disposed opposite to each other. The first surface includes a first region and a second region disposed at intervals. The width of the first surface of the second region in a second direction is less than or equal to 1000 nm, and the width of the first surface of the first region in the second direction is 1 μm to 50 μm, wherein the second direction is perpendicular to the [001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation; A dielectric layer is formed on the first surface of the first region; A photonic crystal layer is formed on a first surface of the second region and on the dielectric layer, having a plurality of periodically spaced photonic crystal units. The photonic crystal layer has a third surface, which is disposed opposite to the first surface. The photonic crystal units extend downward from the third surface. The thickness of the photonic crystal units located above the first surface of the first region is less than or equal to the distance between the third surface and the surface of the dielectric layer. The thickness of the photonic crystal units located above the first surface of the second region is less than or equal to the distance between the third surface and the first surface. The nucleation layer includes a plurality of nucleation units located on the surface of the photonic crystal unit; An epitaxial layer is stacked on top of the nucleation layer and covers the first surface.

2. The heterogeneous integrated structure according to claim 1, characterized in that, The nucleation layer comprises a plurality of periodically arranged nucleation units, the arrangement period of which is the same as that of the photonic crystal units, and the duty cycle of the nucleation layer is the same as that of the photonic crystal layer; and / or, The arrangement period of the photonic crystal unit is 200nm~5μm, and the duty cycle of the photonic crystal layer is 0.1~0.

9.

3. The heterogeneous integrated structure according to claim 1, characterized in that, The substrate is a single-crystal silicon substrate or a single-crystal-buried oxide layer composite silicon substrate.

4. The heterogeneous integrated structure according to claim 1, characterized in that, The dielectric layer comprises one of silicon oxide, aluminum oxide, gallium oxide, silicon nitride, and aluminum nitride; and / or, The thickness of the dielectric layer is 20 nm to 1000 nm.

5. The heterogeneous integrated structure according to claim 1, characterized in that, The crystal structure of the photonic crystal layer is a cubic diamond structure or a zincblende structure; and / or, The room-temperature lattice parameters of the photonic crystal layer range from 5.4 Å to 5.7 Å; and / or, The doping concentration of the photonic crystal layer is less than 1E18cm⁻¹ -3 .

6. The heterogeneous integrated structure according to claim 1, characterized in that, The thickness of the photonic crystal unit is 10 nm to 10 μm; and / or, The roughness of the side surface of the photonic crystal unit is less than or equal to 10 nm.

7. The heterogeneous integrated structure according to claim 1, characterized in that, The photonic crystal unit is a single-layer or multi-layer structure; and / or The nucleation layer is a single-layer or multi-layer structure, and the material of the epitaxial layer is the same as the material of the top layer of the nucleation layer; and / or, The nucleation layer has a zincblende crystal structure and a thickness of 10 nm to 300 nm.

8. The heterogeneous integrated structure according to claim 1, characterized in that, The doping types of the photonic crystal layer, nucleation layer, and epitaxial layer are the same as the doping type of the substrate; and / or, The epitaxial layer has a zincblende crystal structure and a thickness of 100 nm to 1000 nm.

9. A method for fabricating a heterogeneous integrated structure, characterized in that, The heterogeneous integrated structure is as described in any one of claims 1 to 8, and the preparation method includes: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals; A dielectric layer is formed on the first surface, the dielectric layer covering the first region and the second region; Remove the dielectric layer on the first surface of the second region to expose the second region; Forming a buffer layer on the dielectric layer and the second region includes: epitaxially growing a single layer or multiple layers of buffer layers on the dielectric layer and the second region, wherein the ratio of the growth rate of the buffer layer along a first direction to the growth rate along a second direction is greater than or equal to 1.5, wherein the first direction is the [001] crystal orientation, and the second direction is perpendicular to the [001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation; A nucleation layer is formed above the buffer layer, and the nucleation layer is used as a mask to remove part of the buffer layer to form a photonic crystal layer; An epitaxial layer is formed above the nucleation layer, and the epitaxial layer covers the first surface.

10. The method for preparing a heterogeneous integrated structure according to claim 9, characterized in that, A nucleation layer is formed above the buffer layer, and the nucleation layer is used as a mask to remove a portion of the buffer layer to form a photonic crystal layer, including: A nucleation layer is formed on the buffer layer, and the nucleation layer covers the buffer layer; Part of the nucleation layer is removed and part of the buffer layer is exposed to form a plurality of periodically arranged nucleation units; Using the periodically arranged nucleation units as a mask, a portion of the buffer layer is removed to form a photonic crystal layer.

11. The method for preparing a heterogeneous integrated structure according to claim 9, characterized in that, A buffer layer is formed on the dielectric layer and the second region, comprising: A single or multiple buffer layer is epitaxially grown on the dielectric layer and the second region using physical or chemical vapor deposition. The ratio of the growth rate of the buffer layer along a first direction to the growth rate along a second direction is greater than or equal to 1.5, wherein the first direction is the [001] crystal orientation, and the second direction is perpendicular to the [001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

12. The method for preparing a heterogeneous integrated structure according to claim 11, characterized in that, After forming a buffer layer on the dielectric layer and the second region, the surface of the buffer layer is polished until the root mean square roughness of the buffer layer surface is less than or equal to 1 nm.

13. The method for preparing a heterogeneous integrated structure according to claim 9, characterized in that, Using the nucleation layer as a mask, a portion of the buffer layer is removed by an etching process to form a photonic crystal layer, wherein the etching selectivity ratio of the nucleation layer to the buffer layer is greater than or equal to 10; and / or, The resonant wavelength of the photonic crystal layer is greater than or equal to 800 nm.

14. The method for preparing a heterogeneous integrated structure according to claim 9, characterized in that, An epitaxial layer is formed above the nucleation layer, the epitaxial layer covering the first surface, including: An epitaxial layer is epitaxially grown on the surface of the nucleation layer using physical or chemical vapor deposition. The doping type of the epitaxial layer is consistent with the doping type of the substrate. The ratio of the growth rate of the epitaxial layer along a first direction to the growth rate along a second direction is greater than or equal to 2, wherein the first direction is the [001] crystal orientation, and the second direction is perpendicular to the [001] crystal orientation. <100> Crystal orientation or <110> Crystal orientation.

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