A test signal verification processing method for a PCBA circuit board

Abstract

The application discloses a test signal verification processing method for a PCBA circuit board, and relates to the technical field of circuit board testing.The test data is obtained by initially testing the PCBA circuit board through test data, the signal path model and the element topology layer of the PCBA circuit board are analyzed, data interaction of the signal path model and the element topology layer is realized, the standard signal of the PCBA circuit board test is obtained by using the signal path model, the fault element is located by comparing the standard signal with the test signal and combining the element topology layer, and a fault diagnosis report is obtained.The application realizes accurate verification of the test signal of the PCBA circuit board by constructing the signal path model and the element topology layer and combining dynamic parameter adjustment of the mapping space, and improves the signal test efficiency and accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board testing, and particularly relates to a test signal verification processing method for a PCBA circuit board. BACKGROUND

[0002] In the manufacturing process of a PCBA (Printed Circuit Board Assembly), testing and quality control of the circuit board are crucial links. Traditional testing methods mainly include flying probe testing, in-circuit testing (ICT), and functional testing. ICT detects electrical connectivity and component parameters through probe contact test points, but its coverage is limited by physical access points, making it difficult to detect signal integrity or high-frequency performance problems. Functional testing can verify overall performance, but it cannot accurately locate faulty components. In addition, existing methods rely on static parameter comparison and lack modeling capability for dynamic signal paths, resulting in low diagnostic efficiency for impedance mismatch abnormalities, timing errors, and other hidden faults.

[0003] At the same time, existing PCBA circuit board test signal verification methods lack systematic modeling, and most solutions only use discrete test point data for threshold judgment, which cannot restore the complete propagation characteristics of signals in the path and is prone to misjudgment. Secondly, fault location relies on experience rules or simple correlation analysis, making it difficult to handle the coupling effect between components in a multi-layer topology structure. For example, power integrity degradation can cause remote component functional abnormalities, and traditional methods are difficult to trace the root cause.

[0004] Therefore, it is of great significance to develop an efficient and intelligent PCBA circuit board test signal verification processing method. SUMMARY

[0005] The present application aims to provide a test signal verification processing method for a PCBA circuit board to solve the problems in the background art.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solution: a test signal verification processing method for a PCBA circuit board, comprising:

[0007] Testing the PCBA circuit board to obtain component parameters and test signals of the PCBA circuit board;

[0008] Constructing a signal path model and a component topology layer, connecting the component topology layer and the components in the signal path model one by one, and verifying the accuracy of the test signals using the signal path model;

[0009] Locating faulty components using the signal path model and the component topology layer and generating a fault diagnosis report.

[0010] In a preferred embodiment, the step of testing the PCBA circuit board to obtain the component parameters and test signals of the PCBA circuit board is:

[0011] extracting the standard parameters of each component of the PBCA circuit board;

[0012] formulating test data for the PCBA circuit board, the test data including input signal types, signal amplitudes, and frequency ranges;

[0013] initially testing the PCBA circuit board using the test data to obtain test signals.

[0014] The step of constructing the signal path model is:

[0015] extracting information of the signal path in the circuit schematic diagram of the PCBA circuit board, including the starting point, the ending point, the components passed through, and the wires;

[0016] converting the signal path into a circuit network, and drawing a signal flow diagram on the circuit network to obtain a signal path model including components, signal paths, and signal flow directions;

[0017] wherein the initial values of the parameters of the components are the standard parameters and are adjustable;

[0018] setting multiple detection windows on the signal path and at both ends of the components, connecting multiple mapping spaces through mapping channels, and storing the signal path model in the mapping spaces.

[0019] In a preferred embodiment, the step of constructing the component topology layer and connecting the component topology layer with the components in the signal path model one-to-one is:

[0020] defining each of the components in the PBCA circuit board as: and constructing an adjacency matrix between the components:

[0021]

[0022] wherein, the adjacency matrix is represented by A, the components are represented by V, and the adjacency relationship is represented by E;

[0023] defining the correlation weights between the components, including electrical connection weights, physical connection weights, and performance connection weights;

[0024] wherein the electrical connection weights are:

[0025]

[0026] wherein, ​representing elements and electrical connection weight, representing current flowing through elements and between, representing equivalent impedance between elements and ;

[0027] physical connection weight:

[0028]

[0029] wherein, representing physical connection weight between elements and , representing and physical distance, is distance attenuation factor;

[0030] performance connection weight:

[0031]

[0032] wherein, representing performance connection weight between elements and , representing performance benchmark of circuit board, representing performance benchmark of elements and respectively;

[0033] then the correlation weight between each element is:

[0034]

[0035] wherein, is adjustable parameter;

[0036] a component topology layer is constructed by adjacency matrix and correlation weight, the component topology layer is composed of components and directed edges connecting components, and the value of the directed edge is the value of the correlation weight between two components;

[0037] the component topology layer is connected with the components in the signal pathway model through data transmission channel one by one.

[0038] In a preferred embodiment, the step of verifying the accuracy of the test signal by using the signal pathway model and the component topology layer is:

[0039] The test data input signal path model obtains the optimal test signal, and the optimal test signal passing through the detection point is taken as a standard signal;

[0040] A preset error threshold is used to compare the test signal with the standard signal of the detection point. If the error value of the test signal of a detection point in the signal path model and the standard signal exceeds the preset error threshold, the detection point is taken as an abnormal point;

[0041] The abnormal point activates a mapping space, the mapping space expands the stored signal path model as a mapping path, the test signal is transmitted to the mapping space, the abnormal point is taken as a starting point of the mapping path, the test signal is taken as an input, and the signal flow direction of the test signal is determined;

[0042] The abnormal information of the abnormal point includes an abnormal signal value, an abnormal point position and a signal path to which the abnormal point belongs. The abnormal information is transmitted to an element topology layer through an element closest to the abnormal point. The element topology layer locates a potential fault element and collects data of the potential fault element;

[0043] The element topology layer transmits the data of the potential fault element to the mapping space through a data transmission channel and a mapping channel. The mapping space adjusts parameters of the potential fault element dynamically so that an output of the mapping path is equivalent to standard data;

[0044] The mapping path and the signal path model run in parallel until all the detection points are compared, a fault element is determined, and a fault diagnosis report is generated.

[0045] In a preferred embodiment, the steps that the element topology layer locates a potential fault element and collects data of the potential fault element include an element ID, an element parameter and an adjustment range.

[0046] A preset correlation value threshold is used. An element connected to the element topology layer and receiving the abnormal information is taken as a potential fault element based on the element topology layer searching for an element whose correlation value exceeds the correlation value threshold.

[0047] In a preferred embodiment, the steps that the mapping space adjusts parameters of the potential fault element dynamically so that an output of the mapping path is equivalent to standard data include:

[0048] The mapping space receives data of the potential fault element and defines a priority calculation formula:

[0049]

[0050] wherein, Pn represents a priority of an nth potential fault element, an output signal error of the mapping path, an output signal error of the mapping path, an output signal error of the mapping path, The error between the output signal of a potentially faulty component and the standard signal. The larger the value, the higher the priority of modifying the potentially faulty component; the modification order table is determined based on the priority.

[0051] Design the objective function:

[0052]

[0053] The optimization objective is defined as follows: F is the objective function, T is the test signal, and C is the standard signal. For the first The adjusted parameter values ​​for each potentially faulty component For the first Standard parameters for a potentially faulty component The regularization coefficient is used.

[0054] The objective function is optimized by minimizing the least squares method.

[0055] A preset output error threshold is set, and the parameters of the highest priority potential faulty components are adjusted. If the error threshold is not reached, the next priority potential faulty components are adjusted in turn, and the operation is iterated until all potential faulty components have been adjusted.

[0056] In a preferred embodiment, the step of identifying the faulty component and generating a fault diagnosis report is as follows:

[0057] After the iteration operation is complete, define the parameter adjustment value:

[0058]

[0059] in, For the first The parameter adjustment values ​​of each potential faulty component are set, and a preset parameter adjustment threshold is set. Potential faulty components whose parameter adjustments exceed the parameter adjustment threshold are identified as faulty components.

[0060] The fault information and abnormal information of the faulty component are summarized into a fault diagnosis report, in which the fault information includes the component ID and parameter adjustment value.

[0061] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0062] 1、The application realizes full-link simulation and dynamic verification of PCBA test signals by constructing a high-precision signal channel model and a multi-level mapping space, the traditional method relies on the comparison of static parameters of discrete test points, and cannot capture the propagation characteristics of signals in complex channels such as reflection, crosstalk, timing offset, etc., while the scheme sets multiple detection windows on the signal channel, compares the test signals and standard signals in the mapping space through the mapping channel, forms a closed-loop mechanism of'signal propagation path-exception point mapping-dynamic parameter correction', and the mapping channel and the signal channel model run in parallel, improving the detection efficiency;

[0063] 2、The application realizes quantitative analysis and accurate positioning of the coupling effect between PCBA elements by constructing an element topology layer that fuses electrical, physical and performance weights, the scheme realizes quantitative analysis and accurate positioning of the coupling effect between PCBA elements, the traditional adjacency matrix only describes the physical connection relationship of the elements, while the scheme introduces a three-dimensional correlation model of electrical connection weight based on current-impedance relationship, physical connection weight based on distance attenuation factor and performance connection weight based on function dependence, and constructs a topology network closer to the actual circuit behavior, and the element topology layer and the signal channel model interact in real time, introduce a dynamic parameter adjustment strategy and a priority mechanism, and significantly improve the positioning efficiency and repair accuracy of the faulty elements. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows, obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0065] Figure 1 The method flowchart of the present application. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the technical scheme in the embodiments of the present application will be described clearly and completely in conjunction with the drawings in the embodiments of the present application, obviously, the described embodiments are some embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0067] Embodiment 1, please refer to Figure 1 The test signal verification processing method for the PCBA circuit board described in this embodiment comprises:

[0068] S1, test the PCBA circuit board to obtain the element parameters and test signals of the PCBA circuit board;

[0069] S2, a signal path model and an element topology layer are constructed, the element topology layer is connected with the elements in the signal path model in one-to-one, and the accuracy of the test signal is verified by using the signal path model;

[0070] S3, the fault element is located by using the signal path model and the element topology layer, and a fault diagnosis report is generated.

[0071] As described in the above steps S1-S3, in the PCBA manufacturing process, the test and quality control of the circuit board are crucial links, and the traditional test methods mainly include flying probe test, in-circuit test (ICT), function test, etc. The in-circuit test detects electrical connectivity and element parameters by probe contact test points, but its coverage is limited by physical access points, and it is difficult to detect signal integrity or high-frequency performance problems. Although the function test can verify the overall performance, it cannot accurately locate the fault element. In addition, the existing methods mostly rely on static parameter comparison, lack of modeling ability for dynamic signal path, resulting in low diagnosis efficiency for hidden faults such as impedance matching abnormality and timing error.

[0072] At the same time, the existing PCBA circuit board test signal verification method lacks systematic modeling, most of the schemes only make threshold judgment through discrete test point data, and cannot restore the complete propagation characteristics of the signal in the path, which is easy to cause misjudgment. Secondly, the fault location depends on experience rules or simple correlation analysis, and it is difficult to handle the coupling effect between elements in the multi-level topology structure, for example, power integrity degradation may cause remote element function abnormality, and the traditional method is difficult to trace the root cause.

[0073] The present application realizes the full-link simulation and dynamic verification of the PCBA test signal by constructing a high-precision signal path model and a multi-level mapping space. The traditional method relies on the static parameter comparison of discrete test points, and cannot capture the propagation characteristics of the signal in the complex path, such as reflection, crosstalk, timing offset, etc. The present application sets multiple detection windows on the signal path, compares the test signal and the standard signal in the mapping space through the mapping channel, forms a closed-loop mechanism of "signal propagation path- abnormal point mapping-dynamic parameter correction", and runs the mapping path and the signal path model in parallel, improving the detection efficiency.

[0074] By constructing the element topology layer of fusing electrical, physical and performance weights, the scheme realizes the quantitative analysis and accurate positioning of the coupling effect between PCBA elements. The traditional adjacency matrix only describes the physical connection relationship of the elements, while the scheme introduces a three-dimensional correlation model based on the electrical connection weight of current-impedance relationship, the physical connection weight based on distance attenuation factor, and the performance connection weight based on function dependency, constructs a topology network closer to the actual circuit behavior, and the element topology layer and the signal path model interact in real time, introduces a dynamic parameter adjustment strategy and priority mechanism, which significantly improves the positioning efficiency and repair accuracy of the faulty element.

[0075] In one embodiment, the step S1 of testing the PCBA circuit board to obtain the element parameters and test signals of the PCBA circuit board comprises:

[0076] S11, extracting the standard parameters of each element of the PBCA circuit board;

[0077] S12, formulating test data for the PCBA circuit board, the test data including input signal type, signal amplitude and frequency range;

[0078] S13, using the test data to perform initial testing on the PCBA circuit board to obtain test signals;

[0079] As described in steps S11-S13 above, use automatic test equipment (ATE) or manual detection to identify the elements on the PCBA circuit board. For each identified element, obtain its standard electrical parameters from the data manual, including voltage level, current level, resistance, capacitance, and frequency response curve, etc. In actual implementation, a database can be constructed to integrate these parameters into a database for subsequent query and use. Define test data to determine the required input signal mode including analog and digital signals. A signal generator can be designed to generate the required type of signal. According to the rated parameters of the circuit, set different input signal amplitude ranges including low amplitude test, rated amplitude test and overload amplitude test. According to the circuit function, set the test frequency range including low frequency test, medium frequency test and high frequency test. Test the PCBA circuit board using the test data to obtain the feedback signals of each detection point and output port on the PCBA circuit board as test signals.

[0080] In one embodiment, the step S2 of constructing a signal path model comprises:

[0081] S21, extracting information of the signal path in the circuit schematic diagram of the PCBA circuit board, including the starting point, ending point, passing elements and wires of the signal;

[0082] S22, converting the signal path into a circuit network, drawing a signal flow graph on the circuit network to obtain a signal path model including elements, signal paths, and signal flow directions;

[0083] S23, wherein the initial value of the parameter of the element is a standard parameter and is adjustable;

[0084] S24, a plurality of detection windows are arranged on the signal path and at both ends of the element, the plurality of detection windows are connected to a plurality of mapping spaces through a mapping channel, and the mapping spaces store the signal path model;

[0085] As described in steps S23-S24 above, open the circuit schematic of the PCBA using circuit design software such as Altium Designer or Cadence, use the automatic tools of the software to extract the information of the signal path in the circuit, including the signal starting point: determine the source of the power supply, input terminal or control signal, signal end point: identify the final output terminal or load or control interface, element list: list all elements participating in signal transmission, including resistors, capacitors, diodes, integrated circuits, etc., wire information: identify the propagation path of the signal in the circuit, record the connection relationship, impedance and length of the wire, etc. Information, organize the extracted information in a structured way to form a basic data model of the signal path, including elements and their connection relationship, convert the extracted signal path information into a circuit network model, where each element is a node in the network, and the signal wire is the edge connecting these nodes. At the same time, determine the flow direction of the signal, construct the signal path model based on the circuit network model and the signal flow, set the initial value of the parameter of each element on the signal path model to its standard parameter, which usually comes from the technical data manual of the element. At the same time, set the parameter adjustment mechanism, the parameters of the elements can be adjusted adaptively based on the test environment during the test, and in the signal path model, a plurality of detection windows are set to specify the key points of the monitored signal, such as input point detection for monitoring the quality of the input signal to ensure that the signal reaches as designed, intermediate node detection for monitoring the change of the signal between key elements such as buffers, amplifiers, etc., and output point detection for checking the signal amplitude, current and timing at the output terminal. In actual situations, the complexity of the PCBA circuit board is dynamically increased or decreased, and the more complex the circuit is, the more detection windows should be set, each detection window is connected to a mapping space through a mapping channel, and the mapping space is a data processing center with edge computing capability, which stores the mapping of the signal path model. When receiving an activation request, it will expand the signal path model stored in it as a mapping path for signal simulation operation.

[0086] In one embodiment, the step S2 of constructing an element topology layer and connecting the element topology layer with the elements in the signal path model one by one includes:

[0087] S25, The PBCA circuit board in Each component is defined as follows: And construct the adjacency matrix between each element:

[0088]

[0089] S26, where, Represents the adjacency matrix. Indicator element and Adjacency relationship;

[0090] S27. Define the association weights between components, including electrical connection weights, physical connection weights, and performance connection weights;

[0091] S28, where electrical connection weights are:

[0092]

[0093] S29, among which, Indicator element and Electrical connection weights, Indicates the flow through the element and The current between, Indicator element and The equivalent impedance between;

[0094] S210, Physical Connection Weights:

[0095]

[0096] S211, where, Indicator element and Physical connection weights between them express and physical distance, It is the distance decay factor;

[0097] S212, Performance Connection Weights:

[0098]

[0099] S213, where, Indicator element and The performance connection weights between them Indicates the performance benchmark of the circuit board. Representing components and performance benchmark of the performance of the PCBA circuit board;

[0100] S214, the correlation weight between each element is:

[0101]

[0102] S215, wherein, is an adjustable parameter;

[0103] S216, a component topology layer is constructed by the adjacency matrix and the correlation weight, the component topology layer is composed of components and directed edges connecting the components, and the value of the directed edge is the value of the correlation weight between the two components;

[0104] S217, the component topology layer is connected with the components in the signal path model through the data transmission channel one by one;

[0105] As described in steps S25-S217, each element on the PCBA circuit board is identified as wherein indicates the unique index, determines the function, type and its role in the circuit of each element, so as to facilitate subsequent modeling, constructing an adjacency matrix to represent the connection relationship between elements, and 0 is used for those not directly connected. In actual implementation, the initial connection relationship can be replaced by electrical connection weight or directly defined as 1. At the same time, the connection weight between each element is constructed, including electrical connection weight, physical connection weight and performance connection weight. The electrical connection weight reflects the electrical connection characteristics between two elements in the circuit, which is mainly measured by the impedance between elements and the current flowing through. The physical connection weight reflects the physical distance between two elements in the circuit and the influence of such distance on signal transmission. The performance connection weight measures the relationship between two elements in terms of circuit performance benchmarks such as power and stability. In actual implementation, more comprehensive situations can be considered, including adding thermal coupling weight to reflect the degree of thermal influence between two elements in the circuit, which is usually evaluated by the thermal conductivity coefficient between elements, physical distance and their respective thermal characteristics. Further, impedance matching weight and electromagnetic interference weight can be added to perfect the relationship between elements on the circuit board. Based on the calculated element association weight, various association weights are integrated by designing adjustable parameters, which allow designers to adjust the importance of weight according to circuit requirements. For example, in high-frequency digital signal circuits, electrical connection weight may be given higher weight as a key factor. Designers can increase the weight of electrical connection weight to ensure minimal signal reflection and distortion in signal transmission. Based on the constructed adjacency matrix and association weight, an element topology layer is constructed to present the directed edges between elements and connected elements, and the value of the directed edge is the value of the association weight. Transmission ports are provided on the elements so that elements can realize real-time data interaction with corresponding elements in the signal path model through data transmission channels. The element topology layer and the elements in the signal path model are connected one by one through the transmission ports and data transmission channels to realize data interaction between the element topology layer and the signal path model.

[0106] In one embodiment, the step S2 of verifying the accuracy of the test signal by using the signal path model and the element topology layer comprises:

[0107] S218, inputting test data into the signal path model to obtain an optimal test signal, and taking the optimal test signal passing through the detection point as a standard signal;

[0108] S219, presetting an error threshold, comparing the test signal with the standard signal of the detection point, and if the error value of the test signal of a detection point in the signal path model exceeds the preset error threshold, the detection point is taken as an abnormal point;

[0109] S2110, the abnormal point activates the mapping space, the mapping space expands the stored signal path model as a mapping path, transmits the test signal to the mapping space, takes the mapping abnormal point as the starting point of the mapping path, takes the test signal as the input, and determines the signal flow direction of the test signal;

[0110] S2111, record the abnormal information of the abnormal point, including the abnormal signal value, the abnormal point position and the signal path to which it belongs, transmit the abnormal information to the element topology layer through the element closest to the abnormal point, locate the potential fault element and collect the data of the potential fault element in the element topology layer;

[0111] S2112, the element topology layer transmits the data of the potential fault element to the mapping space through the data transmission channel and the mapping channel, and the mapping space adjusts the parameters of the potential fault element dynamically to make the output of the mapping path equivalent to the standard data;

[0112] S2113, the mapping path and the signal path model run in parallel until all the detection points are compared, the fault element is determined, and the fault diagnosis report is generated;

[0113] As described above in steps S218-S2113, the test data is transmitted as input into the signal path model, the optimal test signal of the PCBA circuit board is obtained by using the signal path model, and the optimal test data is taken as the standard data for comparison with the test signal to judge the fault in a large range. The specific process includes setting an error threshold, comparing the error of the test signal and the standard signal by using the detection window on the signal path model, taking the detection point with error exceeding the error threshold as an abnormal point, collecting the abnormal information of the abnormal point including the abnormal signal value, the abnormal point position and the signal path to which it belongs, and activating the mapping space by the abnormal point. The mapping space expands the signal path model stored therein as a mapping path, takes the test signal of the detection point as input, takes the mapping of the detection point on the mapping path as the starting point, determines the signal flow direction, makes the test signal run in the mapping path, and compares the test signal and the standard signal in the signal path model at the same time. At the same time, the abnormal point transmits the abnormal information to the corresponding element of the element topology layer through the element closest to it, the element obtaining the abnormal information retrieves the potential fault element through its topological properties, collects the data of the potential fault element, transmits the data to the mapping space through the data transmission channel and the mapping channel, and adjusts the parameters of the potential fault element dynamically after obtaining the data of the potential fault element. The mapping space makes the output of the mapping path equivalent to the standard data, i.e. changes the element that may have a fault to make the output of the circuit board accurate. Through the parallel running of the mapping path and the signal path model and the interaction with the element topology layer, the comparison of all test data and standard data is completed, the fault element is determined, and the fault diagnosis report is generated.

[0114] In one embodiment, the step S2111 of locating potentially faulty components and collecting data on these components, including component ID, component parameters, and adjustment range, in the component topology layer includes:

[0115] S21111: A preset correlation value threshold is set. When a component receives an abnormal information, it searches for components connected to it with correlation values ​​that exceed the correlation value threshold based on the component topology layer, and identifies them as potential faulty components.

[0116] S21112. Record data of potentially faulty components, including component ID, component parameters, and adjustment range;

[0117] As described in steps S21111-S21112 above, the component topology layer presents the connection relationships and association degrees between components. A preset association threshold is set. When a component receives abnormal information transmitted from the nearest component of the abnormal point, the component is taken as the root node, and the components connected to it are retrieved. Components whose edge values ​​exceed the association threshold are regarded as potential faulty components. For potential faulty components, it is necessary to collect their data, including component ID, component parameters, and adjustment range, and transmit the data to the mapping space as the target component for parameter adjustment.

[0118] In one embodiment, step S2112, in which the mapping space dynamically adjusts the parameters of potentially faulty components to make the output of the mapping path equivalent to standard data, includes:

[0119] S21121. The mapping space receives data from potentially faulty components and defines a priority calculation formula:

[0120]

[0121] S21122, where, Indicates the first Prioritizing potentially faulty components For the output signal error of the mapping path, For the first The error between the output signal of a potentially faulty component and the standard signal. The larger the value, the higher the priority of modifying the potentially faulty component; the modification order table is determined based on the priority.

[0122] S21123. Design the objective function:

[0123]

[0124] S21124, as the optimization objective, where F is the objective function, T is the test signal, and C is the standard signal. For the first The adjusted parameter values ​​for each potentially faulty component For the first a standard parameter of the potential fault element, is a regularization coefficient;

[0125] S21125, using the least square method to minimize the optimization of the objective function;

[0126] S21121, preset the output error threshold, adjust the parameter of the potential fault element with the highest priority, if the error threshold is not reached, adjust the potential fault element with the next priority in turn, and iterate until all potential fault elements have been adjusted;

[0127] As described in steps S21121-S21121 above, the mapping space receives the data of the potential fault element sent by the element topology layer of the mapping space, and calculates the ratio of the output signal error of the mapping path and the error of the potential fault element output signal and the standard signal. The ratio is used as the priority of the potential fault element modification. The larger the ratio, the higher the priority of the modification. According to the size of the ratio, the modification order table is obtained, and the objective function is set as the target of adjusting the potential fault element. The optimization goal is to make the output of the mapping path equivalent to the standard signal. The least square algorithm is used to optimize the objective function. The steps are to set the output error threshold, adjust the parameters of the potential fault elements in the objective function based on the priority order table, and the iteration ends when all potential fault elements have been adjusted. The adjustment value of the potential fault element parameter is recorded.

[0128] In one embodiment, the step S3 of determining the fault element and generating the fault diagnosis report comprises:

[0129] After the iteration operation is completed, the parameter adjustment value is defined:

[0130]

[0131] wherein, is the parameter adjustment value of the i-th potential fault element, and the preset parameter adjustment threshold is the parameter adjustment value of the potential fault element that exceeds the parameter adjustment threshold as the fault element. The fault information and abnormal information of the fault element are summarized as a fault diagnosis report, wherein the fault information includes the element ID and the parameter adjustment value.

[0132]

[0133] ​After the iteration operation is completed, the definition function calculates the adjustment value of the potential fault element parameter, judges whether the potential fault element is a fault element by a preset parameter adjustment threshold value, and defines the potential fault element with an adjustment value exceeding the adjustment value threshold value as a fault element. The preset parameter adjustment threshold value can be set as a dynamic threshold value according to the running state of the circuit board or other related factors. For example, in the state that the load of the circuit board is high, the threshold value can be appropriately increased to reduce the false alarm rate; and in the state that the load of the circuit board is low, the threshold value can be appropriately reduced to improve the fault detection sensitivity.

[0134] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A test signal verification processing method for a PCBA circuit board, characterized by, The method comprises the following steps: testing the PCBA circuit board to obtain element parameters and test signals of the PCBA circuit board; constructing a signal path model and an element topology layer, connecting the element topology layer and elements in the signal path model one by one, and verifying the accuracy of the test signals by using the signal path model; locating a faulty element by using the signal path model and the element topology layer and generating a fault diagnosis report; the step of testing the PCBA circuit board to obtain element parameters and test signals of the PCBA circuit board comprises the following steps: extracting standard parameters of each element of the PBCA circuit board; formulating test data corresponding to the PCBA circuit board, the test data including input signal types, signal amplitudes and frequency ranges; performing initial testing on the PCBA circuit board by using the test data to obtain test signals; the step of constructing the signal path model comprises the following steps: extracting information of the signal path in the circuit schematic diagram of the PCBA circuit board, the information including starting points, ending points, elements and conductors passed by the signal; converting the signal path into a circuit network, drawing a signal flow diagram on the circuit network to obtain a signal path model, the signal path model including elements, signal paths and signal flow directions; wherein the initial values of the parameters of the elements are the standard parameters and can be adjusted; in the signal path model, a plurality of detection windows are set, and key points of the monitored signals are designated, including input point detection for monitoring the quality of the input signals, ensuring that the signals arrive as designed, intermediate node detection for monitoring the changes of the signals between key elements, and output point detection for checking the signal amplitudes, currents and timing at the output end; each detection window is connected to a mapping space through a mapping channel, the mapping space being a data processing center with edge computing capability, and the mapping space storing the mapping of the signal path model.

2. The test signal verification processing method for a PCBA circuit board according to claim 1, wherein The step of constructing the element topology layer and connecting the element topology layer and elements in the signal path model one by one comprises the following steps: In the PBCA circuit board Each component is defined as follows: And construct the adjacency matrix between each element: ； wherein denotes an adjacency matrix, denotes an element and adjacency relationship; defining the correlation weights between elements, including electrical connection weights, physical connection weights and performance connection weights; wherein the electrical connection weight is: ； wherein, the electrical connection weight of the element and , the equivalent impedance between the elements and , the current flowing between the elements and ; the physical connection weight is: ； wherein, represents the physical connection weight between elements and , represents and the physical distance, N is the distance attenuation factor; the performance connection weight is: ； wherein, represents a performance connection weight between elements and represents a performance reference of a circuit board, respectively represent performance references of elements and ​​ then the correlation weight between elements is: ； wherein is an adjustable parameter; the element topology layer is constructed by using an adjacency matrix and the correlation weight, the element topology layer being composed of elements and directed edges connecting the elements, and the value of the directed edge being the value of the correlation weight between the two elements; the element topology layer and the elements in the signal path model are connected one by one through a data transmission channel.

3. The test signal verification processing method for a PCBA circuit board according to claim 2, wherein, The step of locating a faulty element by using the signal path model and the element topology layer and generating a fault diagnosis report comprises the following steps: inputting the test data into the signal path model to obtain optimal test signals, and taking the optimal test signals passing through the detection points as standard signals; presetting an error threshold, comparing the test signals with the standard signals at the detection points, and taking a detection point as an abnormal point if the error value of the test signal of the detection point in the signal path model exceeds the preset error threshold; activating the mapping space by the abnormal point, expanding the stored signal path model as a mapping path by the mapping space, transmitting the test signals to the mapping space, taking the mapping abnormal point as the starting point of the mapping path, taking the test signals as the input, and determining the signal flow direction of the test signals; The abnormal information of the abnormal point is recorded, the abnormal information includes abnormal signal value, abnormal point position and belonging signal path, the abnormal information is transmitted to the element topology layer through the element closest to the abnormal point, the element topology layer locates the potential fault element and collects data of the potential fault element; The element topology layer transmits the data of the potential fault element to the mapping space through the data transmission channel and the mapping channel, and the mapping space adjusts the parameters of the potential fault element dynamically to make the output of the mapping path equivalent to the standard data; The mapping path and the signal path model run in parallel until all detection points are compared, the fault element is determined, and a fault diagnosis report is generated.

4. The test signal verification processing method for a PCBA circuit board according to claim 3, wherein, The step of locating the potential fault element and collecting data of the potential fault element by the element topology layer is: A correlation value threshold is preset, and the element receiving the abnormal information locates the element whose correlation value connected to the element exceeds the correlation value threshold as the potential fault element based on the element topology layer, and the data of the potential fault element includes element ID, element parameter and adjustment range; The data of the potential fault element includes element ID, element parameter and adjustment range.

5. The test signal verification processing method for a PCBA circuit board according to claim 4, wherein, The step of the mapping space adjusting the parameters of the potential fault element dynamically to make the output of the mapping path equivalent to the standard data is: The mapping space receives the data of the potential fault element, and defines a priority calculation formula: ； wherein, represents a priority of the potential faulty element, is an output signal error of the mapping path, is an error of the output signal of the potential faulty element and the standard signal, the greater the value of the potential faulty element modification priority is, and a modification order table is determined based on the priority. Design a target function: ； as an optimization target, wherein is a target function, is a test signal, is a standard signal, is an adjusted parameter value of the potential faulty element, is a standard parameter of the potential faulty element, is a regularization coefficient; Use the least square method to minimize the optimization of the target function; A preset output error threshold is set, the parameter of the potential fault element with the highest priority is adjusted, if the preset output error threshold is not reached, the next potential fault element with the next priority is adjusted, and the iteration operation is performed until all potential fault elements are adjusted.

6. The test signal verification processing method for a PCBA circuit board according to claim 5, wherein, The step of determining the fault element and generating the fault diagnosis report is: After the iteration operation is completed, the parameter adjustment value is defined: ； in, For the first The parameter adjustment values ​​of each potential faulty component are set, and a preset parameter adjustment threshold is set. Potential faulty components whose parameter adjustments exceed the parameter adjustment threshold are identified as faulty components. The fault information and the abnormal information of the fault element are summarized as a fault diagnosis report, wherein the fault information includes element ID and parameter adjustment value.

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