A method, system and program product for latency testing of interconnected chips

Abstract

The application provides a kind of interconnection chip-oriented latency test method, system and program product, the method includes: the first test signal is collected to obtain original signal;Second test signal is collected through the chip under test, and delay signal is obtained;First test signal and second test signal are associated periodic binary sequence;The period of periodic binary sequence is greater than the latency of chip under test;First intercept signal in preset time range is intercepted from original signal, and second intercept signal in preset time range is intercepted from delay signal;The time length of preset time range is not less than the period of periodic binary sequence;First intercept signal or second intercept signal is cyclically shifted towards the set direction, and the target shift bit number corresponding to the coincidence of first intercept signal and second intercept signal is recorded;The latency of chip under test is determined according to target shift bit number.The application can improve the accuracy of chip latency test.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a latency test method, system and program product for interconnected chips. BACKGROUND

[0002] With the emergence and development of new technologies such as AI and large models, there is a strong demand for large computing power and large bandwidth. The improvement of server single machine computing power also requires higher data exchange rate between machines, and the data exchange latency has become an important indicator affecting system performance.

[0003] How to evaluate and measure the accurate data exchange latency at the initial stage of interconnected chip design and optimize to reduce the latency has become a key to improve product competitiveness.

[0004] A existing solution records the sending and receiving time of the message through the computer, and calculates the difference between the sending time and the receiving time to obtain the latency performance of the module. However, testing latency through messages will be affected by the computer itself latency and message analysis time, and the accuracy of the result is low.

[0005] A existing solution is to send a square wave with a period of f to the to-be-tested link and the internal link (basically no latency) at the same time, record the period difference n between the arrival of the two square waves, and obtain the latency of the to-be-tested link as t=n / f. However, testing through square waves can only be used for passive link testing. Currently, the receiving end of high-speed interconnected chips has a CDR (Clock and Data Recovery) module, and a square wave or pulse signal with a short period cannot be used for latency testing of such chips. In addition, the communication rate of current high-speed interconnected chips is getting higher and higher, and the receiving end has equalization capability to compensate for the loss of the transmission link; the receiving end will start to perform equalization and establish a connection when the receiving end signal is from nothing to something; using the above square wave form for testing will also include the time of the receiving end equalization and connection establishment process, which is not the accurate latency of the chip link to the signal.

[0006] A solution in the prior art is that after a to-be-tested module inputs to-be-tested data, a test signal of the to-be-tested module is output to a data comparator and compared with a set expected value, i.e. another test signal is compared, when the data comparator outputs a target signal, a counter counting bit is obtained, and a time delay is calculated through the counting bit and a time delay of each unit. However, this solution requires that the two signals to be calculated are the same digital signals, and in a real application scenario, the signals of two sending ends of a chip cannot be guaranteed to be completely the same, so this solution is only applicable to internal digital circuits of a chip and is not applicable to real analog scenarios. In addition, this solution triggers the calculation of the time delay when the alignment of the two signals is determined to be out of alignment, which leads to a short measurable time delay, and the total time delay of the to-be-tested module can only be within a unit time interval. SUMMARY

[0007] A first object of the present application is to provide a time delay test method for interconnected chips to solve the problem that the existing time delay test method is not accurate enough and the scene is limited.

[0008] A second object of the present application is to provide a system for implementing the time delay test method for interconnected chips.

[0009] A third object of the present application is to provide a computer program product for implementing the time delay test method for interconnected chips.

[0010] In order to achieve the first object, the present application provides a time delay test method for interconnected chips, which comprises the following steps: collecting a first test signal to obtain an original signal; collecting a second test signal passing through a to-be-tested chip to obtain a time delay signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the time delay of the to-be-tested chip; a first intercepted signal in a preset time range is intercepted from the original signal, and a second intercepted signal in the preset time range is intercepted from the time delay signal; the time length of the preset time range is not less than the period of the periodic binary sequence; the first intercepted signal or the second intercepted signal is cyclically shifted towards a set direction, and the target shift bit number corresponding to the coincidence of the first intercepted signal and the second intercepted signal is recorded; and the time delay of the to-be-tested chip is determined according to the target shift bit number.

[0011] From the above scheme, it can be seen that the application can directly quantify the time delay of the internal link of the measured chip to the signal, is not disturbed by the message processing time delay or the computer processing time delay, and the measured time delay data is close to the real situation of the chip; the application simulates the real signal flip through the periodic binary sequence, so that for the interconnected chip, especially the high-speed interconnected chip with the function of CDR, the working state of the measured chip during the measurement of the time delay is consistent with the actual use. The application has no requirement for the signal being analog or digital, and even if the amplitudes of the two signals are different (for example, one signal is 1V and the other is 3V), the application can also normally complete the signal alignment and time delay analysis, has a wider coverage, and the result is stable, and can be applied to real simulation scenarios.

[0012] Further, the first test signal and the second test signal are the same or inverse signals; when the first test signal and the second test signal are inverse, the original signal is obtained by collecting the first test signal and performing polarity inversion, or the time delay signal is obtained by collecting the second test signal passing through the measured chip and performing polarity inversion; the time delay of the measured chip is obtained by multiplying the target shift bit number and the sampling point interval.

[0013] As can be seen, when the first test signal and the second test signal are the same or inverse, the sampling point interval can be determined according to the sampling rate of the original signal and the time delay signal, and then the time delay of the measured chip is directly determined by multiplying the sampling point interval and the target shift bit number.

[0014] Further, the first test signal and the second test signal are the same signals with a set time delay, or signals with different positions in a period.

[0015] As can be seen, for the first test signal and the second test signal with a specific relationship, the time delay of the measured chip can be determined after the target shift bit number is determined and the specific relationship is determined. For example, the first test signal and the second test signal are set to be emitted with a set time delay, so that there is a set time delay when collecting, and then the time delay of the measured chip is obtained by adding or subtracting the set time delay after the current time delay is calculated according to the target shift bit number; for example, the signals with different positions in a period, the specific position can be ignored when the first intercepted signal and the second intercepted signal are overlapped by cyclic shift to determine the target shift bit number.

[0016] Further, before collecting the original signal and the time delay signal, a preset time is waited for the measured chip to complete the establishment of the link.

[0017] As can be seen, accurate time delay test results can be obtained.

[0018] Further, the first intercepted signal or the second intercepted signal is circularly shifted in a set direction, and the target shift bit number when the first intercepted signal and the second intercepted signal coincide is recorded, including: initializing the count value as 0; repeatedly executing the following steps until the count value is not less than the difference between the bit number of the first intercepted signal and 1: circularly shifting the first intercepted signal to the left or to the right by the same bit number as the count value to obtain a first shifted signal; calculating the product of the values of the first intercepted signal and the first shifted signal at the same position, and summing the products of all positions to obtain a correlation coefficient; adding 1 to the count value; when the count value is not less than the difference between the bit number of the first intercepted signal and 1, determining the target shift bit number according to the shift bit number of the first intercepted signal corresponding to the maximum correlation coefficient.

[0019] Therefore, the first intercepted signal can be circularly shifted to the left or to the right to coincide with the first intercepted signal, and the time delay can be calculated based on the corresponding left circular shift bit number or right circular shift bit number.

[0020] Further, the first intercepted signal or the second intercepted signal is circularly shifted in a set direction, and the target shift bit number when the first intercepted signal and the second intercepted signal coincide is recorded, including: initializing the count value as 0; repeatedly executing the following steps until the count value is not less than the difference between the bit number of the first intercepted signal and 1: circularly shifting the first intercepted signal to the left or to the right by the same bit number as the count value to obtain a first shifted signal; calculating the product of the values of the first intercepted signal and the first shifted signal at the same position, and summing the products of all positions to obtain a correlation coefficient; adding 1 to the count value; when the count value is not less than the difference between the bit number of the first intercepted signal and 1, determining the target shift bit number according to the shift bit number of the first intercepted signal corresponding to the maximum correlation coefficient.

[0021] Therefore, the first intercepted signal can be circularly shifted to the left or to the right to coincide with the first intercepted signal, and the time delay can be calculated based on the corresponding left circular shift bit number or right circular shift bit number.

[0022] Further, the first intercepted signal or the second intercepted signal is circularly shifted in a set direction, and the target shift bit number when the first intercepted signal and the second intercepted signal coincide is recorded, including: initializing the count value as 0; repeatedly executing the following steps until the count value is not less than the difference between the bit number of the first intercepted signal and 1: circularly shifting the first intercepted signal to the left or to the right by the same bit number as the count value to obtain a first shifted signal; calculating the product of the values of the first intercepted signal and the first shifted signal at the same position, and summing the products of all positions to obtain a correlation coefficient; adding 1 to the count value; when the count value is not less than the difference between the bit number of the first intercepted signal and 1, determining the target shift bit number according to the shift bit number of the first intercepted signal corresponding to the maximum correlation coefficient.

[0023] Therefore, the application can determine the target shift number by judging whether the current correlation coefficient is equal to the maximum correlation coefficient, reduce the shift number, and improve the efficiency of the time delay test.

[0024] Further, the code type corresponding to the first test signal and the second test signal is a PRBS code type.

[0025] Therefore, by using the PRBS code type, the application can approach the data code stream under the real working scene of the chip, the time delay information obtained by the test is more real, and the chip receiving end equalization function does not interfere.

[0026] In order to achieve the second purpose, the application provides a time delay test system for interconnected chips, which comprises a signal generation module, a signal acquisition module and a time delay analysis module.

[0027] Therefore, the application can improve the accuracy of the time delay test of the measured chip, and can adjust the sampling point interval by setting the sampling rate of the signal sampling module, so as to facilitate the adjustment of different time delay test precisions.

[0028] In order to achieve the third purpose, the application provides a computer program product comprising computer instructions, wherein the computer instructions are executed by a processor to realize the time delay test method for interconnected chips. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is the system framework diagram of the time delay test system in the first embodiment of the application.

[0030] Figure 2 is the flowchart of the first embodiment of the application.

[0031] Figure 3 is Figure 2The detailed flow chart of step S15.

[0032] Figure 4 is a schematic diagram of the correlation coefficient calculation in the first embodiment of the present application.

[0033] Figure 5 is a flow chart of determining the target shift bit number in the second embodiment of the present application.

[0034] Figure 6 is a flow chart of determining the target shift bit number in the third embodiment of the present application.

[0035] Figure 7 is a flow chart of determining the target shift bit number in the fourth embodiment of the present application.

[0036] The present application is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0037] The time delay test system for high-speed interconnection chips of the present application generates two identical test signals through a signal generation module, one of which directly enters a first channel of a signal collection module, and the other of which enters a second channel of the signal collection module after passing through a device under test. A time delay analysis module intercepts signals collected by the signal collection module according to a preset time range, obtains two intercepted signals, calculates the correlation between the two intercepted signals, obtains the time difference between the two intercepted signals, and determines the time delay of the device under test. The device under test of the present application is an active chip device such as a high-speed interconnection chip.

[0038] First embodiment:

[0039] Referring to Figure 1 , the time delay test system of the present embodiment includes a signal generation module 11, a signal collection module 12, and a time delay analysis module 13. The signal generation module 11 is connected to the signal collection module 12 and the receiving end of an external device under test chip 2, the transmitting end of the device under test chip 2 is connected to the signal collection module 12, and the signal collection module 12 is connected to the time delay analysis module 13. The present embodiment realizes the test of the time delay of the device under test chip 2 through the time delay test system.

[0040] The signal generation module 11 is used to generate a first test signal and a second test signal. The first test signal and the second test signal are associated periodic binary sequences. "Associated" means that there is a specific relationship between the first test signal and the second signal, such as the same, inverse, a specific time delay, or a specific bit difference in a period. The first test signal and the second test signal of the present embodiment are the same test signals emitted at the same time by the signal generation module 11. The period of the periodic binary sequence is greater than the time delay of the device under test chip 2.

[0041] The first test signal directly enters the first channel of the signal acquisition module 12. The second test signal enters the receiving end of the chip under test 2, and then is output from the transmitting end of the chip under test 2 to the second channel of the signal acquisition module.

[0042] The periodic pseudo-random binary sequence is a binary sequence repeated according to a specific period, and the binary sequence of each period is the same. The signal generation module 11 of the embodiment generates two PRBS (Pseudo-Random Binary Sequence) code patterns of the same phase as the first test signal and the second test signal respectively.

[0043] In other embodiments, other periodic binary sequences can also be used as the first test signal and the second test signal.

[0044] The signal acquisition module 12 includes a first channel and a second channel for acquiring signals. The first channel is used to acquire the first test signal from the signal generation module 11, and the second channel is used to acquire the second test signal from the transmitting end of the chip under test 2. The first test signal directly acquired by the first channel is referred to as an original signal, and the second test signal acquired by the second channel enters the chip under test 2 and is referred to as a delayed signal. The signal acquisition module 12 is also used to send the original signal and the delayed signal to the time delay analysis module 13.

[0045] The time delay analysis module 13 is used to calculate and determine the time delay of the chip under test 2. After the time delay analysis module 13 acquires the original signal and the delayed signal, a first intercepted signal is obtained by intercepting the original signal within a preset time range, and a second intercepted signal is obtained by intercepting the delayed signal within the preset time range. The length of the preset time range is not less than the period of the periodic binary sequence. Then, the second intercepted signal is cyclically shifted to the left, and the target shift number corresponding to the time when the first intercepted signal and the second intercepted signal coincide is recorded. The target shift number is used to calculate the time delay of the chip under test 2, which represents the number of bits required for shifting between the first intercepted signal and the second intercepted signal when the accurate time delay of the chip under test 2 is obtained by multiplying the acquisition point interval.

[0046] In different embodiments, the above-mentioned signal generation module 11, signal acquisition module 12 and time delay analysis module 13 can correspond to specific hardware modules and / or software functional modules.

[0047] Referring to Figure 2 , the time delay test method of the chip under test based on the above-mentioned time delay test system can be implemented by a computer program, and specifically includes the following steps:

[0048] S11: Control the signal generation module to generate a first test signal and a second test signal.

[0049] Wherein, by controlling the output enable signal to the signal generation module, the code type of its output is PRBS15, so that the signal generation module can output the same first test signal and second test signal, wherein "same" not only means that the binary sequence of the composed signal is the same, but also the value corresponding to each position in the sequence is the same, for example, the value corresponding to the 0th position of the first test signal is the same as the value corresponding to the 0th position of the first test signal.

[0050] The repetition period of the PRBS code type is related to the length of the PRBS code and the signal transmission rate. The code type of PRBS15 (the repetition period is 32767 UI) is selected in this embodiment, and the signal transmission rate is 112G PAM4 signal (the symbol rate is 56Gsym / s, and the transmission time of one UI is 1 / 56G≈17.86ps), so the repetition period of one PRBS15 code type is 32767*17.86=585218.62ps≈585ns. As long as the time delay of the chip under test is not greater than 585ns, PRBS15 code type can be used for testing, otherwise a PRBS code type with a longer repetition period, such as PRBS23, etc. The present application only needs to satisfy that the repetition period of the PRBS code type is greater than the time delay of the chip under test, and does not limit the specific PRBS code type used.

[0051] S12: waiting for a preset time to make the chip under test complete the establishment of the link.

[0052] Wherein, by waiting for a preset time, the chip is allowed to enter a normal working state. The chip needs time for initialization from power-on to entering a normal working state, and the specific waiting time is determined according to the initialization time requirement of the chip under test. If no waiting is performed, the test is performed when the chip is not in a normal working state, which may cause inaccurate delay test. There are several possible reasons: one is that the internal data path of the chip is not normally established; two is that the chip under test may have no signal output to the signal acquisition module; three is that the output of the chip under test is not stable, and the signal acquisition module may acquire incorrect signals. By setting a preset time, the chip under test is allowed to complete the equalization of the receiving end and the establishment of the internal link of the chip.

[0053] S13: directly acquiring the first test signal by the signal acquisition module to obtain an original signal, and acquiring the second test signal passing through the chip under test to obtain a delay signal.

[0054] Wherein, the signal length recorded by the original signal and the delay signal is the same, and needs to be greater than the repetition period of one PRBS code type. Assuming that the sampling rate is Sa, the accuracy of the delay calculation is 1 / Sa, so the higher the sampling rate, the higher the accuracy of the delay. For example, if the sampling rate is 1GSa / s, the delay accuracy is 1ns; if the sampling rate is 100GSa / s, the delay accuracy is 0.01ns.

[0055] S14: intercepting, by the time delay analysis module, a first intercepted signal in a preset time range from the original signal, and intercepting a second intercepted signal in the preset time range from the time-delay signal.

[0056] The time intervals of the original signal and the time-delay signal need to be the same, that is, starting at the same time and ending at the same time. The duration of the preset time range needs to be greater than or equal to the length of a PRBS repetition period.

[0057] S15: circularly shifting, by the time delay analysis module, the second intercepted signal to the left, and recording a target shift bit number corresponding to a time when the first intercepted signal and the second intercepted signal coincide.

[0058] S16: multiplying, by the time delay analysis module, the target shift bit number by a sampling point interval of the signal acquisition module to obtain a time delay of the measured chip.

[0059] In the above step S15, referring to Figure 3 , specifically comprising the following steps:

[0060] S101: initializing a count value k = 0.

[0061] S102: circularly shifting the second intercepted signal to the left by k bits to obtain a shifted second intercepted signal. The shifted second intercepted signal is a second shifted signal.

[0062] S103: calculating the product of the values of the first intercepted signal and the shifted second intercepted signal at the same position, and adding all the corresponding products to obtain a correlation coefficient.

[0063] S104: adding 1 to the count value k.

[0064] S105: determining whether the count value is not less than the difference between the bit number of the first intercepted signal minus 1. If the result of the determination is yes, continue to execute step S106, otherwise return to step S102.

[0065] S106: determining that the bit number of the left circular shift corresponding to the maximum correlation coefficient is the target shift bit number.

[0066] Referring to Figure 4 , the bit numbers of the first intercepted signal and the second intercepted signal are both m+1 bits (the value of m+1 is determined by the sampling rate of the signal acquisition module and the preset time range), that is, including m+1 positions, each position corresponding to a binary value collected by a sampling point, that is, each position stores a "0" or a "1".

[0067] When k=0, the first intercepted signal is represented as Wa0, the value corresponding to the 0th position of the first intercepted signal is A0, the value corresponding to the 1st position is A1, and so on, the value corresponding to the mth position is Am; the second intercepted signal is represented as Wb0, the value corresponding to the 0th position of the second intercepted signal is B0, the value corresponding to the 1st position is B1, and so on, the value corresponding to the mth position is Bm. At this time, the correlation coefficient [0]=Result0+Result1+Result2+…+Result(m-1)+Result(m), Result0=A0xB0, Result1=A1xB1, Result2=A2xB2, …, Result(m-1)=A(m-1)xB(m-1), Result(m)=AmxBm.

[0068] When k=1, the values recorded on the second intercepted signal are circularly shifted to the left by 1 bit relative to when k=0, represented as Wb1, the first intercepted signal remains unchanged and is still represented as Wa0. At this time, the value corresponding to the 0th position of the second intercepted signal is B1, the value corresponding to the 1st position is B2, and so on, the value corresponding to the mth position is B0. At this time, the correlation coefficient [1]=Result0+Result1+Result2+…+Result(m-1)+Result(m), Result0=A0xB1, Result1=A1xB2, Result2=A2xB3, …, Result(m-1)=A(m-1)xBm, Result(m)=AmxB0.

[0069] When k=m-1, the values recorded on the second intercepted signal are circularly shifted to the left by (m-1) bits relative to when k=0, represented as Wb(m-1), the first intercepted signal remains unchanged and is still represented as Wa0. At this time, the value corresponding to the 0th position of the second intercepted signal is Bm, the value corresponding to the 1st position is B0, and so on, the value corresponding to the mth position is B(m-1). At this time, the correlation coefficient [m-1]=Result0+Result1+Result2+…+Result(m-1)+Result(m), Result0=A0xBm, Result1=A1xB0, Result2=A2xB1, …, Result(m-1)=A(m-1)xB(m-2), Result(m)=AmxB(m-1).

[0070] Thus, m correlation coefficients can be obtained, and the bit number of the left cyclic shift corresponding to the maximum correlation coefficient is the target shift bit number.

[0071] In step S106, the target shift bit number is multiplied by each sample point interval to obtain the time delay of the measured chip. The sample point interval is determined according to the sampling rate of the signal acquisition module, and the sampling rate of the embodiment is Sa. The accuracy of the time delay calculation is 1 / Sa, and the sample point interval is 1 / Sa. The target shift bit number is Pa, and the time delay of the measured chip is Pa*1 / Sa.

[0072] The computer instructions for implementing the above method can be stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device execute each step of the above time delay test method for the interconnection chip.

[0073] Second embodiment:

[0074] The difference between the embodiment and the above first embodiment is step S15. Referring to Figure 5 , step S15 of the embodiment specifically includes the following steps:

[0075] S201: initialize the count value j=0.

[0076] S202: right cyclic shift the second intercepted signal by j bits to obtain a second shifted signal.

[0077] S203: calculate the product of the values of the first intercepted signal and the second shifted signal at the same position, and add all the corresponding products to obtain a correlation coefficient.

[0078] S204: add 1 to the count value j.

[0079] S205: determine whether the count value is not less than the difference between the bit number of the first intercepted signal and 1. If the result of the determination is yes, continue to execute step S206, otherwise return to step S202.

[0080] S206: determine the target shift bit number as the difference between the bit number of the first intercepted signal and the bit number of the right cyclic shift corresponding to the maximum correlation coefficient.

[0081] Third embodiment:

[0082] The difference between the embodiment and the above first embodiment is step S15. Referring to Figure 6 , step S15 of the embodiment specifically includes the following steps:

[0083] S301: initialize a count value i=0.

[0084] S302: cyclically shift the first intercepted signal to the left by i bits to obtain a shifted first intercepted signal.

[0085] S303: calculate the product of the values of the shifted first intercepted signal and the second intercepted signal at the same positions, and sum all the products corresponding to the positions to obtain a correlation coefficient.

[0086] S304: add 1 to the count value i.

[0087] S305: determine whether the count value i is not less than the difference between the number of bits of the first intercepted signal and 1. If the result of the determination is yes, continue to execute step S306, otherwise return to step S302.

[0088] S306: determine the target shift bit number as the difference between the number of bits of the first intercepted signal and the number of bits of the left cyclic shift corresponding to the maximum correlation coefficient.

[0089] Fourth embodiment:

[0090] The difference between the present embodiment and the first embodiment described above lies in the method of determining the target shift bit number.

[0091] In the present embodiment, the time delay analysis module is further configured to determine the maximum correlation coefficient according to the first intercepted signal. Since the number of values "1" in the first intercepted signal is fixed, the number of values "1" is counted to obtain the value of the maximum correlation coefficient. For example, if the number of values "1" in the first intercepted signal is M, then the value of the maximum correlation coefficient is M.

[0092] The difference between the determination of the target shift bit number in step S15 of the first embodiment described above lies in that, in the present embodiment, the corresponding correlation coefficient is calculated after one left cyclic shift, until the current correlation coefficient is the maximum correlation coefficient, at which time the number of bits of the current left cyclic shift is recorded as the target shift bit number. See Figure 7 , which specifically includes the following steps:

[0093] S401: initialize a count value n=0.

[0094] S402: cyclically shift the second intercepted signal to the left by n bits to obtain a shifted second intercepted signal.

[0095] S403: calculate the product of the values of the first intercepted signal and the shifted second intercepted signal at the same positions, and sum all the products corresponding to the positions to obtain a correlation coefficient.

[0096] S404: add 1 to the count value n.

[0097] S405: determine whether the current correlation coefficient is the maximum correlation coefficient, if yes, continue to execute step S406, otherwise return to step S402.

[0098] S406: determine that the bit number of the left cyclic shift corresponding to the current correlation coefficient is the target shift bit number.

[0099] The fifth embodiment:

[0100] The difference between the embodiment and the first embodiment is the signal generation module and the delay analysis module.

[0101] The difference between the signal generation module is that it is a differential output, that is, the first test signal and the second test signal are aligned but inverted. The first end of the differential output is connected to the signal acquisition module, so that the first test signal enters the signal acquisition module; the second end of the differential output is connected to the receiving end of the chip under test, so that the second test signal enters the input end of the chip under test.

[0102] The difference between the delay analysis module is that after obtaining the original signal and the delay signal, the polarity of the original signal or the delay signal is flipped, and then the first and second cut-off signals are obtained.

[0103] The sixth embodiment:

[0104] The difference between the embodiment and the first embodiment is that the signal generation module sends the same first test signal and second test signal according to a set delay, and the first test signal and the second test signal are the same periodic binary sequence, and the set delay is less than the period of the periodic binary sequence. Therefore, when the target shift bit number is multiplied by the interval of each sampling point, the set delay needs to be subtracted to obtain the delay of the chip under test.

[0105] In summary, the application ensures the normal operation of the internal circuit of the high-speed interconnection chip by using the PRBS code type, ensures that the delay test result is close to the real scene of the device under test, and uses the characteristic that the PRBS code has a certain repetition period, obtains the delay information between two signals by the cyclic shift point product sum between two signals, and obtains accurate delay test results.

[0106] Finally, it should be emphasized that the above description is only the preferred embodiment of the application and is not used to limit the application. For those skilled in the art, the application can have various changes and modifications, and any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A method for testing latency for interconnect chips, the method comprising: The method comprises the following steps: collecting a first test signal to obtain an original signal; collecting a second test signal passing through the chip under test to obtain a delay signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the time delay of the chip under test; cutting a first cut signal in a preset time range from the original signal, and cutting a second cut signal in the preset time range from the delay signal; the time length of the preset time range is not less than the period of the periodic binary sequence; cyclically shifting the first cut signal or the second cut signal in a set direction, and recording the target shift bit number corresponding to the coincidence of the first cut signal and the second cut signal; determining the time delay of the chip under test according to the target shift bit number.

2. The inter-chip time delay test method according to claim 1, wherein: the first test signal and the second test signal are the same or inverse signals; when the first test signal and the second test signal are inverse signals, the original signal is obtained by collecting the first test signal and performing polarity inversion, or the delay signal is obtained by collecting the second test signal passing through the chip under test and performing polarity inversion; multiplying the target shift bit number and the sampling point interval to obtain the time delay of the chip under test.

3. The inter-chip time delay test method according to claim 1, wherein: the first test signal and the second test signal are the same signals emitted by the set time delay, or signals different at specific bits in a period.

4. The inter-chip time delay test method according to claim 1, wherein: before collecting the original signal and the delay signal, a preset time is waited for the chip under test to complete the establishment of a link.

5. The inter-chip time delay test method according to claim 1, wherein: when cyclically shifting the first cut signal or the second cut signal in a set direction and recording the target shift bit number corresponding to the coincidence of the first cut signal and the second cut signal, the method comprises: initializing a count value to 0; repeatedly performing the following steps until the count value is not less than the difference between the bit number of the first cut signal and 1: cyclically shifting the first cut signal to the left or to the right by the same bit number as the count value to obtain a first shifted signal; calculating the product of the values of the first cut signal and the first shifted signal at the same positions, and summing all the corresponding products to obtain a correlation coefficient; and increasing the count value by 1; when the count value is not less than the difference between the bit number of the first cut signal and 1, determining the target shift bit number according to the shift bit number of the first cut signal corresponding to the maximum correlation coefficient.

6. The inter-chip time delay test method according to claim 1, wherein: when cyclically shifting the first cut signal or the second cut signal in a set direction and recording the target shift bit number corresponding to the coincidence of the first cut signal and the second cut signal, the method comprises: initializing a count value as 0; repeating the following steps until the count value is not less than the difference between the bit number of the first intercepted signal and 1: cyclically shifting the second intercepted signal left or right by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values of the first intercepted signal and the second shifted signal at the same positions, and summing up the products corresponding to all positions to obtain a correlation coefficient; and adding 1 to the count value; when the count value is not less than the difference between the bit number of the first intercepted signal and 1, determining the target shift bit number according to the shift bit number of the second intercepted signal corresponding to the maximum correlation coefficient.

7. The method of claim 1, wherein the method further comprises: determining a time delay between the first and second clock signals; and determining a time delay between the third and fourth clock signals. Further comprising: determining the maximum correlation coefficient according to the first intercepted signal; when the first intercepted signal or the second intercepted signal is shifted towards a set direction and the target shift bit number corresponding to the time when the first intercepted signal and the second intercepted signal coincide is recorded, comprising: initializing a count value as 0; repeating the following steps until the current correlation coefficient is the maximum correlation coefficient: cyclically shifting the second intercepted signal left by the same number of bits as the count value to obtain a second shifted signal; calculating the product of the values of the first intercepted signal and the second shifted signal at the same positions, and summing up the products corresponding to all positions to obtain the current correlation coefficient; and adding 1 to the count value; when the current correlation coefficient is the maximum correlation coefficient, determining the left cyclic shift bit number of the second intercepted signal corresponding to the current correlation coefficient as the target shift bit number.

8. The inter-chip oriented time delay test method of claim 1, wherein: the code type corresponding to the first test signal and the second test signal is a PRBS code type.

9. A latency test system for interconnect chips, characterized by, comprising: a signal generation module, a signal collection module, and a time delay analysis module; the signal generation module is configured to generate a first test signal and a second test signal; the first test signal and the second test signal are associated periodic binary sequences; the period of the periodic binary sequence is greater than the time delay of the tested chip; the signal collection module is configured to directly collect the first test signal to obtain an original signal, and to collect the second test signal passing through the tested chip to obtain a time-delayed signal; the time delay analysis module is further configured to determine the time delay of the tested chip, comprising the following steps: intercepting the original signal in a preset time range to obtain a first intercepted signal, and intercepting the time-delayed signal in the preset time range to obtain a second intercepted signal; the time length of the preset time range is not less than the period of the periodic binary sequence; cyclically shifting the first intercepted signal or the second intercepted signal towards a set direction, and recording the target shift bit number corresponding to the time when the first intercepted signal and the second intercepted signal coincide; determining the time delay of the tested chip according to the target shift bit number.

10. A computer program product comprising computer instructions, wherein: the computer instructions are executed by a processor to implement the inter-chip oriented time delay test method of any one of claims 1-8.

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