An inter-board synchronization platform and method based on RFSoC

Abstract

This application relates to the field of signal acquisition technology, and discloses an inter-board synchronization platform and method based on RFSoC, including a frequency synthesis board, a timing control board, and multiple acquisition boards. The output of the frequency synthesis board is connected to the input of the timing control board and the input of the multiple acquisition boards, respectively. The output of the timing control board is connected to the input of the multiple acquisition boards. The frequency synthesis board is used to output a reference clock signal to the timing control board and the multiple acquisition boards. The timing control board is used to synchronously output a synchronization trigger multiplexing signal to the multiple acquisition boards according to the reference clock signal, and to receive the synchronization deviation information of the multiple acquisition boards, and to perform timing synchronization correction on the multiple acquisition boards according to the synchronization deviation information. The multiple acquisition boards are used to synchronously execute corresponding actions according to the synchronization trigger multiplexing signal. Its beneficial effect is that it effectively improves the synchronization between the acquisition boards and ensures that the acquisition boards and their acquisition channels are in a synchronized state.

Description

Technical Field

[0001] This application relates to the field of signal acquisition technology, and in particular to an inter-board synchronization platform and method based on RFSoC. Background Technology

[0002] In fields such as radio astronomy, radar, ultrasonic imaging, and meteorological detection, increasing the number of acquisition channels and simultaneously acquiring signals and performing beamforming across multiple channels is typically used to improve the accuracy of observation results and enhance signal quality. In practice, the number of acquisition channels can range from dozens to thousands, deployed across different acquisition boards. However, due to limitations in chip manufacturing processes, delay uncertainties or phase inconsistencies often exist between acquisition boards in any system containing multiple independent analog-to-digital converters and clock structures. This can negatively impact the performance of backend digital signal processing. Therefore, ensuring the synchronization and consistency of multi-channel signals across acquisition boards is crucial.

[0003] Related technologies typically utilize complex systems to synchronize the acquisition channels of various acquisition boards. However, as the number of channels increases, this approach becomes susceptible to transmission delays and signal jitter. Furthermore, its overly complex system structure itself reduces the synchronization accuracy between acquisition boards. Therefore, the complexity of inter-board synchronization platforms in related technologies still needs improvement. Summary of the Invention

[0004] This application provides an inter-board synchronization platform and method based on RFSoC. A reference clock signal of the same origin is generated based on the frequency synthesis board as the reference clock of the inter-board synchronization platform. The timing control board is used to perform synchronization control on each acquisition board based on the reference clock, which effectively improves the synchronization between the acquisition boards and ensures that the acquisition boards and their acquisition channels are in a synchronized state.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide an inter-board synchronization platform based on RFSoC, including a frequency synthesis board, a timing control board, and multiple acquisition boards, wherein:

[0007] The output terminal of the frequency integration board is connected to the input terminal of the timing control board and the input terminals of the multiple acquisition boards, respectively; the output terminal of the timing control board is connected to the input terminals of the multiple acquisition boards.

[0008] The frequency integration board is used to output a reference clock signal to the timing control board and the plurality of acquisition boards;

[0009] The timing control board is used to synchronously output a synchronous trigger multiplexing signal to the plurality of acquisition boards according to the reference clock signal, and to receive the synchronization deviation information of the plurality of acquisition boards, and to perform timing synchronization correction on the plurality of acquisition boards according to the synchronization deviation information.

[0010] The multiple acquisition boards are used to synchronously execute corresponding actions based on the reference clock signal as a clock reference and the synchronous trigger multiplexing signal.

[0011] The inter-board synchronization platform based on RFSoC proposed in this application constructs an inter-board synchronization platform including a frequency synthesis board, a timing control board, and multiple acquisition boards. The frequency synthesis board generates a common reference clock signal and sends it to the timing control board and each acquisition board as the reference clock for the inter-board synchronization platform. Based on the reference clock, the timing control board controls each acquisition board to synchronously execute corresponding actions through a synchronous trigger multiplexing signal. Furthermore, by acquiring synchronization deviation information between acquisition boards, timing synchronization correction is performed on each acquisition board to ensure the timing synchronization state between the acquisition boards. Compared with related technologies, the inter-board synchronization platform provided in this application utilizes a common reference clock signal output from the frequency synthesis board to other boards as a reference clock, and further uses a synchronous trigger multiplexing signal to synchronously control multiple acquisition boards through the timing control board. This effectively reduces the hardware structure required for synchronous control of the acquisition boards and lowers the complexity of the inter-board synchronization platform. Furthermore, multiple acquisition channels undergo timing synchronization correction under the synchronous control of the timing control board, enabling signal acquisition with the same timing state, further improving the synchronization between acquisition boards.

[0012] Optionally, the length of the wiring connecting the timing control board and any one of the plurality of acquisition boards is the same, so that the synchronous trigger multiplexed signals output to the plurality of acquisition boards are all in phase.

[0013] Optionally, the synchronous trigger multiplexing signal controls the multiple acquisition boards to synchronously execute any one of the following actions: signal acquisition synchronous trigger, logic state reset trigger, and synchronous deviation information acquisition trigger.

[0014] Optionally, the inter-board synchronization platform further includes a data switch, which is connected between the timing control board and the plurality of acquisition boards.

[0015] Optionally, the data switch is used to transmit the synchronization deviation information of the multiple acquisition boards to the timing control board after the multiple acquisition boards are triggered by the synchronization trigger multiplexing signal.

[0016] Optionally, the timing control board is used to determine deviation compensation information and output the deviation compensation information to the plurality of acquisition boards through the data switch.

[0017] Optionally, the deviation compensation information is obtained by performing deviation compensation calculation based on the synchronization deviation information.

[0018] Optionally, in a bare-metal programming environment, the inter-board synchronization platform stores corresponding register physical addresses in each of the multiple acquisition boards.

[0019] Optionally, in the operating system environment, the inter-board synchronization platform allows the multiple acquisition boards to obtain the corresponding register physical addresses according to the integrated device tree.

[0020] Secondly, embodiments of this application provide an inter-board synchronization method based on RFSoC, used in any of the above embodiments of the inter-board synchronization platform based on RFSoC. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the clock tree structure of the RFSoC-based inter-board synchronization platform provided in this application embodiment;

[0023] Figure 2 This is a hardware block diagram of the frequency integration board in the embodiments of this application;

[0024] Figure 3 This is a hardware block diagram of the timing control board in the embodiments of this application;

[0025] Figure 4 This is a waveform diagram of the synchronous trigger multiplexing signal in an embodiment of this application;

[0026] Figure 5 A flowchart illustrating the RFSoC-based inter-board synchronization method provided in this application embodiment;

[0027] Figure 6 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used in the description of this application is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the description, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the description, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a specific order or hierarchy.

[0030] In fields such as radio astronomy, radar, ultrasonic imaging, or meteorological detection, conventional techniques typically increase the number of acquisition channels and use multiple channels to simultaneously receive and transmit signals, thereby increasing the amount of data collected and improving the quality of the acquired signals. In real-world scenarios, the number of acquisition channels can range from dozens to thousands, and these channels are deployed on different acquisition boards. The degree of synchronization between these acquisition boards greatly affects the synchronization between the acquisition channels.

[0031] For example, multi-channel synchronous signal acquisition can be achieved using a phased array system in conventional technology. A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to achieve precise regulation of electromagnetic wave transmission and reception. With the rapid development of phased array systems, they have played an important role in many fields such as radio astronomy, radar, ultrasonic imaging, and meteorological detection, and have broad application prospects. A phased array system can have thousands of acquisition channels, which are designed on multiple acquisition boards. The synchronization between different acquisition boards is the key to achieving multi-channel synchronous signal acquisition in a phased array system.

[0032] Related technologies typically employ analog-to-digital converters (ADCs) and the J.204B protocol for inter-channel synchronization. Within a field-programmable gate array (FPGA), the J.204B protocol is used to synchronize, parse, and process the data from each channel. However, as the number of channels increases, this approach becomes susceptible to transmission delays and signal jitter, leading to a decline in the quality of the acquired signal. Understandably, the overly complex system architecture in these technologies can also reduce the synchronization between acquisition boards, posing a challenge to system stability. Therefore, the complexity of inter-board synchronization platforms in these technologies still needs improvement.

[0033] To address the aforementioned issues, this application provides an inter-board synchronization platform and method based on RFSoC, comprising a frequency synthesis board, a timing control board, and multiple acquisition boards. The output of the frequency synthesis board is connected to the input of the timing control board and the inputs of the multiple acquisition boards, respectively. The output of the timing control board is connected to the input of the multiple acquisition boards. The frequency synthesis board outputs a reference clock signal to the timing control board and the multiple acquisition boards. The timing control board outputs a synchronization trigger multiplexing signal to the multiple acquisition boards synchronously based on the reference clock signal, receives synchronization deviation information from the multiple acquisition boards, and performs timing synchronization correction on the multiple acquisition boards based on the synchronization deviation information. The multiple acquisition boards use the reference clock signal as a clock reference and synchronously execute corresponding actions based on the synchronization trigger multiplexing signal.

[0034] The RFSoC-based inter-board synchronization platform provided in this application establishes an inter-board synchronization platform including a frequency synthesis board, a timing control board, and multiple acquisition boards. The frequency synthesis board generates a common reference clock signal and sends it to the timing control board and each acquisition board as the reference clock for the inter-board synchronization platform. Based on the reference clock, the timing control board controls each acquisition board to synchronously execute corresponding actions through a synchronous trigger multiplexing signal. Furthermore, by acquiring the synchronization deviation information between the acquisition boards, the timing synchronization correction of each acquisition board is performed to ensure the timing synchronization status between the acquisition boards.

[0035] Compared with related technologies, the inter-board synchronization platform provided in this application uses a frequency synthesis board to output a reference clock signal from the same source to other boards as a reference clock. Furthermore, it uses a timing control board to synchronously control multiple acquisition boards using a synchronous trigger multiplexing signal, which effectively reduces the hardware structure required for synchronous control of acquisition boards and lowers the complexity of the inter-board synchronization platform. On this basis, multiple acquisition channels undergo timing synchronization correction under the synchronous control of the timing control board, thereby enabling signal acquisition with the same timing state and further improving the synchronization between acquisition boards.

[0036] The RFSoC-based inter-board synchronization platform provided in this specification can be applied to phased array systems. Phased array systems can be used in various fields such as radio astronomy, radar, ultrasonic imaging, and meteorological detection. In radio astronomy, phased array systems can be used to build phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It is understood that, with adaptive modifications, this application can also be used in other systems or devices that perform multi-channel signal acquisition, such as multi-channel data acquisition systems, high-frequency trading systems, or automated testing systems.

[0037] This application provides an inter-board synchronization platform based on RFSoC, including a frequency synthesis board, a timing control board, and multiple acquisition boards, wherein:

[0038] The output of the frequency integration board is connected to the input of the timing control board and the input of multiple acquisition boards, respectively. The output of the timing control board is connected to the input of multiple acquisition boards.

[0039] The frequency integration board is used to output reference clock signals to the timing control board and multiple acquisition boards;

[0040] The timing control board is used to output synchronous trigger multiplexing signals to multiple acquisition boards according to the reference clock signal, and to receive the synchronization deviation information of multiple acquisition boards, and to perform timing synchronization correction on multiple acquisition boards according to the synchronization deviation information.

[0041] Multiple acquisition boards are used to execute corresponding actions synchronously based on the reference clock signal as the clock reference and the synchronous trigger multiplexing signal.

[0042] The reference clock signal can be a low-frequency clock signal generated by the frequency synthesis board, used to calibrate the clock of the inter-board synchronization platform, so that all boards within the platform can operate synchronously with the same clock signal. For example, the frequency of the reference clock signal can be 10MHz.

[0043] The synchronous trigger multiplexing signal can be a clock pulse signal generated by the timing control board, containing different indicator signals, used to control each acquisition board to perform corresponding actions for synchronous processing. It should be noted that different indicator signals are distinguishable in terms of the same signal characteristics, which may include signal level, signal frequency, signal amplitude, or signal phase. For example, different indicator signals may correspond to different signal frequencies, thus allowing for differentiation by frequency measurement of the synchronous trigger multiplexing signal.

[0044] Synchronization deviation information can be the channel delay value or channel phase value of each acquisition channel in the acquisition board. When the acquisition boards are out of sync, the channel delay value or channel phase value of each acquisition channel will be different. For example, the channel delay value can be the FIFO delay value.

[0045] Reference Figure 1 As shown, the inter-board synchronization platform provided in this embodiment includes a frequency integration board, a timing control board, and multiple acquisition boards. The output of the frequency integration board is connected to the input of the timing control board and the input of the multiple acquisition boards, respectively. The output of the timing control board is connected to the input of the multiple acquisition boards. Each acquisition board contains one or more acquisition channels for signal acquisition.

[0046] The frequency synthesis board generates a reference clock signal as a global reference clock and outputs it to the timing control board, which then uses this reference clock signal to synchronize the acquisition boards. The frequency synthesis board can have multiple outputs, typically exceeding the number of acquisition boards, and each output connects to a specific acquisition board to provide a reference clock signal as a clock base, ensuring that all acquisition boards have the same clock reference. It is understood that the reference clock signals received by each board are coherent and from the same source. Outputting the clock signal through a single frequency synthesis board effectively reduces potential timing errors between clock signals generated from different clock sources, improving the timing consistency and stability of multiple clock signals. Furthermore, the single frequency synthesis board simplifies the hardware design within the inter-board synchronization platform, reducing its complexity and improving its hardware stability and ease of use.

[0047] For example, refer to Figure 2 As shown, the frequency integration board can be a board comprising one rubidium atomic clock frequency standard source and two 1:16 frequency standard distributors. The rubidium atomic clock frequency standard source has GPS / BeiDou satellite discipline capabilities, enabling it to receive GPS / BeiDou satellite signals and synchronize the rubidium oscillator output frequency with the GPS / BeiDou satellite signal, thus providing a high-precision time and frequency signal at the level of a cesium atomic clock. The clock signal output from the rubidium atomic clock frequency standard source is then passed through the two 1:16 frequency standard distributors to obtain multiple clock signals, providing stable operating reference clocks for multiple acquisition boards, thereby ensuring the stable and synchronous operation of the acquisition boards.

[0048] The timing control board generates synchronous trigger multiplexed signals for synchronizing the acquisition boards. After receiving the reference clock signal from the frequency synthesis board, it uses the reference clock signal as a clock reference to output synchronous trigger multiplexed signals to each acquisition board, thereby performing timing synchronization correction or synchronous action control on each acquisition board. The output of the timing control board is connected to the input of multiple acquisition boards, and signal coupling between the timing control board and the multiple acquisition boards is achieved through DC coupling to reduce glitches in the synchronous trigger multiplexed signals received by the acquisition boards and improve the signal quality of the synchronous trigger multiplexed signals. It should be noted that the timing control board is connected to each acquisition board through separate wiring and controls each acquisition board to perform corresponding actions through synchronous trigger multiplexed signals. This effectively reduces the number of wires between the timing control board and the acquisition boards, thereby reducing the complexity of the inter-board synchronization platform and improving its reliability.

[0049] Furthermore, the timing control board includes a programmable logic (PL) side and a processing system (PS) side, which can be connected via an AXI bus for instruction transmission and parameter configuration. The PL side has multiple output terminals, each corresponding to a different acquisition board. The PL side receives multiplexed signal commands from the processing system side and then sends synchronous trigger multiplexed signals to the acquisition boards to instruct them to perform corresponding actions. The processing system side loads the timing control board's firmware and drivers and can schedule the board's outputs via multiplexed signal commands, ensuring that the synchronous trigger multiplexed signals output by the timing control board indicate the appropriate actions. The processing system side can connect to a host computer or other devices to obtain system status or external commands, thereby generating corresponding multiplexed signal commands.

[0050] For example, refer to Figure 3As shown, the timing control board can be a board comprising Zynq SoC series FPGA modules, KU series pure PL FPGA modules, and input terminals. The input terminals receive a reference clock signal output from the frequency synthesis board and send this reference clock signal to the Zynq SoC series FPGA modules and the KU series pure PL FPGA modules as their clock references. The Zynq SoC series FPGA modules communicate with a host computer or multiple acquisition boards to exchange signal data. For example, the Zynq SoC series FPGA modules may communicate with the host computer or multiple acquisition boards via a gigabit Ethernet port on the PS side. The KU series pure FPGA modules have output terminals connected to multiple acquisition boards respectively, used to output synchronous trigger multiplexed signals to each acquisition board using the reference clock signal as a clock reference, for synchronous control of each acquisition board.

[0051] The acquisition board, acting as the executor of signal acquisition, is used to perform corresponding actions based on the synchronous trigger multiplexed signal, using the reference clock signal output by the frequency synthesis board as the clock reference, to achieve synchronous signal acquisition. The acquisition board includes a programmable logic side and a processing system side. The programmable logic side contains a signal acquisition module with one or more acquisition channels for signal acquisition. In some embodiments, the programmable logic side may also integrate digital signal processing functions, including but not limited to digital quadrature demodulation and decimation filtering, to process the acquired signal after acquisition. The programmable logic side also receives the synchronous trigger multiplexed signal output by the timing control board, parses the signal, and determines the corresponding action to be performed. The processing system side can configure the clock signal of the acquisition board and start the required logic files by calling the API driver software. The processing system side also receives synchronization information obtained from the acquisition board. The processing system side interacts with the programmable logic side through the AXI interface, sending multiplexed signal commands to the programmable logic side.

[0052] For example, the acquisition board can integrate modules such as input interfaces, a clock management chip, an RFSoC series FPGA processing chip, a DDR memory module, a power supply module, and output interfaces. The input interfaces include multi-channel RF signal acquisition interfaces and a clock signal interface. The clock management chip can be a single clock chip connected to the clock signal interface, used to receive the reference clock signal output from the frequency synthesis board and perform clock signal processing on the reference clock signal to obtain clock signals such as the programmable logic side user clock and the high-frequency sampling clock. The high-frequency sampling clock serves as the clock reference for each acquisition channel during signal acquisition. The programmable logic side user clock serves as the clock reference for the programmable logic side on the acquisition board, enabling the programmable logic side to synchronously execute corresponding actions according to the programmable logic side user clock, including signal processing and multiplexing signal triggering. The RFSoC series FPGA processing chip integrates an RFDCIP core, capable of simultaneously performing analog-to-digital conversion or digital processing on analog signals input from multiple RF signal acquisition interfaces. The DDR memory module expands the data storage capacity of the acquisition board. The power supply module includes a Core PWR and a PWR Conn, providing the voltage required for signal acquisition. The output interfaces include a QSFP28 optical port and a GE Ethernet interface, with the QSFP28 optical port having a single-port communication rate of up to 100Gbps.

[0053] In some embodiments, timing synchronization correction may include board delay synchronization correction and board phase synchronization correction. The board delay synchronization correction process may include: initializing the delay of each acquisition channel in multiple acquisition boards; performing automatic channel delay value testing on each acquisition channel to obtain its own channel delay value; if the channel delay values ​​corresponding to each acquisition channel are the same, determining that each acquisition board has completed delay synchronization, and ending the board delay synchronization correction process; if the channel delay values ​​corresponding to each acquisition channel are different, selecting the largest channel delay value from all channel delay values, and performing redundancy design based on this channel delay value to obtain a target delay value; allocating the target delay value to each acquisition board, and allocating the target delay value to the acquisition channels within each acquisition board, so that the channel delay value of each acquisition channel is set to the target delay value, thus completing the board delay synchronization correction. For example, the redundancy design may be adding a delay of 16 clock cycles to the largest channel delay value.

[0054] The board phase synchronization correction process may include: turning off the reference signal receivers of each acquisition channel and stopping the reception of the analog reference signal used to trigger the board phase synchronization correction; performing initial phase settings and application configuration updates for each acquisition channel, and setting the mixing trigger source of each acquisition channel to the analog reference signal; turning on the reference signal receivers of each acquisition channel so that each acquisition channel synchronously receives the analog reference signal; capturing multiple cycles of the analog reference signal, and using the analog reference signal in each cycle to trigger phase synchronization of each acquisition channel to align the channel phase values ​​of each acquisition channel; turning off the reference signal receivers of each acquisition channel after multiple cycles of signal capture, stopping the reception of the analog reference signal, to lock the channel phase value settings of each acquisition channel and ensure phase synchronization between acquisition channels.

[0055] It should be noted that the phase synchronization process may include: triggering each acquisition channel to perform phase initialization with an analog reference signal within each cycle; acquiring the channel phase value of each acquisition channel and calculating the channel phase difference between each acquisition channel; if the channel phase difference between each acquisition channel is fixed, performing channel phase compensation on each acquisition channel to align the channel phase values ​​of each acquisition channel; and triggering each acquisition channel again with an analog reference signal for multiple cycles to make the channel phase compensation of each acquisition channel effective, thereby achieving phase synchronization between channels. In some embodiments, if the channel phase difference between each acquisition channel is not fixed, multiple synchronization processes including phase information acquisition, channel phase compensation, and analog reference signal triggering can be performed until the channel phase values ​​of all acquisition channels are aligned, achieving a phase synchronization state.

[0056] In some embodiments, the acquisition board may include digital processing capabilities, in which case the signal flow of each acquisition channel passes through both analog and digital processing domains. Each of these two signal processing domains corresponds to a clock signal with a different processing frequency, and there may be a phase difference between the analog processing clock in the analog processing domain and the digital processing clock in the digital processing domain. When each signal enters the digital processing domain from the analog processing domain, the phase difference between the analog and digital processing clocks can cause signal delay errors in different acquisition channels, affecting the synchronization between the acquisition channels. In this case, when synchronizing the phase of each acquisition channel between boards, the analog and digital processing clocks of each board are also synchronized separately, ensuring that the analog and digital processing clocks are in a relatively fixed phase state. This ensures that the acquisition signals in each acquisition channel enter the digital processing domain at the same clock position, enabling the acquisition signals to be received and processed synchronously, reducing potential delays or phase errors between acquisition channels, and improving the synchronization between acquisition channels.

[0057] The RFSoC-based inter-board synchronization platform provided in this embodiment establishes an inter-board synchronization platform including a frequency synthesis board, a timing control board, and multiple acquisition boards. The frequency synthesis board generates a common reference clock signal and sends it to the timing control board and each acquisition board as the reference clock for the inter-board synchronization platform. Based on the reference clock, the timing control board controls each acquisition board to synchronously execute corresponding actions through a synchronous trigger multiplexing signal. Furthermore, by acquiring the synchronization deviation information between the acquisition boards, the timing synchronization correction of each acquisition board is performed to ensure the timing synchronization status between the acquisition boards.

[0058] Compared with related technologies, the inter-board synchronization platform provided in this application uses a frequency synthesis board to output a reference clock signal from the same source to other boards as a reference clock. Furthermore, it uses a timing control board to synchronously control multiple acquisition boards using a synchronous trigger multiplexing signal, which effectively reduces the hardware structure required for synchronous control of acquisition boards and lowers the complexity of the inter-board synchronization platform. On this basis, multiple acquisition channels undergo timing synchronization correction under the synchronous control of the timing control board, thereby enabling signal acquisition with the same timing state and further improving the synchronization between acquisition boards.

[0059] As one embodiment of this application, the length of the wiring connecting the timing control board and any one of the multiple acquisition boards is the same, so that the synchronous trigger multiplexed signals output to the multiple acquisition boards are all in phase.

[0060] Specifically, the timing control board is connected to each acquisition board and outputs synchronous trigger multiplexed signals to each acquisition board through separate connection wiring to control each acquisition board to execute corresponding actions synchronously. To ensure that each acquisition board can execute actions synchronously, the synchronous trigger multiplexed signals output to each acquisition board need to be in phase. By sending the same synchronous trigger multiplexed signal to each acquisition board and designing the length of the connection wiring between the timing control board and any acquisition board to be the same, the output time required for multiple synchronous trigger multiplexed signals to be output to each acquisition board is the same, thereby ensuring that the synchronous trigger multiplexed signals arriving at each acquisition board are in phase, improving the synchronization between the acquisition boards.

[0061] As one embodiment of this application, the synchronous trigger multiplexing signal controls multiple acquisition boards to synchronously execute any one of the following actions: signal acquisition synchronous trigger, logic state reset trigger, and synchronous deviation information acquisition trigger.

[0062] Among these, signal acquisition synchronization triggering can be based on a synchronization trigger multiplexed signal, triggering the action of synchronous signal acquisition by each acquisition channel on multiple acquisition boards. Logic state reset triggering can be based on a synchronization trigger multiplexed signal, triggering the action of resetting the logic state of each acquisition channel on multiple acquisition boards to restore it to its initial logic state. Synchronization deviation information acquisition triggering can be based on a synchronization trigger multiplexed signal, triggering the action of each acquisition channel on multiple acquisition boards to acquire its own synchronization deviation information.

[0063] Specifically, the synchronization trigger multiplexing signal can be a clock pulse signal generated by the timing control board, containing different indicator signals, used to control each acquisition board to perform corresponding actions to synchronize the acquisition boards. These corresponding actions can include signal acquisition synchronization triggering, logic state reset triggering, and synchronization deviation information acquisition triggering, etc. Each corresponding action corresponds to a different indicator signal. Different indicator signals are distinguishable from each other based on the same signal characteristics, which can include signal level, high / low level duration, signal frequency, signal amplitude, or signal phase.

[0064] For example, a distinguishable signal characteristic of the indication signal could be the duration of a low level, thereby enabling the differentiation of different indication signals by level-detection timing of the synchronous trigger multiplexed signal. (See reference...) Figure 4 As shown, Figure 4 In this context, clk represents the reference clock signal, IO_in represents the synchronous trigger multiplexing signal, count represents the timing signal, SYNC represents the indicator signal for synchronous triggering of the corresponding signal acquisition, Reset represents the indicator signal for triggering the corresponding logic state reset, and Catch represents the indicator signal for triggering the corresponding synchronous deviation information acquisition.

[0065] As can be seen, the synchronous trigger multiplexed signal contains a low-level signal for 3 clock cycles. This low-level signal is used as an indicator signal, and the acquisition board determines the duration of the low level to be 3 clock cycles using a timing signal, thus determining the corresponding action as signal acquisition synchronization trigger. Similarly, the synchronous trigger multiplexed signal contains a low-level signal for 2 clock cycles. This low-level signal is used as an indicator signal, and the acquisition board determines the duration of the low level to be 2 clock cycles using a timing signal, thus determining the corresponding action as logic state reset trigger. The synchronous trigger multiplexed signal contains a low-level signal for 1 clock cycle. This low-level signal is used as an indicator signal, and the acquisition board determines the duration of the low level to be 1 clock cycle using a timing signal, thus determining the corresponding action as synchronization deviation information acquisition trigger.

[0066] As one embodiment of this application, the inter-board synchronization platform also includes a data switch, which is connected between the timing control board and multiple acquisition boards.

[0067] Specifically, the processing system side of the timing control board is connected to the processing system side of multiple acquisition boards via a data switch, and receives synchronization deviation information from each acquisition board through the data switch. After determining the deviation compensation information based on the synchronization deviation information, the timing control board distributes the deviation compensation information to each acquisition board through the data switch, so as to configure the deviation information of the acquisition channels in the multiple acquisition boards according to the deviation compensation information, so that the acquisition channels on the multiple acquisition boards can work synchronously, thereby putting the acquisition boards in a synchronized state.

[0068] It should be noted that in some cases, the number of acquisition boards is large, and direct connection between the timing control board and the acquisition boards may lead to messy wiring, increasing the complexity of the inter-board synchronization platform and thus affecting its maintainability. Furthermore, the acquisition boards may use different standard communication interfaces, further complicating the connection relationship between the timing control board and the acquisition boards. Considering the above reasons, this application sets up a data switch between the timing control board and multiple acquisition boards, enabling data exchange between them. This not only provides multi-standard interface support for the acquisition boards, ensuring that all acquisition boards can correctly exchange data, but also optimizes the wiring structure between the timing control board and the acquisition boards, improving the data exchange rate and reliability.

[0069] In some embodiments, the data switch can also be connected to a host computer, allowing users to control and manage data exchange within the inter-board synchronization platform, thereby improving the reliability of data exchange. Furthermore, users can manually intervene in the synchronization process within the inter-board synchronization platform via the host computer, enhancing the flexibility and reliability of the synchronization process and enabling the handling of special situations requiring manual intervention.

[0070] As one embodiment of this application, the data switch is used to transmit the synchronization deviation information of multiple acquisition boards to the timing control board after multiple acquisition boards are triggered by the synchronous trigger multiplexing signal.

[0071] Specifically, the synchronous trigger multiplexing signal contains different indication signals used to control each acquisition board to perform corresponding actions to synchronize the acquisition boards. Among these actions are synchronous deviation information acquisition triggering, which can be based on the synchronous trigger multiplexing signal to trigger each acquisition channel on multiple acquisition boards to acquire its own synchronous deviation information.

[0072] Furthermore, the synchronization trigger multiplexing signal is output to each acquisition board to control each acquisition board to trigger the acquisition of synchronization deviation information, thereby obtaining the synchronization deviation information of each acquisition board, and transmitting the synchronization deviation information to the timing control board. After receiving the synchronization deviation information, the timing control board performs timing synchronization correction on the acquisition boards according to the synchronization deviation information to ensure the timing synchronization status between the acquisition boards.

[0073] As one embodiment of this application, a timing control board is used to determine deviation compensation information and output the deviation compensation information to multiple acquisition boards through a data switch.

[0074] Specifically, the timing control board is also used to receive synchronization deviation information from each acquisition board. Upon receiving the synchronization deviation information, the timing control board performs calculations based on this information to determine the deviation compensation information. It should be noted that the deviation compensation information can be the target delay value or target phase value for each acquisition channel in multiple acquisition boards, used to configure the synchronization state of each acquisition board to correct the synchronization state of each acquisition channel in multiple acquisition boards, thereby improving the synchronization between the acquisition boards.

[0075] Furthermore, the timing control board distributes deviation compensation information to each acquisition board through a data switch, thereby configuring the deviation compensation information to the acquisition channels in multiple acquisition boards, enabling each acquisition channel on multiple acquisition boards to work synchronously, and thus ensuring that the acquisition boards are in a timing synchronization state.

[0076] As one embodiment of this application, the deviation compensation information is obtained by performing deviation compensation calculation based on the synchronization deviation information.

[0077] Specifically, after receiving the synchronization deviation information, the timing control board performs deviation compensation calculations based on the synchronization deviation information to determine the corresponding deviation compensation information. For example, when the synchronization deviation information is the channel delay value of each acquisition channel in the acquisition board, the deviation compensation calculation process may include: comparing the channel delay values ​​of each acquisition channel; if the channel delay values ​​corresponding to each acquisition channel are the same, it is determined that each acquisition board is already in a timing synchronization state and no synchronization deviation compensation is needed; if the channel delay values ​​corresponding to each acquisition channel are different, the largest channel delay value is taken from all channel delay values, and redundancy design is performed based on this channel delay value to obtain a target delay value, which is used as deviation compensation information to configure the synchronization state of each acquisition board.

[0078] As one embodiment of this application, in a bare-metal programming environment, the inter-board synchronization platform stores the corresponding physical addresses of registers in multiple acquisition boards.

[0079] Specifically, a bare-metal programming environment can be an environment without an operating system, meaning the inter-board synchronization platform runs directly on the hardware devices. Users manually control the hardware devices and other related equipment and need to manually configure the physical addresses of each hardware device. In this case, during the synchronization process of the inter-board synchronization platform, the user stores the physical addresses of the acquisition cards' registers in each acquisition card and directly accesses the hardware in the acquisition cards through the physical addresses of the registers.

[0080] As one embodiment of this application, in the operating system environment, the inter-board synchronization platform allows multiple acquisition boards to obtain the corresponding register physical addresses according to the integrated device tree.

[0081] Specifically, the operating system environment can be an environment supported by an operating system, meaning that hardware device management and resource allocation on the inter-board synchronization platform are handled by the operating system, and hardware device configuration and management are completed through device drivers and the operating system kernel. The integrated device tree can be a structure within the operating system used to describe hardware information, providing the operating system with information such as the device's physical address, interrupt requests, and input / output mappings. In this case, the user adds the physical addresses of the acquisition board's registers and related hardware resource information to the integrated device tree. During the synchronization process on the inter-board synchronization platform, the operating system reads the integrated device tree to identify the acquisition board based on the integrated register physical addresses and other information, thus enabling subsequent synchronization.

[0082] This application provides an RFSoC-based inter-board synchronization method, applicable to any of the above embodiments of the RFSoC-based inter-board synchronization platform.

[0083] Reference Figure 5 As shown, before using multiple acquisition boards to achieve multi-channel synchronous signal acquisition, the synchronization deviation information of each acquisition board is obtained through the timing control board. Based on this information, timing synchronization correction is performed on each acquisition board to improve the synchronization between them. It should be noted that the frequency synthesis board also generates the analog reference signal AMS_SYSREF and the logic reference signal PL_SYSREF, both of which are periodic clock signals used for synchronization processing of the acquisition boards. The analog reference signal AMS_SYSREF and the logic reference signal PL_SYSREF have the same clock frequency and a constant phase difference.

[0084] Specifically, timing synchronization correction can include board delay synchronization correction and board phase synchronization correction. The board delay synchronization correction process can include: enabling the clock signals required for board delay synchronization correction, including but not limited to reference clock signals, synchronous trigger multiplexing signals, analog reference signals, and logic reference signals, so that the aforementioned clock signals can be output periodically, stably, and continuously; performing status self-checks on the RFDCIP cores integrated with multiple acquisition channels in each acquisition board, including but not limited to module enable status checks, phase-locked loop status checks, power-on status checks, and channel enable status checks, to ensure that the RFDCIP cores are in normal working condition; calling the API function XRFdc_MultiConverter_Sync in each acquisition board to initialize the delay of each acquisition board; and using the analog reference signal AMS_SYSREF and the logic reference signal PL_SYSREF to automatically test the delay values ​​of each acquisition board to obtain the delay values ​​of each acquisition board. The system calculates the channel delay value for each acquisition channel on each acquisition board. If the channel delay values ​​for all acquisition channels are the same, the acquisition boards are considered to have completed delay synchronization, and the board delay synchronization correction process ends. If the channel delay values ​​for each acquisition channel are different, the largest channel delay value is selected from all channel delay values, and redundancy design is performed based on this channel delay value to obtain the target delay value Target_latency. The target delay value Target_latency is then allocated to each acquisition board, and the API function XRFdc_MultiConverter_Sync is called on each acquisition board to allocate the target delay value Target_latency to its acquisition channels, so that the channel delay value of each acquisition channel is set to the target delay value Target_latency, completing the board delay synchronization correction. For example, the redundancy design can be to add a delay of 16 clock cycles to the largest channel delay value.

[0085] Furthermore, the board phase synchronization correction process may include: calling the API function XRFdc_MTS_Sysref_Config to turn off the reference signal receivers of each acquisition board and stop receiving the analog reference signal AMS_SYSREF; turning off the output of the analog reference signal AMS_SYSREF until the clock output of the analog reference signal AMS_SYSREF completely disappears, ensuring that there is no interference or glitches in the output of the analog reference signal AMS_SYSREF, and improving the signal quality of the analog reference signal AMS_SYSREF; calling the API function XRFdc_SetMixerSettings to set the mixing trigger source of each acquisition board to the analog reference signal AMS_SYSREF; calling the API function XRFdc_MTS_Sysref_Config to turn on the reference signal receivers of each acquisition board, so that the acquisition channels in each acquisition board synchronously receive the analog reference signal AMS_SYSREF; capturing at least two cycles of the analog reference signal AMS_SYSREF, and repeatedly activating each board with the analog reference signal AMS_SYSREF in each cycle. The initial phase settings for the acquisition channels are as follows: Phase acquisition is performed on each acquisition channel to obtain the phase difference between them; Individual phase settings are applied to each acquisition channel based on the phase difference to compensate for the phase difference and ensure that all acquisition channels have the same phase; The API function XRFdc_MTS_Sysref_Config is called again to enable the reference signal receivers of each acquisition board, allowing the acquisition channels on each board to synchronously receive the analog reference signal AMS_SYSREF; At least two cycles of the analog reference signal AMS_SYSREF are captured, and the AMS_SYSREF signal in each cycle triggers phase synchronization of each acquisition channel, enabling phase compensation for each acquisition channel to take effect and align the phases of each acquisition channel; The API function XRFdc_MTS_Sysref_Config is called to disable the reference signal receivers of each acquisition board, stopping the reception of the analog reference signal AMS_SYSREF to lock the phase settings of each acquisition channel, ensuring phase synchronization between acquisition channels and, consequently, phase synchronization between acquisition boards.

[0086] In some embodiments, after completing the board delay synchronization correction and board phase synchronization correction, the channel phase difference between each acquisition channel in multiple acquisition boards can be obtained through a synchronous trigger multiplexing signal, and it can be determined whether the channel phase difference meets a preset stability condition. If the channel phase difference meets the preset stability condition, it indicates that the phase synchronization state between the acquisition boards is stable, and the inter-board synchronization process can be terminated. If the channel phase difference does not meet the preset stability condition, it indicates that the phase synchronization state between the acquisition boards is unstable. At this time, the board phase synchronization correction can be repeated for each acquisition board to ensure that the acquisition boards are in a stable phase synchronization state. For example, at least one cycle of the analog reference signal AMS_SYSREF is used in the board phase synchronization correction process.

[0087] Please see Figure 6 , Figure 6 This is a schematic diagram of a computer device according to an embodiment of this application. As shown in the figure, the computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 6 Take a processor 10 as an example.

[0088] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0089] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0090] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0091] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0092] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0093] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0094] One embodiment of this application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0095] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0096] The systems, apparatus, modules, or units described in the embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, a computer may be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0097] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0098] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0100] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0101] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0102] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0104] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0105] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An inter-board synchronization platform based on RFSoC, characterized in that, It includes a frequency integration board, a timing control board, and multiple acquisition boards, each of which contains multiple acquisition channels; wherein: The output terminal of the frequency integration board is connected to the input terminal of the timing control board and the input terminals of the multiple acquisition boards, respectively; the output terminal of the timing control board is connected to the input terminals of the multiple acquisition boards. The frequency integration board is used to output a reference clock signal to the timing control board and the plurality of acquisition boards; The timing control board is used to synchronously output a synchronization trigger multiplexing signal to the plurality of acquisition boards according to the reference clock signal, and to receive synchronization deviation information of the plurality of acquisition boards, and to perform timing synchronization correction on the plurality of acquisition boards according to the synchronization deviation information; wherein, the timing synchronization correction includes phase synchronization, and the phase synchronization process includes: triggering the plurality of acquisition channels to perform phase initialization with an analog reference signal in each cycle; obtaining the channel phase value of the plurality of acquisition channels and calculating the channel phase difference between the plurality of acquisition channels; when the channel phase difference between the plurality of acquisition channels is fixed, performing channel phase compensation on the plurality of acquisition channels respectively to align the channel phase values ​​of the plurality of acquisition channels; triggering the plurality of acquisition channels again with the analog reference signal in multiple cycles, so that the channel phase compensation of the plurality of acquisition channels takes effect, and realizing phase synchronization between channels; The multiple acquisition boards are used to synchronously execute corresponding actions based on the reference clock signal as a clock reference and the synchronous trigger multiplexing signal.

2. The inter-board synchronization platform according to claim 1, characterized in that, The length of the wiring connecting the timing control board to any of the multiple acquisition boards is the same, so that the synchronous trigger multiplexed signals output to the multiple acquisition boards are all in phase.

3. The inter-board synchronization platform according to claim 1, characterized in that, The synchronous trigger multiplexing signal controls the multiple acquisition boards to synchronously execute any one of the following actions: signal acquisition synchronous trigger, logic state reset trigger, and synchronous deviation information acquisition trigger.

4. The inter-board synchronization platform according to claim 1, characterized in that, The inter-board synchronization platform also includes a data switch, which is connected between the timing control board and the multiple acquisition boards.

5. The inter-board synchronization platform according to claim 4, characterized in that, The data switch is used to transmit the synchronization deviation information of the multiple acquisition boards to the timing control board after the multiple acquisition boards are triggered by the synchronization trigger multiplexing signal.

6. The inter-board synchronization platform according to claim 5, characterized in that, The timing control board is used to determine the deviation compensation information and output the deviation compensation information to the multiple acquisition boards through the data switch.

7. The inter-board synchronization platform according to claim 6, characterized in that, The deviation compensation information is obtained by performing deviation compensation calculations based on the synchronization deviation information.

8. The inter-board synchronization platform according to claim 1, characterized in that, In the bare-metal programming environment, the inter-board synchronization platform stores the corresponding physical addresses of registers in the multiple acquisition boards.

9. The inter-board synchronization platform according to claim 1, characterized in that, In the operating system environment, the inter-board synchronization platform allows the multiple acquisition boards to obtain the corresponding register physical addresses according to the integrated device tree.

10. A board-to-board synchronization method based on RFSoC, characterized in that, Applicable to the RFSoC-based inter-board synchronization platform according to any one of claims 1 to 9.

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