A chip design rule violation optimization method based on prediction probability

Abstract

The application belongs to the field of semiconductor chip design, and discloses a chip design rule violation optimization method based on prediction probability. First, a risk area distribution map of a chip layout is generated through a DRC violation prediction model, and the layout is divided into global routing units (GCell). Then, optimization is carried out in stages. First, coarse optimization is carried out by dynamically adjusting the forbidden area margin according to the risk level. Then, fine optimization is completed by optimizing white space allocation through a simulated annealing algorithm. Finally, legality is checked, and the optimization result is output. Through the prediction-driven hierarchical optimization strategy, the DRC violation correction efficiency is significantly improved. Through the dynamic margin setting and parallel processing technology, the process compatibility is ensured, and the layout disturbance is reduced. At the same time, through the risk area expansion optimization, hot spot transfer is effectively prevented, and the DRC violation rate is reduced. The application is suitable for large-scale chip design of advanced process nodes, and can significantly shorten the design cycle while ensuring the design quality.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor chip design, and particularly relates to a chip design rule violation optimization method based on prediction probability. BACKGROUND

[0002] With the continuous development of process nodes and the increasing size of chips, design rule checking (DRC) as a key means to ensure chip reliability and improve manufacturing yield, its importance is increasingly prominent. The traditional DRC process is usually carried out in the late stage of layout and routing, when a large number of DRC violations are detected, tedious correction work is often needed, and these corrections may have a significant impact on the layout, thereby causing the design cycle to be prolonged and the cost to be increased. Therefore, it is necessary to adopt a more efficient and flexible DRC optimization method to reduce the negative impact on design progress and cost, so as to improve the efficiency and quality of the overall design.

[0003] At present, although a variety of optimization methods for DRC violations have been proposed: for example, white space (White Space) optimization technology as an effective means, can improve the utilization rate of wiring resources by reasonably adjusting the distribution of white space without increasing the chip area, effectively alleviate the wiring congestion in the chip, improve the routability of the chip and the final wiring quality. Global routing optimization technology based on integer linear programming, by establishing decision variables, objective functions and constraint conditions, the chip routing problem is transformed into a mathematical problem to solve the mathematical model, reduces unnecessary wiring on the routing path, makes the wiring utilization more reasonable, optimizes the global routing result of the chip, and reduces the probability of local congestion and DRC violation.

[0004] However, the existing DRC violation optimization scheme has many limitations. First, the optimization speed is difficult to meet the actual demand. The existing optimization method has high dependence on computing resources, resulting in long optimization time, which is difficult to adapt to the requirements of fast iteration and high efficiency in chip design, thereby affecting the design efficiency. Secondly, the process compatibility is insufficient. Due to the great difference between DRC rules of different process nodes, the existing optimization strategy lacks sufficient flexibility and adaptability between different process nodes, making it difficult to achieve seamless switching and compatibility, which limits its wide application in various process environments. Finally, the optimization effort is insufficient. The existing optimization method has limited ability to correct DRC violations under the premise of minimizing the impact on chip layout and routing, often cannot completely solve the violation problem, resulting in that the optimization effect fails to meet the expectations, and it is difficult to fully meet the demand of improving chip design quality and reliability. Therefore, there is an urgent need for a new DRC optimization method, which can improve the optimization effect while considering optimization speed, process compatibility and layout disturbance control, etc., to adapt to the complexity and rapid development of modern chip design. SUMMARY

[0005] The present application aims to provide a chip design rule violation optimization method based on prediction probability to solve the above technical problems.

[0006] To solve the above technical problems, a specific technical solution of the chip design rule violation optimization method based on prediction probability is as follows:

[0007] A chip design rule violation optimization method based on prediction probability includes the following steps:

[0008] Step 1: System initialization and data preparation: load chip layout file and DRC rule, run DRC violation prediction model, generate risk area distribution map, and divide global routing unit GCell;

[0009] Step 2: DRC prediction-based coarse optimization: dynamically set the forbidden area margin of the standard unit according to the risk level to quickly and roughly improve the DRC result;

[0010] Step 3: DRC risk area distribution and optimization adjustment: optimization adjustment is performed on high-risk, medium-risk and adjacent areas;

[0011] Step 4: Fine tuning based on white space optimization: further optimize white space layout using simulated annealing algorithm;

[0012] Step 5: Legality check: check whether the adjusted layout meets the design rules;

[0013] Step 6: Output the final optimized layout result.

[0014] Further, the step 1 includes the following steps:

[0015] Step 1.1: Input data preparation: load chip layout design file and design rule check file, run DRC violation prediction model, generate DRC violation probability distribution map of each area in the chip layout, and mark areas of different risk levels;

[0016] Step 1.2: Divide global routing unit GCell: divide the chip layout into uniform global routing unit GCell, ensuring that each standard unit completely belongs to a certain grid interval.

[0017] Further, the DRC violation probability distribution map of step 1.1 marks the area as high-risk, medium-risk, low-risk and no-risk, corresponding to different color marks.

[0018] Further, the step 1.2 divides the chip layout into 256x256 grids, forming 255² independent 2x2 grid intervals, and the boundary grid is ignored in subsequent adjustment.

[0019] Further, the step 2 comprises the following steps:

[0020] Step 2.1: Dynamic setting of forbidden zone margin: dynamically setting the forbidden zone margin of the standard cell according to the global routing unit GCell of different risk levels;

[0021] Step 2.2: Comprehensive judgment and adjustment: if a standard cell belongs to multiple GCells, comprehensively considering the risk level and layout influence of the GCell where the standard cell is located, taking the maximum forbidden zone margin as the final value, and skipping the area with unreasonable innate layout.

[0022] Further, the step 2.1 dynamic setting rule of forbidden zone margin is as follows:

[0023] High-risk GCell: 50% of the width of the standard cell;

[0024] Medium-risk GCell: 25% of the width of the standard cell;

[0025] Low-risk or no-risk GCell: no forbidden zone margin is set;

[0026] Further adjusting the forbidden zone margin of the standard cell according to the pin number and fan-out number of the standard cell: for the standard cell with high pin number or high fan-out number, further increasing the forbidden zone margin; otherwise, decreasing the forbidden zone margin.

[0027] Further, the step 4 comprises the following steps:

[0028] Step 4.1: Fixing the position of key cells: processing all macro cells and layout congestion, fixing the left and right nearest standard cells in the horizontal direction, and fixing the leftmost and rightmost standard cells in each row in the chip;

[0029] Step 4.2: Dividing parallel processing set: dividing the 255² grid intervals into a set of non-adjacent 2×2 grid intervals, using parallel processing algorithm, i.e. multi-threading to optimize the GCells in different grid intervals at the same time;

[0030] Step 4.3: Simulated annealing optimization: performing simulated annealing optimization on the standard cells in each 2×2 grid interval.

[0031] Further, the step 4.3 comprises the following steps:

[0032] Step 4.3.1: Calculating the total length of the white space and the divisible shares;

[0033] Step 4.3.2: Generating a new solution: randomly adjusting the white space allocation;

[0034] Step 4.3.3: Calculate the RUDY value of the new solution, if the RUDY value is reduced, accept the new solution, and obtain the white space allocation optimal solution; otherwise, accept the suboptimal solution with a set probability.

[0035] Step 4.3.4: Repeat the iteration multiple times for each 2x2 grid interval set until the global optimal solution is converged.

[0036] Further, the step 5 legality check is realized by the standard cell legalization function of the commercial APR tool.

[0037] The chip design rule violation optimization method based on prediction probability has the following advantages:

[0038] High optimization efficiency

[0039] By identifying high-risk areas in advance through the DRC violation prediction model and adopting a phased optimization (coarse adjustment + fine adjustment) strategy, the blindness and computational complexity of traditional DRC correction are significantly reduced, and the overall optimization time is shortened.

[0040] By using parallel processing set partitioning and simulated annealing algorithm, multi-thread efficient optimization is realized, which is especially suitable for large-scale chip design scenarios.

[0041] Strong process compatibility

[0042] The dynamic forbidden zone margin setting and risk area hierarchical optimization mechanism can flexibly adapt to the differences in DRC rules of different process nodes, without the need to redesign the optimization process, thereby improving the universality of the method.

[0043] Significant optimization effect

[0044] By combining coarse adjustment (forbidden zone margin adjustment) and fine adjustment (white space optimization), not only the problem of insufficient optimization effort in the prior art is solved, but also DRC hotspots are effectively prevented from shifting, and the violation rate is significantly reduced.

[0045] By fixing the key cell position and legality check, it is ensured that the optimized layout not only meets the design rules, but also maintains the performance and reliability of the original design.

[0046] Small layout disturbance

[0047] In the optimization process, high-risk areas are prioritized, and low-risk areas are only fine-tuned, thereby minimizing the disturbance to the original layout and avoiding performance fluctuations caused by global adjustment in traditional methods.

[0048] Good scalability

[0049] The GCell division, parallel processing set and other design support modules in the method support modular expansion, can be easily integrated into an existing EDA tool chain, and provide a technical basis for subsequent more complex optimization requirements.

[0050] In summary, the chip design rule violation optimization method based on prediction probability is superior to the traditional method in terms of optimization speed, process compatibility, correction effect and layout stability, and can significantly improve the efficiency and quality of chip design and reduce manufacturing cost. BRIEF DESCRIPTION OF DRAWINGS

[0051] Figure 1 The chip design rule violation optimization method based on prediction probability is based on the overall flowchart of the chip design rule violation optimization method based on prediction probability.

[0052] Figure 2 The flowchart of the coarse adjustment strategy based on DRC violation prediction is based on the flowchart of the coarse adjustment strategy based on DRC violation prediction.

[0053] Figure 3 The DRC risk area distribution and optimization adjustment diagram is based on the DRC risk area distribution and optimization adjustment diagram.

[0054] Figure 4 The flowchart of the fine adjustment strategy based on white space optimization is based on the flowchart of the fine adjustment strategy based on white space optimization. DETAILED DESCRIPTION

[0055] In order to better understand the purpose, structure and function of the present application, the chip design rule violation optimization method based on prediction probability is described in detail below in combination with the drawings.

[0056] As shown in Figure 1 The chip design rule violation optimization method based on prediction probability comprises the following steps:

[0057] Step 1: system initialization and data preparation: load chip layout file and DRC rule, run DRC violation prediction model, generate risk area distribution diagram, and divide global routing unit (GCell);

[0058] Step 1.1: input data preparation:

[0059] Load the chip layout design file, including standard cells, macro cells, routing information, etc.

[0060] Load the design rule check file (DRC rule) to clearly specify the specific requirements of the current process node.

[0061] Run the DRC violation prediction model to generate a DRC violation probability distribution diagram for each region in the chip layout, and mark the high-risk (red), medium-risk (orange), low-risk (green) and no-risk (gray) regions.

[0062] Step 1.2: divide global routing unit (GCell):

[0063] The chip layout is divided into uniform 256x256 grid points, forming 255² independent 2x2 grid point intervals. Among them, the boundary grid points are mainly used as wiring channels due to the extremely low proportion of standard cells, so the subsequent white space adjustment of the boundary grid points can be ignored. This division method ensures that each standard cell completely belongs to a grid point interval, avoiding the confusion problem of white space adjustment caused by the division of standard cells in multiple intervals.

[0064] Step 2: Coarse optimization based on DRC prediction: dynamically set the forbidden zone margin of the standard cell according to the risk level, quickly and roughly improve the DRC result, as shown in Figure 2 as follows:

[0065] Step 2.1: Dynamic setting of forbidden zone margin:

[0066] According to the DRC prediction result, for the global routing unit (GCell) in different risk areas, different forbidden zone margins are set for the standard cells in it, thereby optimizing the spacing between standard cells near the hot spot area, realizing the priority optimization of high-risk areas, and reasonable adjustment of low-risk areas to improve area utilization.

[0067] High-risk GCell: 50% of the width of the standard cell.

[0068] Medium-risk GCell: 25% of the width of the standard cell.

[0069] Low-risk or no-risk GCell: No forbidden zone margin is set.

[0070] According to the number of pins and the number of fanouts of the standard cell, further adjust the forbidden zone margin of the standard cell. For example: for standard cells with high pin count or high fanout count, further increase the forbidden zone margin; otherwise, reduce it.

[0071] Step 2.2: Comprehensive judgment and adjustment:

[0072] If a standard cell belongs to multiple GCells, consider the risk level and layout influence of the GCell it belongs to, and take the maximum forbidden zone margin as the final value.

[0073] Skip the area with unreasonable layout (such as narrow channel between macro cells), and suggest the designer to optimize the layout from a macro perspective to fundamentally solve the DRC violation problem and enhance the rationality and reliability of chip design.

[0074] Step 3: DRC risk area distribution and optimization adjustment: optimize and adjust the high-risk, medium-risk and adjacent areas to prevent DRC hot spots from moving;

[0075] Not only the high-risk and medium-risk areas are optimized, but also the edge areas adjacent to the high-risk areas are optimized. As shown in Figure 3 , the red grid points represent high-risk areas, the orange grid points represent medium-risk areas, the green grid points represent low-risk areas with high-risk areas in the surrounding, and the gray grid points represent low-risk areas with no high-risk areas in the surrounding. In order to prevent the transfer of DRC hotspots, the coarse adjustment operation is not only performed on the red and orange areas, but also appropriately adjusted on the green area to ensure that all potential risk areas are effectively optimized and the optimization efficiency is improved.

[0076] Step 4: Fine adjustment based on white space optimization: further optimize the white space layout using simulated annealing algorithm to improve optimization efficiency and effect. As shown in Figure 4 , the following steps are included:

[0077] Step 4.1: Fix the position of key cells:

[0078] All macro cells and layout congestion are processed to fix the left and right nearest standard cells in the horizontal direction, and at the same time, the leftmost and rightmost standard cells in each row within the chip are fixed. This step not only reduces the impact on macro cells, IO signal pins or ports, but also prevents the occurrence of too dense standard cell columns in each column on the left and right sides of macro cells, layout congestion or each row of the chip, thereby leaving appropriate space for signal routing.

[0079] Step 4.2: Divide parallel processing sets:

[0080] The 255² grid point intervals are divided into a number of non-adjacent 2×2 grid point interval sets for subsequent set division strategy. Since the grid point intervals in each set are not directly adjacent, when processing the 2×2 grid point intervals in each set simultaneously, the standard cells will not affect each other, thereby ensuring the effectiveness of the set division strategy. By dividing the non-adjacent 2×2 grid point interval sets, using parallel processing algorithm, i.e. multi-threading to optimize GCell in different grid point intervals simultaneously, not only improves the optimization efficiency, but also ensures the global consistency of the chip after DRC optimization, effectively avoids the local optimal problem, thereby improving the overall optimization effect.

[0081] Step 4.3: Simulated annealing optimization:

[0082] The following steps are performed on the standard cell horizontal row (Row) in each 2×2 grid point interval:

[0083] Step 4.3.1: Calculate the total length of the current white space and the number of divisible shares. When dividing the shares, through the simulated annealing algorithm, the positions of the fixed standard cells, the head and tail standard cells in the Row, and the layout information and connection relationship of each standard cell are considered to generate a new solution.

[0084] Step 4.3.2: Generate new solution: randomly adjust white space allocation (increase or decrease by a certain value).

[0085] Step 4.3.3: Calculate RUDY value (Rectangular Uniform Density of Y) of new solution, if RUDY value is reduced, accept new solution and get the optimal solution of white space allocation; otherwise, accept suboptimal solution with a certain probability (simulated annealing mechanism).

[0086] Step 4.3.4: Repeat the iteration for each 2x2 grid interval set multiple times (the number of times is pre-set according to the process and design scale), until the global optimal solution is converged.

[0087] Step 5: Legality check:

[0088] Use the standard cell legalization function of the commercial APR tool to check whether the adjusted layout meets the design rules.

[0089] Step 6: Output the final optimized layout result.

[0090] It can be understood that the present application is described through some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to these features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, these features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

Claims

1. A chip design rule violation optimization method based on predicted probability, characterized in that, Package the following steps: Step 1: System initialization and data preparation: Load the chip layout file and DRC rules, run the DRC violation prediction model, generate a risk area distribution map, and divide the global routing unit (GCell); Step 2: Coarse-tuning optimization based on DRC prediction: Dynamically set the forbidden zone margin of the standard cell according to the risk level to quickly and coarsely improve the DRC results; Step 3: Distribution and Optimization of DRC Risk Areas: Optimize and adjust high-risk, medium-risk areas and their adjacent areas; Step 4: Fine-tuning based on white space optimization: Further optimize the white space layout using simulated annealing algorithm; Step 5: Legality Check: Check whether the adjusted layout conforms to the design rules; Step 6: Output the final optimized layout result.

2. The chip design rule violation optimization method based on predicted probability according to claim 1, characterized in that, Step 1 includes the following steps: Step 1.1: Input data preparation: Load the chip layout design file and design rule check file, run the DRC violation prediction model, generate the DRC violation probability distribution map of each region in the chip layout, and mark the regions with different risk levels; Step 1.2: Divide the global routing unit GCell: Divide the chip layout into uniform global routing units GCell, ensuring that each standard cell belongs to a certain grid interval.

3. The chip design rule violation optimization method based on predicted probability according to claim 2, characterized in that, The DRC violation probability distribution map in step 1.1 marks the areas as high risk, medium risk, low risk, and no risk, each corresponding to a different color label.

4. The chip design rule violation optimization method based on predicted probability according to claim 2, characterized in that, Step 1.2 divides the chip layout into 256×256 grid points, forming 255² independent 2×2 grid point intervals, with boundary grid points ignored for subsequent adjustments.

5. The chip design rule violation optimization method based on predicted probability according to claim 1, characterized in that, Step 2 includes the following steps: Step 2.1: Dynamic setting of forbidden zone margin: Dynamically set the forbidden zone margin of the standard unit according to the global cabling unit (GCell) with different risk levels; Step 2.2: Comprehensive Judgment and Adjustment: If a standard cell belongs to multiple GCells, the risk level and layout impact of the GCell in which it belongs are comprehensively considered, the maximum forbidden zone margin is taken as the final value, and areas with inherently unreasonable layouts are skipped.

6. The chip design rule violation optimization method based on predicted probability according to claim 5, characterized in that, The rules for dynamically setting the boundary distance of the prohibited area in step 2.1 are as follows: High-risk GCell: 50% of the standard cell width; Medium-risk GCell: 25% of the standard cell width; Low-risk or no-risk GCell: No forbidden zone margins set; The forbidden zone margin of the standard cell is further adjusted based on the number of pins and the number of fan-outs: for standard cells with a high number of pins or a high number of fan-outs, the forbidden zone margin is further increased; otherwise, it is decreased.

7. The chip design rule violation optimization method based on predicted probability according to claim 1, characterized in that, Step 4 includes the following steps: Step 4.1: Fix the position of key cells: process all macro cells and layout congestion, fix the nearest standard cells in the horizontal direction, and fix the leftmost and rightmost standard cells in each row of the chip. Step 4.2: Divide the grid intervals into parallel processing sets: Divide the 255² grid intervals into several sets of non-adjacent 2×2 grid intervals, and use parallel processing algorithms, i.e., multi-threaded optimization of GCells in different grid intervals at the same time. Step 4.3: Simulated Annealing Optimization: Perform simulated annealing optimization on the standard cell horizontal row within each 2×2 grid interval.

8. The chip design rule violation optimization method based on predicted probability according to claim 7, characterized in that, Step 4.3 includes the following steps: Step 4.3.1: Calculate the total length of the current white space and the number of parts it can be divided into; Step 4.3.2: Generate a new solution: Randomly adjust the white space allocation; Step 4.3.3: Calculate the RUDY value of the new solution. If the RUDY value decreases, accept the new solution and obtain the optimal solution for white space allocation; otherwise, accept the suboptimal solution with a set probability. Step 4.3.4: For each set of 2×2 grid points, repeat the iteration multiple times until convergence to the global optimum.

9. The chip design rule violation optimization method based on predicted probability according to claim 1, characterized in that, The legality check in step 5 is performed using the standard unit legalization function of commercial APR tools.

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