A method and apparatus for detecting edge defects in silicon wafers under a special chamfering process

Abstract

This invention discloses a method and apparatus for detecting edge defects in silicon wafers under a special chamfering process, relating to the field of semiconductor manufacturing technology. The method includes: acquiring an edge image of a defect-free silicon wafer under a special chamfering process; using its multi-layer, multi-scale features in a pre-trained WideResNet50 as supervision, and obtaining an edge feature tensor through spatial unification, channel stitching, and residual compression; training and freezing an autoencoder using this tensor as the target, and then training a convolutional neural network using the encoder output as supervision; subsequently, using the autoencoder with frozen parameters and the trained convolutional neural network to perform edge defect detection on the image under test, obtaining two sets of defect feature maps; generating a defect feature map by calculating the pixel-by-pixel differences between the two sets of feature maps in the channel, width, and height dimensions, and mapping it to a defect score; highlighting and locating defect areas based on the defect score, and outputting the silicon wafer edge defect detection result. This method effectively solves the problem of insufficient defect labels in industrial settings.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method and apparatus for detecting edge defects in silicon wafers under a special chamfering process. Background Technology

[0002] Edge chamfering of silicon wafers is a critical mechanical process in semiconductor wafer manufacturing. In the initial stage, after silicon ingots are cut into wafers, the wafer edges are typically sharp and rough, which not only affects subsequent processing steps but also increases the risk of wafer breakage. Chamfering reshapes these rough edges into smooth, curved surfaces, thereby enhancing the mechanical strength of the wafer edges and effectively preventing cracks caused by stress generated during handling, cleaning, or heat treatment. This lays a solid foundation for subsequent polishing, high-temperature oxidation, and other processes. While edge chamfering is crucial for improving the overall quality of silicon wafer manufacturing, the process itself can introduce new defects. In detecting edge defects on silicon wafers after chamfering, the size variations of silicon wafer defects are extremely wide, ranging from large-area cracks to tiny scratches, posing a significant challenge to defect detection.

[0003] In existing technologies, due to the high diversity of defects at the edges of silicon wafers, and the possibility of previously unseen rare defects in silicon wafer production lines, it is difficult to collect and label comprehensive data covering all possible defects. Existing supervised learning detection algorithms are ill-equipped to handle these issues, resulting in insufficient accuracy in silicon wafer defect detection to support practical engineering needs.

[0004] Therefore, there is an urgent need for a silicon wafer edge defect detection method to effectively improve the accuracy of silicon wafer defect detection without requiring image labels. Summary of the Invention

[0005] Therefore, it is necessary to provide a method and apparatus for detecting edge defects in silicon wafers under a special chamfering process to address the aforementioned technical problems.

[0006] The present invention adopts the following technical solution:

[0007] This invention provides a method for detecting edge defects in silicon wafers under a special chamfering process, comprising:

[0008] Acquire images of the edge of a defect-free silicon wafer under a special chamfering process with double 45-degree edges;

[0009] Using a pre-trained WideResNet50 network as the backbone network, multiple multi-scale feature maps of the defect-free silicon wafer edge image are extracted from the outputs of the first and second residual modules in the backbone network. The multi-scale feature maps are then stitched together along the channel dimension after unifying their spatial dimensions, and residual feature compression is performed on the stitched multi-scale feature maps to obtain the silicon wafer edge feature tensor.

[0010] The silicon wafer edge feature tensor is used as the first supervision target to train the autoencoder, and all parameters of the trained autoencoder are frozen. The image of the defect-free silicon wafer is processed using the autoencoder with frozen parameters to obtain the output feature map. The output feature map is used as the second supervision target to train the convolutional neural network.

[0011] An autoencoder with frozen parameters and a trained convolutional neural network are used to detect edge defects in the silicon wafer image under test, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map. The silicon wafer edge defect detection result is determined based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0012] Preferably, obtaining an edge image of a defect-free silicon wafer under a special chamfering process specifically includes:

[0013] After the wafer is adsorbed and positioned in the center and horizontally calibrated and oriented, the edge of the wafer is stably illuminated by a ring light source.

[0014] By using dual CCD linear array cameras symmetrically arranged on the top and bottom sides of the wafer and scanning at a fixed frequency, high-resolution images of the top and bottom 45-degree edges of the silicon wafer after chamfering are continuously acquired, resulting in defect-free silicon wafer edge images.

[0015] Preferably, residual feature compression is performed on the spliced ​​multi-scale feature map to obtain the silicon wafer edge feature tensor, specifically including:

[0016] The spliced ​​multi-scale feature maps are sequentially activated by 1×1 convolution, batch normalization and ReLU activation function to obtain the first silicon wafer edge feature tensor.

[0017] The spliced ​​multi-scale feature maps are sequentially processed through 3×3 convolution, batch normalization, ReLU activation function activation, 3×3 convolution and batch normalization to obtain the edge feature tensor of the second silicon wafer;

[0018] The silicon wafer edge feature tensor is obtained by concatenating the first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor.

[0019] Preferably, the spatial dimensions of the multi-scale feature maps are unified using a bilinear interpolation method.

[0020] Preferably, the loss function used when training the convolutional neural network is:

[0021] ;

[0022] In the formula, L AS To train the loss function of the convolutional neural network, C, W, HThese represent the number of channels, width, and height of the feature map, respectively. S ( I The output of the convolutional neural network is . A ( I ( ) represents the output feature map of the autoencoder after freezing the parameters. μ c A The channel mean of the output features of the automatic encoder. σ c A The channel standard deviation of the output characteristics of the auto encoder.

[0023] Preferably, the silicon wafer edge defect detection result is determined based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map, specifically including:

[0024] Calculate the pixel-by-pixel differences between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions, and map them to defect scores;

[0025] Based on the defect score, determine the edge defect feature map of the silicon wafer image under test; based on the edge defect feature map, determine the edge defect detection result of the silicon wafer.

[0026] Preferably, the formula for calculating the pixel-by-pixel differences in the channel, width, and height dimensions of the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map, and mapping them to the defect score, is as follows:

[0027] ;

[0028] ;

[0029] In the formula, M AS S represents the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions. AS Let C represent the defect score of the silicon wafer image to be inspected, and let C, W, and H represent the number of channels, width, and height of the silicon wafer edge defect feature map, respectively. S(I) and A(I) represent the outputs of the convolutional neural network and the autoencoder, respectively, i.e., the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. μ A The channel mean of the output features of the automatic encoder. σ A The channel standard deviation of the output characteristics of the auto encoder.

[0030] Preferably, the edge defect feature map of the silicon wafer image under test is determined based on the defect score, specifically including:

[0031] When the defect score is greater than the preset threshold, it indicates that the silicon wafer image under test has edge defects, and the image is identified as an edge defect feature map; otherwise, it indicates that the silicon wafer image under test does not have edge defects.

[0032] Preferably, the defective portion of the silicon wafer edge defect feature map is highlighted in white, while the remaining portion is black; the step of determining the silicon wafer edge defect detection result based on the silicon wafer edge defect feature map specifically includes:

[0033] Based on the highlighted positioning areas of the defect portion in the silicon wafer edge defect feature map, the position, size, and shape of the highlighted positioning areas on the silicon wafer edge defect feature map are statistically analyzed, which is the silicon wafer edge defect detection result.

[0034] This invention provides a device for detecting edge defects in silicon wafers under a special chamfering process, comprising:

[0035] The data acquisition module is used to acquire edge images of defect-free silicon wafers under a special chamfering process with double 45-degree edges;

[0036] The feature compression module is used to extract multiple multi-scale feature maps of the defect-free silicon wafer edge image from the output of the first set of residual modules and the second set of residual modules in the backbone network using the pre-trained WideResNet50 network as the backbone network; after unifying the spatial size of the multi-scale feature maps, they are stitched along the channel dimension, and residual feature compression is performed on the stitched multi-scale feature maps to obtain the silicon wafer edge feature tensor.

[0037] The model training module uses the silicon wafer edge feature tensor as the first supervision target to train the autoencoder and freezes all parameters of the trained autoencoder; it then uses the autoencoder with frozen parameters to process the defect-free silicon wafer image to obtain the output feature map; and finally uses the output feature map as the second supervision target to train the convolutional neural network.

[0038] The defect detection module is used to perform edge defect detection on the silicon wafer image under test using an autoencoder with frozen parameters and a trained convolutional neural network, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and to determine the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0039] The present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the above-described method for detecting edge defects in silicon wafers under a special chamfering process.

[0040] The present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the above-mentioned method for detecting edge defects of silicon wafers under a special chamfering process.

[0041] The above-mentioned at least one technical solution adopted in this invention can achieve the following beneficial effects:

[0042] In the silicon wafer edge defect detection method provided by this invention under a special chamfering process, an autoencoder can reconstruct the defect location of anomaly images on a test set, while the reconstruction capability of a convolutional neural network cannot generalize to unknown anomaly patterns. The comparison of the output feature maps of the two can detect defects. Even without any defect labels in advance, it can still efficiently and accurately distinguish between defective images and normal images and output a defect feature map. This feature map contains the location, size, and shape of the defect and can detect defects of different sizes simultaneously. Even when only normal silicon wafer images are used for model training, it can still efficiently and reliably detect abnormal silicon wafer images and defect information of different shapes and sizes. This achieves unsupervised detection of silicon wafer edge defects and effectively solves the problem of insufficient silicon wafer edge defect labels under the chamfering process in industrial settings, thereby effectively improving the detection accuracy of silicon wafer defects under the chamfering process. Attached Figure Description

[0043] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0044] Figure 1 A schematic flowchart illustrating a silicon wafer edge defect detection method under a special chamfering process provided by the present invention;

[0045] Figure 2 A schematic diagram of residual feature compression for a silicon wafer edge defect detection method under a special chamfering process provided by the present invention;

[0046] Figure 3 A schematic diagram of the training of the convolutional neural network and autoencoder for a silicon wafer edge defect detection method under a special chamfering process provided by the present invention;

[0047] Figure 4 This is a schematic diagram of a silicon wafer edge defect detection device under a special chamfering process provided by the present invention;

[0048] Figure 5 A schematic diagram of a computer device for implementing a method for detecting edge defects in silicon wafers under a special chamfering process, as provided by the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in the specification without creative effort are within the scope of protection of this application.

[0050] In high-precision semiconductor manufacturing, a widely used chamfering method is the double 45-degree edge chamfering process. In this process, approximately 45-degree bevels are applied between the top and bottom surfaces of the wafer to ensure a smooth transition around the wafer edges.

[0051] Current industry practices for detecting edge defects after silicon wafer chamfering rely on manual visual inspection, which is inefficient and lacks accuracy. This invention, based on computer vision and deep learning technologies in artificial intelligence, provides an efficient and reliable digital solution for unsupervised defect detection of high-resolution wafer edge images, demonstrating powerful anomaly detection, localization, and segmentation capabilities. Simultaneously, the lightweight nature of this solution makes it easy to deploy on industrial production lines. The unsupervised AI nature of this solution allows it to detect rare or unseen defects without relying on existing defect labels, overcoming the challenges of data scale and label scarcity.

[0052] Existing intelligent defect recognition technologies struggle to cover both large and small defects using a single framework. They often require more complex model architectures to address different defect scales, resulting in a large number of model parameters that are difficult to deploy at the edge of industrial scenarios.

[0053] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0054] Figure 1 This is a schematic diagram of a silicon wafer edge defect detection method under a special chamfering process according to the present invention, which specifically includes the following steps:

[0055] S101: Obtain an image of the edge of a defect-free silicon wafer under a special chamfering process with double 45-degree edges.

[0056] Optionally, obtaining defect-free silicon wafer edge images under a special chamfering process includes: after the wafer is adsorbed and positioned at the center and horizontally calibrated and angularly oriented, the wafer edge is stably illuminated by a ring light source; using a dual CCD linear array camera symmetrically arranged on the upper and lower sides of the wafer and scanning at a fixed frequency, high-resolution images of the upper and lower 45-degree edges of the silicon wafer after chamfering are continuously acquired to obtain defect-free silicon wafer edge images under a special chamfering process.

[0057] Specifically, a silicon wafer edge imaging system is used to acquire the required image data. This system, through the synergy of a wafer adsorption platform and a groove alignment module, ensures the accuracy of wafer centering, horizontal calibration, and angular orientation. Operating under stable illumination provided by a ring light source, the system uses a dual CCD linear array camera arranged symmetrically at the top and bottom for fixed-frequency scanning, capturing high-resolution images of the chamfered wafer's top and bottom 45-degree edges. First, edge images from eight anomaly-free wafers are acquired, each containing approximately 150 high-resolution images (768×10000 pixels), resulting in eight anomaly-free datasets. Two of these datasets are used for the information distillation step, transferring knowledge from the backbone network to the autoencoder network, while the other two are used to train the autoencoder-convolutional neural network architecture. The remaining four anomaly-free datasets, along with four additional datasets each containing approximately 150 defective images acquired during wafer manufacturing, constitute four test sets for model performance evaluation. This design rigorously implements a separation mechanism between distillation, training, and testing, ensuring the reliability of model performance evaluation.

[0058] S102: Using a pre-trained WideResNet50 network as the backbone network, extract multiple multi-scale feature maps from the first and second residual modules of the defect-free silicon wafer edge image in the backbone network; after unifying the spatial size of the multi-scale feature maps, stitch them along the channel dimension, and perform residual feature compression on the stitched multi-scale feature maps to obtain the silicon wafer edge feature tensor.

[0059] The spatial dimensions of the multi-scale feature maps are unified using a bilinear interpolation method.

[0060] Optionally, residual feature compression is performed on the stitched multi-scale feature map to obtain the silicon wafer edge feature tensor. Specifically, this includes: sequentially activating the stitched multi-scale feature map through 1×1 convolution, batch normalization, and ReLU activation function to obtain the first silicon wafer edge feature tensor; sequentially activating the stitched multi-scale feature map through 3×3 convolution, batch normalization, ReLU activation function, 3×3 convolution, and batch normalization to obtain the second silicon wafer edge feature tensor; and stitching the first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor together to obtain the silicon wafer edge feature tensor.

[0061] Specifically, the WideResNet50 residual network is used as the backbone network, and the outputs of its intermediate layers are extracted for training the autoencoder network, such as... Figure 2As shown, this process achieves knowledge distillation from the rich feature information of the backbone network to an autoencoder network with a relatively simple architecture. All input images in this step are defect-free. Specifically, this processing step involves: extracting the target intermediate layers of the backbone network, taking layers 1 and 2 as an example; using bilinear interpolation to unify the size of the output feature maps; and then concatenating the feature maps of different intermediate layers along the channel dimension after size adjustment. The concatenated data is then processed as follows... Figure 2 The feature compression module shown contains a residual structure consisting of a 1×1 convolutional block and a 3×3 convolutional block. This module can improve the representation quality of intermediate features and enhance the stability of training in subsequent steps. The goal of the autoencoder in this step is to learn the intermediate layers of the backbone network after the feature compression module, and the loss function is the mean squared error (MSE).

[0062] S103: Use the silicon wafer edge feature tensor as the first supervision target to train the autoencoder and freeze all parameters of the trained autoencoder; use the autoencoder with frozen parameters to process the defect-free silicon wafer image to obtain the output feature map; use the output feature map as the second supervision target to train the convolutional neural network.

[0063] Optionally, the loss function used when training the convolutional neural network is:

[0064] ;

[0065] In the formula, L AS To train the loss function of the convolutional neural network, C, W, H These represent the number of channels, width, and height of the feature map, respectively. S ( I The output of the convolutional neural network is . A ( I ( ) represents the output feature map of the autoencoder after freezing the parameters. μ c A The channel mean of the output features of the automatic encoder. σ c A The channel standard deviation of the output characteristics of the auto encoder.

[0066] S104: Use the autoencoder with frozen parameters and the trained convolutional neural network to perform edge defect detection on the silicon wafer image under test, respectively, to obtain the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map; determine the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0067] Optionally, the silicon wafer edge defect detection result is determined based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. Specifically, this includes: calculating the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions and mapping it to a defect score; determining the edge defect feature map of the silicon wafer image under test based on the defect score; and determining the silicon wafer edge defect detection result based on the edge defect feature map.

[0068] Optionally, the formula for calculating the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions is as follows:

[0069] ;

[0070] ;

[0071] In the formula, M AS S represents the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width, and height dimensions. AS Let C represent the defect score of the silicon wafer image to be inspected, and let C, W, and H represent the number of channels, width, and height of the silicon wafer edge defect feature map, respectively. S(I) and A(I) represent the outputs of the convolutional neural network and the autoencoder, respectively, i.e., the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map. μ A The channel mean of the output features of the automatic encoder. σ A The channel standard deviation of the output characteristics of the auto encoder.

[0072] Optionally, the silicon wafer edge defect detection results include: the location, size, and shape of the defect on the image of the silicon wafer under test.

[0073] Optionally, the edge defect feature map of the silicon wafer image under test is determined based on the defect score. Specifically, when the defect score is greater than a preset threshold, it indicates that the silicon wafer image under test has an edge defect, and the image is determined as an edge defect feature map; otherwise, it indicates that the silicon wafer image under test does not have an edge defect.

[0074] Specifically, since this scheme is an unsupervised learning scheme, there is no fixed defect score threshold. The model's evaluation criterion is based on AUROC (Area Under the Receiver Operating Characteristic curve). In practical applications, the point on the ROC curve that is closest to the top left corner is taken as the optimal threshold for judging whether the image is defective or not during inference. This value will vary depending on the dataset.

[0075] Defect identification is performed using a contrastive learning architecture of an autoencoder and a convolutional neural network. A model with strong image reconstruction capabilities, such as an autoencoder, is introduced and contrasted with a regular convolutional neural network, which has relatively weaker reconstruction capabilities. For an autoencoder trained with knowledge distillation, even when processing anomalous inputs, its output feature map remains consistent with the feature map generated from normal samples. In contrast, the regular convolutional neural network, due to its weaker reconstruction capabilities, lacks the ability to generalize to unknown anomalous patterns. Therefore, when processing anomalous images, the outputs of the autoencoder and the convolutional neural network will show significant differences, and this difference can serve as a basis for anomaly detection. Figure 3 As shown, the parameters of the autoencoder network after knowledge freezing and distillation are displayed. The network parameters remain constant throughout the process. Using a normal, defect-free silicon wafer edge image as input, the mean and standard deviation of the autoencoder output feature map at the channel level are first calculated, and the output feature map is then normalized. A convolutional neural network is trained using the processed autoencoder output feature map as the target.

[0076] Specifically, the trained autoencoder-convolutional neural network contrastive learning architecture can be used for image defect detection. Given a test dataset of silicon wafer edge images (a mixture of normal and defective images), the architecture can distinguish between normal and defective images and highlight defective regions. In the defect feature map, defective regions at the silicon wafer edges are highlighted in white, while other areas are black, to show the location, shape, and size of the defects, thus segmenting normal and defective regions.

[0077] An Autoencoder-CNN contrastive learning framework. This framework uses the feature map output by the autoencoder after distillation as a basis, and trains a convolutional neural network to reconstruct this feature map. This training step only requires normal, defect-free images and does not require manual defect labels. After training, the autoencoder in this framework can reconstruct defective areas in anomalous images on a test set, while the reconstruction capability of the convolutional neural network cannot generalize to unknown anomalous patterns. The comparison of the output feature maps of the two can detect defects.

[0078] This embodiment can efficiently and accurately distinguish between defective images and normal images even without prior knowledge of any defect labels, and output a defect feature map containing the location, size, and shape of the defect. This method can simultaneously detect defects of different sizes. Furthermore, existing intelligent defect recognition technologies struggle to cover both large and small defects using a single framework, often requiring more complex model architectures to handle different defect scales. This results in a large number of model parameters, making deployment difficult in industrial settings. To address this issue, this invention performs residual feature compression on the multi-scale feature map of the stitched silicon wafer, effectively reducing the number of parameters in the silicon wafer defect detection model and achieving a lightweight silicon wafer defect detection model.

[0079] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this invention.

[0080] The above describes a method for detecting edge defects in silicon wafers under a special chamfering process, provided by one or more embodiments of the present invention. Based on the same idea, the present invention also provides a corresponding device for detecting edge defects in silicon wafers under a special chamfering process, such as... Figure 4 As shown.

[0081] Figure 4 This invention provides a schematic diagram of a silicon wafer edge defect detection device under a special chamfering process. The device includes:

[0082] Data acquisition module 401 is used to acquire edge images of defect-free silicon wafers under a special chamfering process with double 45-degree edges;

[0083] The feature compression module 402 is used to extract multiple multi-scale feature maps of the defect-free silicon wafer edge image from the output of the first set of residual modules and the second set of residual modules in the backbone network using the pre-trained WideResNet50 network as the backbone network; after unifying the spatial size of the multi-scale feature maps, they are stitched along the channel dimension, and residual feature compression is performed on the stitched multi-scale feature maps to obtain the silicon wafer edge feature tensor.

[0084] The model training module 403 is used to train an autoencoder with the silicon wafer edge feature tensor as the first supervision target and freeze all parameters of the trained autoencoder; the autoencoder with frozen parameters is used to process the defect-free silicon wafer image to obtain the output feature map; the output feature map is used as the second supervision target to train a convolutional neural network.

[0085] The defect detection module 404 is used to perform edge defect detection on the silicon wafer image under test using an autoencoder with frozen parameters and a trained convolutional neural network, respectively, to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and to determine the silicon wafer edge defect detection result based on the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

[0086] Specific limitations regarding the silicon wafer edge defect detection device under a special chamfering process can be found in the above-described limitations of the silicon wafer edge defect detection method under a special chamfering process, and will not be repeated here. Each module in the aforementioned silicon wafer edge defect detection device under a special chamfering process can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0087] The present invention also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 1 A method for detecting edge defects in silicon wafers under a special chamfering process is provided.

[0088] The present invention also provides Figure 5 The schematic diagram of the computer device shown is as follows: Figure 5 As shown, at the hardware level, this computer device includes a processor, internal bus, network interface, memory, and non-volatile memory, and may also include other hardware required for business operations. The processor reads the corresponding computer program from the non-volatile memory into memory and then executes it to achieve the above. Figure 1 A method for detecting edge defects in silicon wafers under a special chamfering process is provided.

[0089] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

Claims

1. A method for detecting edge defects of a silicon wafer under a special chamfering process, characterized in that, The method comprises the following steps: acquiring an edge image of a defect-free silicon wafer under a special chamfering process of double 45-degree edges; using a pre-trained WideResNet50 network as a backbone network to extract a plurality of multi-scale feature maps output by a first group of residual modules and a second group of residual modules of the edge image of the defect-free silicon wafer in the backbone network; uniformly spatially sizing the multi-scale feature maps, splicing the multi-scale feature maps along a channel dimension, and performing residual feature compression on the spliced multi-scale feature maps to obtain a silicon wafer edge feature tensor; wherein the residual feature compression on the spliced multi-scale feature maps to obtain the silicon wafer edge feature tensor specifically comprises: sequentially passing the spliced multi-scale feature maps through a 1*1 convolution, a batch normalization and a ReLU activation function to obtain a first silicon wafer edge feature tensor; sequentially passing the spliced multi-scale feature maps through a 3*3 convolution, a batch normalization, a ReLU activation function, a 3*3 convolution and a batch normalization to obtain a second silicon wafer edge feature tensor; and splicing the first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor to obtain the silicon wafer edge feature tensor; using the silicon wafer edge feature tensor as a first supervision target to train an autoencoder and freeze all parameters of the trained autoencoder; using the autoencoder with the frozen parameters to process a defect-free silicon wafer image to obtain an output feature map; using the output feature map as a second supervision target to train a convolutional neural network; using the autoencoder with the frozen parameters and the trained convolutional neural network to respectively perform edge defect detection on a to-be-tested silicon wafer image to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and determining a silicon wafer edge defect detection result according to a pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

2. The method for detecting edge defects in silicon wafers under a special chamfering process as described in claim 1, characterized in that, The method for acquiring the edge image of the defect-free silicon wafer under the special chamfering process specifically comprises the following steps: after the wafer is adsorbed and positioned at the center and horizontal calibration and angle orientation are performed, a ring light source is used to stably illuminate the edge of the wafer; a double-CCD line array camera arranged symmetrically on the upper and lower sides of the wafer is used to continuously acquire high-resolution images of the 45-degree edges of the silicon wafer after chamfering processing, to obtain the edge image of the defect-free silicon wafer.

3. The method for detecting edge defects in silicon wafers under a special chamfering process as described in claim 1, characterized in that, The spatial size of the multi-scale feature map is unified by a bilinear interpolation method.

4. The method of claim 1, wherein the method is used for detecting edge defects of a silicon wafer after a special chamfering process. The loss function used when training the convolutional neural network is: ； In the formula, L AS Loss function for training the convolutional neural network, C, W, H respectively the channel number, width, height of the feature map, S ( I ) is the output of the convolutional neural network, A ( I ) is the output feature map of the autoencoder after freezing the parameters, μ c A is the channel mean of the output feature of the autoencoder, σ c A is the channel standard deviation of the output feature of the autoencoder.

5. The method of claim 1, wherein the method is a method of detecting edge defects of a silicon wafer under a special chamfering process, characterized by, The determination of the silicon wafer edge defect detection result according to the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map specifically comprises the following steps: calculating a pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width and height dimensions and mapping the difference into a defect score; determining an edge defect feature map of the to-be-tested silicon wafer image according to the defect score; and determining the silicon wafer edge defect detection result according to the edge defect feature map.

6. The method for detecting edge defects in silicon wafers under a special chamfering process as described in claim 5, characterized in that, The calculation formula of the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map in the channel, width and height dimensions and the mapping into the defect score is: ； ； wherein M AS is the pixel-wise difference of the first and second silicon wafer edge defect feature maps in the channel, width and height dimensions, S AS is the defect score of the silicon wafer image to be detected, C, W, H are the channel number, width and height of the silicon wafer edge defect feature map, S(I) and A(I) are the outputs of the convolutional neural network and the autoencoder, i.e. the first and second silicon wafer edge defect feature maps, μ A is the channel mean of the autoencoder output features, σ A is the channel standard deviation of the autoencoder output features.

7. The method of claim 5, wherein the method is a method of detecting edge defects of a silicon wafer under a special chamfering process, characterized by, The edge defect feature map of the to-be-tested silicon wafer image is determined according to the defect score, and specifically includes the following steps: When the defect score is greater than a preset threshold, it indicates that the to-be-tested silicon wafer image has an edge defect, and the image is determined as an edge defect feature map; otherwise, it indicates that the to-be-tested silicon wafer image does not have an edge defect.

8. The method of claim 5, wherein the method is a method of detecting edge defects of a silicon wafer under a special chamfering process, characterized by, The defect part of the silicon wafer edge defect feature map is highlighted by white color, and the remaining part is black; and the silicon wafer edge defect detection result is determined according to the silicon wafer edge defect feature map, and specifically includes the following steps: According to the highlighted positioning area of the defect part of the silicon wafer edge defect feature map, the position, size and shape of the highlighted positioning area on the silicon wafer edge defect feature map are counted, which is the silicon wafer edge defect detection result.

9. A device for detecting edge defects of a silicon wafer under a special chamfering process, characterized in that, It includes: A data acquisition module is configured to acquire a defect-free silicon wafer edge image under a double-45-degree edge special chamfer process; A feature compression module is configured to use a pre-trained WideResNet50 network as a backbone network to extract a plurality of multi-scale feature maps output by a first group of residual modules and a second group of residual modules in the backbone network; unify the spatial size of the multi-scale feature maps, then concatenate them along the channel dimension, and perform residual feature compression on the concatenated multi-scale feature maps to obtain a silicon wafer edge feature tensor; wherein the residual feature compression on the concatenated multi-scale feature maps to obtain the silicon wafer edge feature tensor specifically includes: sequentially passing the concatenated multi-scale feature maps through a 1x1 convolution, batch normalization and a ReLU activation function to obtain a first silicon wafer edge feature tensor; sequentially passing the concatenated multi-scale feature maps through a 3x3 convolution, batch normalization, a ReLU activation function, a 3x3 convolution and batch normalization to obtain a second silicon wafer edge feature tensor; and concatenating the first silicon wafer edge feature tensor and the second silicon wafer edge feature tensor to obtain the silicon wafer edge feature tensor; A model training module is configured to use the silicon wafer edge feature tensor as a first supervision target to train an autoencoder, and freeze all parameters of the trained autoencoder; use the autoencoder with frozen parameters to process a defect-free silicon wafer image to obtain an output feature map; use the output feature map as a second supervision target to train a convolutional neural network; A defect detection module is configured to use the autoencoder with frozen parameters and the trained convolutional neural network to respectively perform edge defect detection on a to-be-tested silicon wafer image to obtain a first silicon wafer edge defect feature map and a second silicon wafer edge defect feature map; and determine a silicon wafer edge defect detection result according to the pixel-by-pixel difference between the first silicon wafer edge defect feature map and the second silicon wafer edge defect feature map.

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