Voltage mode driver and interface circuit

Abstract

The embodiment of the invention provides a voltage mode driver and an interface circuit, the voltage mode driver comprises a differential circuit and an attenuation circuit, and the differential circuit is connected with a power supply and the attenuation circuit; the attenuation circuit is connected with the power supply and is grounded; the differential circuit is used for outputting differential voltage; according to the voltage mode driver, the attenuation circuit can attenuate the output voltage of the differential circuit under the condition that a relatively high voltage is input to the differential circuit, so that the output voltage of the differential circuit is reduced, and the power consumption of the voltage mode driver is further reduced.

Description

Technical Field

[0001] The present application belongs to the field of circuit technology, and specifically relates to a voltage mode driver and an interface circuit. Background Art

[0002] Voltage-mode drivers are key circuit modules in high-speed serial interfaces, controlling the load's operating state by adjusting the output voltage. Their core function is to provide a stable, adjustable voltage signal to drive various electronic components or systems.

[0003] In the related art, the output voltage of a voltage-mode driver is controlled by an input voltage value. If the input voltage value is high, the output voltage of the voltage-mode driver will be high, which in turn will lead to higher power consumption. Summary of the Invention

[0004] The present application relates to a voltage-mode driver and an interface circuit, which solves the technical problem of high power consumption caused by high input voltage of existing voltage-mode drivers.

[0005] In a first aspect, the present application provides a voltage mode driver, comprising: a differential circuit and an attenuation circuit, wherein:

[0006] The differential circuit is connected to the power supply and the attenuation circuit;

[0007] The attenuation circuit is connected to the power supply and is grounded;

[0008] The differential circuit is used to output a differential voltage;

[0009] The attenuation circuit is used to attenuate the output voltage of the differential circuit.

[0010] In one possible implementation, the attenuation circuit includes: a control subcircuit and a first resistor, wherein:

[0011] The control subcircuit is connected to the first resistor and the power supply;

[0012] The first resistor is connected to the power supply;

[0013] The control subcircuit is also connected to the differential circuit;

[0014] The control subcircuit is used to adjust the current value of the output end of the differential circuit.

[0015] In a possible implementation, the control subcircuit includes: a negative feedback subcircuit, a first MOS transistor, and a second MOS transistor, wherein:

[0016] The first end of the negative feedback subcircuit is connected to the second end of the first resistor, and the second end of the negative feedback subcircuit is used to input a preset voltage; the third end of the negative feedback subcircuit is respectively connected to the gate of the first MOS transistor and the gate of the second MOS transistor;

[0017] The drain of the first MOS transistor is connected to the first end of the negative feedback sub-circuit, and the source of the first MOS transistor is grounded;

[0018] The drain of the second MOS transistor is connected to the output end of the differential circuit, and the source of the second MOS transistor is grounded.

[0019] In a possible implementation, the size of the second MOS transistor is a first multiple of the size of the first MOS transistor, and the resistance value of the first resistor and the first multiple satisfy a preset positive correlation.

[0020] In a possible implementation, both the first MOS transistor and the second MOS transistor are N-channel MOS transistors.

[0021] In one possible implementation, the differential circuit includes: a first differential sub-circuit, a second differential sub-circuit, and a second resistor, wherein:

[0022] A first end of the first differential subcircuit is connected to a power supply, a second end of the first differential subcircuit is grounded, and an output end of the first differential subcircuit is connected to a first end of the second resistor;

[0023] The first end of the second differential subcircuit is connected to the power supply, the second end of the second differential subcircuit is grounded, the output end of the second differential subcircuit is connected to the second end of the second resistor, and the output end of the first differential subcircuit and the output end of the second differential subcircuit are used to output a differential voltage.

[0024] In a possible implementation, the voltage mode driver further includes: a third MOS transistor and a fourth MOS transistor;

[0025] The drain of the third MOS transistor is connected to the output end of the first differential subcircuit, and the source of the third MOS transistor is connected to the first end of the attenuation circuit;

[0026] The drain of the fourth MOS transistor is connected to the output end of the second differential subcircuit, and the source of the fourth MOS transistor is connected to the first end of the attenuation circuit.

[0027] In a possible implementation, the first differential subcircuit includes: a fifth MOS transistor, a sixth MOS transistor, a third resistor, and a fourth resistor, wherein:

[0028] The source of the fifth MOS transistor is connected to the power supply, and the drain of the fifth MOS transistor is connected to the first end of the third resistor;

[0029] The second end of the third resistor is connected to the first end of the fourth resistor and the output end of the first differential subcircuit;

[0030] The second end of the fourth resistor is connected to the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is grounded.

[0031] In a possible implementation, the second differential subcircuit includes: a seventh MOS transistor, an eighth MOS transistor, a fifth resistor, and a sixth resistor, wherein:

[0032] The source of the seventh MOS transistor is connected to the power supply, and the drain of the seventh MOS transistor is connected to the first end of the fifth resistor;

[0033] The second end of the fifth resistor is connected to the first end of the sixth resistor and the output end of the second differential subcircuit;

[0034] The second end of the sixth resistor is connected to the drain of the eighth MOS transistor, and the source of the eighth MOS transistor is grounded.

[0035] In a possible implementation manner, the fifth MOS transistor and the seventh MOS transistor are both P-channel MOS transistors, and the sixth MOS transistor and the eighth MOS transistor are both N-channel MOS transistors.

[0036] In a possible implementation, the power supply is a drain-drain voltage VDD or a low dropout linear regulator LDO.

[0037] In a second aspect, an embodiment of the present application provides an interface circuit, comprising the voltage-mode driver of the first aspect.

[0038] An embodiment of the present application provides a voltage-mode driver and an interface circuit. The voltage-mode driver includes: a differential circuit and an attenuation circuit, wherein: the differential circuit is connected to a power supply and the attenuation circuit; the attenuation circuit is connected to the power supply and is grounded; the differential circuit is used to output a differential voltage; the attenuation circuit is used to attenuate the output voltage of the differential circuit. The present application can achieve that when a higher voltage is input to the differential circuit, the attenuation circuit can attenuate the output voltage of the differential circuit, thereby reducing the output voltage of the differential circuit and thereby reducing the power consumption of the voltage-mode driver. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of a voltage mode driver provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of another voltage mode driver provided in an embodiment of the present application;

[0041] Figure 3 A schematic structural diagram of another voltage mode driver provided in an embodiment of the present application;

[0042] Figure 4 A schematic structural diagram of an attenuation circuit provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of the structure of a differential circuit provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of current flow provided in an embodiment of the present application;

[0045] 10: voltage mode driver;

[0046] 20: voltage mode driver;

[0047] 30: Power supply;

[0048] 21: Differential circuit;

[0049] 22: Attenuation circuit;

[0050] 221: control subcircuit;

[0051] F: negative feedback subcircuit;

[0052] 211: first differential subcircuit;

[0053] 212: second differential subcircuit;

[0054] R6: first resistor;

[0055] R7: second resistor;

[0056] R8: the third resistor;

[0057] R9: fourth resistor;

[0058] R10: fifth resistor;

[0059] R11: The sixth resistor

[0060] M5: first MOS tube;

[0061] M6: second MOS tube;

[0062] M7: the third MOS tube;

[0063] M8: fourth MOS tube;

[0064] M9: fifth MOS tube;

[0065] M10: sixth MOS tube;

[0066] M11: seventh MOS tube;

[0067] M12: The eighth MOS tube. DETAILED DESCRIPTION

[0068] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0069] The terms "first," "second," and so on, appearing in this application are merely for illustration and to distinguish between the objects being described. They are not in any particular order, do not represent a specific limit on the number of objects in the embodiments of this application, and do not constitute any limitation on the embodiments of this application. For example, the terms "first resistor," "second resistor," and so on are merely for distinguishing between different resistors and do not indicate a difference in priority or importance between the two resistors.

[0070] In the present application, "at least one" means one or more, and "a plurality of" means two or more.

[0071] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0072] Throughout this application, the terms "exemplary," "in some embodiments," and "in other embodiments" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete manner.

[0073] The application scenario of the present application is how to attenuate the output voltage of a differential circuit to reduce power consumption. It should be noted that the voltage mode driver provided by the present application can be applied to a high-speed SerDes (Serializer / Deserializer) interface, for example, an MPHY (Mobile Industry Processor Interface Physical Layer) interface, a DPHY (Mobile Industry Processor Interface Digital Physical Layer) interface, a CPHY (Mobile Industry Processor Interface C-Physical Layer, where C represents "Camera / Display" and "Clock-Embedded") interface, an LVDS (Low-Voltage Differential Signaling) interface, wherein the device to which the voltage mode driver provided by the present application is applicable includes but is not limited to the above high-speed SerDes interface.

[0074] In an embodiment, the voltage mode driver is as shown in Figure 1 The voltage mode driver 10 includes an NMOS (N-channel Metal-Oxide-Semiconductor) transistor M1, an NMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5.

[0075] The voltage mode driver 10 is powered by a power supply LDO (Low Dropout Regulator) and provides a voltage of 0.4V. The gate of the NMOS transistor M1 is INP (Input Positive), the drain of the NMOS transistor M1 is connected to the power supply LDO, and the source of the NMOS transistor M1 is connected to the first end of the resistor R1. The second end of the resistor R1 is connected to the first end of the resistor R3, the first end of the resistor R5, and the output end TXDP (Transmit Differential Positive). The second end of the resistor R3 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M3 is INN (Input Negative), and the source of the NMOS transistor M3 is grounded.

[0076] The gate of NMOS transistor M2 is INN, the drain of NMOS transistor M2 is connected to the power supply LDO, and the source of NMOS transistor M2 is connected to the first end of resistor R2. The second end of resistor R2 is connected to the first end of resistor R4, the second end of resistor R5, and the output terminal TXDN (Transmit Differential Negative) 1. The second end of resistor R4 is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is INP, and the source of NMOS transistor M4 is grounded.

[0077] based on Figure 1 The voltage mode driver 10, in order to increase the transmission speed of the voltage signal, Figure 1 The NMOS tube M1, NMOS tube M2, NMOS tube M3 and NMOS tube M4 are all core components of the voltage mode driver 10. INP and INN both use a relatively low voltage. Since the voltage mode driver 10 needs to output a low-voltage differential signal, the LDO power supply voltage is 0.4V. With the evolution of the process, the voltages of INP and INN are required to be lower and lower. At this time, since the LDO power supply voltage is also low, the NMOS tube M1 and NMOS tube M2 will enter the cutoff region, and the voltage mode driver 10 will not work properly. If the LDO power supply voltage is increased, the differential voltage of the outputs of TXDP1 and TXDP2 will be higher, which will lead to higher power consumption.

[0078] In order to solve the above technical problems, an embodiment of the present application provides a voltage-mode driver, in which an attenuation circuit is connected to the differential circuit, and the attenuation circuit is used to attenuate the output voltage of the differential circuit. When the power supply provides a high voltage, the attenuation circuit can be used to reduce the output voltage of the differential circuit, thereby enabling the voltage-mode driver to operate normally while reducing power consumption.

[0079] The technical solutions shown in this application are described in detail below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or displayed content will not be repeated in different embodiments.

[0080] Figure 2 This is a schematic diagram of the structure of a voltage mode driver provided in an embodiment of the present application. Figure 2 The voltage mode driver 20 includes a differential circuit 21 and an attenuation circuit 22, wherein: the differential circuit 21 is connected to the power supply 30 and the attenuation circuit 22; the attenuation circuit 22 is connected to the power supply 30 and is grounded; the differential circuit 21 is used to output a differential voltage; and the attenuation circuit 22 is used to attenuate the output voltage of the differential circuit 21.

[0081] Specifically, refer to Figure 2The input end of the differential circuit 21 is connected to the power supply 30, and the output end of the differential circuit 21 is connected to the first end of the attenuation circuit 22; the third end of the attenuation circuit 22 is connected to the power supply 30, and the second end of the attenuation circuit 22 is grounded.

[0082] It can be understood that in the embodiment of the present application, the power supply 30 supplies power to the voltage mode driver 20. In order for the differential circuit 21 to work normally, the supply voltage of the power supply 30 needs to be increased. When the supply voltage of the power supply 30 is large, if there is no attenuation circuit 22, the output voltage of the differential circuit 21 is also large, which will cause higher power consumption. If the attenuation circuit is added, the attenuation circuit can reduce the output voltage of the differential circuit 21, thereby reducing the power consumption of the voltage mode driver 20.

[0083] In some embodiments, referring to Figure 3 The attenuation circuit 22 includes: a control subcircuit 221 and a first resistor R6, wherein: the control subcircuit 221 is connected to the first resistor R6 and the power supply 30; the first resistor R6 is connected to the power supply 30; the control subcircuit 221 is also connected to the differential circuit 21; the control subcircuit 221 is used to adjust the current value of the output end of the differential circuit.

[0084] Specifically, the first end of the control subcircuit 221 is connected to the first end of the first resistor R6, and the second end of the first resistor R6 is connected to the power supply 30; the third end of the control subcircuit 221 is used to input the preset voltage Vatt; the second end of the control subcircuit 221 is connected to the output end of the differential circuit 21, and the output voltage Vs of the power supply and the preset voltage Vatt are used to adjust the current value of the second end of the control subcircuit 221.

[0085] exist Figure 3 It can be understood that the power supply also supplies power to the attenuation circuit. The voltage value provided by the power supply and the preset voltage Vatt can adjust the current value of the second end of the control sub-circuit 221. This current value is also the current value of the output end of the differential circuit 21, thereby attenuating the output voltage of the differential circuit 21.

[0086] In some embodiments, referring to Figure 4 The control sub-circuit 221 includes: a negative feedback sub-circuit F, a first metal oxide semiconductor field effect transistor MOS tube M5 and a second MOS tube M6, wherein:

[0087] A first terminal (+) of the negative feedback sub-circuit F is connected to the first terminal of the first resistor R6, and a second terminal (-) of the negative feedback sub-circuit F is used to input a preset voltage Vatt; a third terminal of the negative feedback sub-circuit F is connected to the gate of the first MOS transistor M5 and the gate of the second MOS transistor M6;

[0088] The drain of the first MOS transistor M5 is connected to the first end of the negative feedback sub-circuit R6, and the source of the first MOS transistor M5 is grounded;

[0089] The drain of the second MOS transistor M6 is connected to the output end of the differential circuit 21 , and the source of the second MOS transistor M is grounded.

[0090] In some embodiments, the size of the second MOS transistor is a first multiple of the size of the first MOS transistor, and the resistance value of the first resistor R6 and the first multiple satisfy a preset positive correlation.

[0091] The resistance value of the first resistor and the first multiple satisfy the preset positive correlation relationship: parameter y=50x, y represents the resistance value of the first resistor, the unit is ohm Ω, and x represents the first multiple.

[0092] For example, if the resistance value of the first resistor R6 is 200Ω, the size of the second MOS transistor is four times the size of the first MOS transistor.

[0093] In some embodiments, the first MOS transistor M5 and the second MOS transistor M6 are both N-channel MOS transistors.

[0094] In the present application, the voltages of the first terminal (+) and the second terminal (-) of the negative feedback sub-circuit are the same, then the voltage VFB at FB=Vatt, then the current I1 through the first MOS transistor M5=(Vs-VFB) / y=(Vs-Vatt) / y, where if y is 200, then I1=(Vs-Vatt) / 200.

[0095] Furthermore, according to the mirror image relationship between the first MOS transistor M5 and the second MOS transistor M6, I2=x×I1. If y is 200 and x is 4, then I2=(Vs-Vatt) / 50.

[0096] The closer Vatt is to Vs, the smaller the current I2 consumed by the attenuation circuit 22 is, which can reduce power consumption.

[0097] It can be understood that the present application can adjust I2 by adjusting the value of Vatt, thereby adjusting the attenuation degree of the output voltage of the differential circuit.

[0098] In some embodiments, referring to Figure 5 , the differential circuit 21 includes: a first differential sub-circuit 211, a second differential sub-circuit 212 and a second resistor R7, wherein:

[0099] A first end of the first differential subcircuit 211 is connected to the power supply 30 , a second end of the first differential subcircuit 211 is grounded, and an output end TXDP2 of the first differential subcircuit 211 is connected to a first end of the second resistor R7 ;

[0100] The first end of the second differential sub-circuit 212 is connected with the power supply 30, the second end of the second differential sub-circuit 212 is grounded, and the output end TXDN2 of the second differential sub-circuit 212 is connected with the second end of the second resistor R7.

[0101] The output end of the first differential sub-circuit 211 and the output end of the second differential sub-circuit 212 are used for outputting differential voltage.

[0102] In the embodiment of the present application, the output voltage of the output end TXDP2 and the output end TXDN2 is differential voltage.

[0103] In some embodiments, referring to Figure 5 , the voltage mode driver further comprises a third MOS tube M7 and a fourth MOS tube M8.

[0104] The drain of the third MOS tube M7 is connected with the output end TXDP2 of the first differential sub-circuit 211, the source of the third MOS tube M7 is connected with the first end of the attenuation circuit 22, and the gate of the third MOS tube M7 inputs INP.

[0105] The drain of the fourth MOS tube M8 is connected with the output end of the second differential sub-circuit 212, the source of the fourth MOS tube M8 is connected with the first end of the attenuation circuit 22, and the gate of the fourth MOS tube M8 inputs INN.

[0106] In some embodiments, INP and INN can belong to CMOS (Complementary Metal Oxide Semiconductor) level voltage.

[0107] In the embodiment of the present application, the third MOS tube and the fourth MOS tube serve as switches between the differential circuit and the attenuation circuit, and when the third MOS tube and the fourth MOS tube are turned on, the attenuation circuit can attenuate the voltage output by the differential circuit.

[0108] In some embodiments, referring to Figure 5 , the first differential sub-circuit 211 comprises a fifth MOS tube M9, a sixth MOS tube M10, a third resistor R8 and a fourth resistor R9, wherein:

[0109] The source of the fifth MOS tube M9 is connected with the power supply 30, the drain of the fifth MOS tube M9 is connected with the first end of the third resistor R8, and the gate of the fifth MOS tube M9 is INN.

[0110] The second end of the third resistor R8 is connected with the first end of the fourth resistor R9 and the output end TXDP2 of the first differential sub-circuit 211.

[0111] The second end of the fourth resistor R9 is connected to the drain of the sixth MOS transistor M10 , the source of the sixth MOS transistor M10 is grounded, and the gate of the sixth MOS transistor M10 is INN.

[0112] In some embodiments, the second differential subcircuit 212 includes: a seventh MOS transistor M11, an eighth MOS transistor M12, a fifth resistor R10, and a sixth resistor R11, wherein:

[0113] The source of the seventh MOS transistor M11 is connected to the power supply 30 , the drain of the seventh MOS transistor M11 is connected to the first end of the fifth resistor R10 , and the gate of the seventh MOS transistor M11 is INP;

[0114] The second end of the fifth resistor R10 is connected to the first end of the sixth resistor R11 and the output end TXDN2 of the second differential sub-circuit 212;

[0115] The second end of the sixth resistor R11 is connected to the drain of the eighth MOS transistor M12 , the source of the eighth MOS transistor M12 is grounded, and the gate of the eighth MOS transistor M12 is INP.

[0116] In some embodiments, the fifth MOS transistor M9 and the seventh MOS transistor M11 are both P-channel MOS transistors, and the sixth MOS transistor M10 and the eighth MOS transistor M12 are both N-channel MOS transistors.

[0117] The fifth MOS transistor M9 and the seventh MOS transistor M11 are both P-channel MOS transistors that can be connected to the power supply VDD.

[0118] In some embodiments, the power supply is a drain-to-drain voltage VDD (Voltage Drain-to-Drain) or a low dropout linear regulator LDO.

[0119] When the power supply is the drain-drain voltage VDD, the fifth MOS transistor M9 and the seventh MOS transistor M11 will not enter the cut-off region due to the high drain-drain voltage VDD. However, in the absence of an attenuation circuit, the differential voltage Vdiff-pp (Differential Peak-to-Peak Voltage) output by the output terminal TXDP2 and the output terminal TXDN2 will be high, resulting in higher power consumption. To meet certain requirements, such as some protocols requiring Vdiff-pp=0.4V, Vdiff-pp needs to be attenuated. Therefore, an attenuation circuit 22 is introduced to attenuate Vdiff-pp by controlling the output current I2 of the attenuation circuit 22.

[0120] Furthermore, the power supply may also adopt an LDO, which can provide a voltage of 0.6V to the voltage mode driver 20 .

[0121] The current flow directions of the first differential subcircuit 211 , R11 and the attenuation circuit 22 are I3 , I4 and I2 , and the current flow direction of the second differential subcircuit 212 is the same as that of the first differential subcircuit 211 . The current flow direction of the first differential subcircuit 212 is taken as an example for description.

[0122] Further, based on Figure 5 , the current flow direction of the first differential subcircuit 211, R11 and attenuation circuit 22 is obtained as follows Figure 6 As shown, based on Figure 6 , we get the following expression:

[0123] I3=I2+I4;

[0124] I3=(Vs-VTXDP2) / R7;

[0125] I2=x×(Vs-Vatt) / y;

[0126] I4=Vs / (R7+R11);

[0127] In the above expression, if R7 is 50Ω, x is 4, y is 200, and R11 is 100Ω, Vs=0.75×Vatt, VTXDN2=1 / (3×Vs)=0.25×Vatt.

[0128] Further, in Figure 5 The resistance values ​​of R7, R8, R9 and R10 can all be 50Ω.

[0129] Considering the current flow direction of the second differential subcircuit 212, we can obtain Vdiff-pp = 2 × (Vs - V TXDN2) = Vatt. It can be concluded that the value of Vdiff-pp is only related to Vatt and has nothing to do with the voltage Vs. Furthermore, the present application can flexibly adjust Vdiff-pp by setting the preset voltage Vatt.

[0130] It can be further obtained that the common mode voltage Vcm of the voltage mode driver 20 is 0.5×Vatt. It can be understood that the present application can flexibly adjust Vcm by setting the preset voltage Vatt.

[0131] In the embodiment of the present application, the value of Vatt needs to be less than Vs and greater than a preset voltage value (such as 150mV) to avoid the value determination process of Vatt affecting the working state of the first MOS transistor M5 and the second MOS transistor M6.

[0132] In the above description, VTXDP2 represents the voltage of the output terminal TXDP2, and VTXDN2 represents the voltage of the output terminal TXDN2.

[0133] In summary, the above-mentioned voltage-mode driver 20 can be applied to high-speed SerDes interfaces. When the high-speed SerDes interface requires a specified driving output voltage, the voltage-mode driver 20 of the present application can be implemented, and can reduce the current consumed by the attenuation circuit and reduce power consumption.

[0134] In addition, the present invention can output differential signals at high speed through the differential circuit, and output lower differential voltage and common mode voltage by adjusting Vatt, thereby reducing power consumption. Furthermore, the present invention can flexibly and variably output differential voltage and common mode voltage by adjusting Vatt.

[0135] Furthermore, an interface circuit is provided for the present application. Figure 2 , the interface circuit includes the voltage mode driver 20 of any one of the above embodiments.

[0136] For example, the interface circuit includes: a SerDes interface circuit.

[0137] The transmission system provided in the embodiment of the present application can implement the technical solution shown in the above-mentioned voltage mode driver embodiment. Its implementation principle and beneficial effects are similar and will not be repeated here.

[0138] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the embodiments of the present invention.

Claims

1. A voltage mode driver, characterized in that: include: Differential circuit and attenuation circuit, where: The differential circuit is connected to a power supply and the attenuation circuit; The attenuation circuit is connected to the power supply, and the attenuation circuit is grounded; The differential circuit is used to output a differential voltage; The attenuation circuit is used to attenuate the output voltage of the differential circuit.

2. The voltage mode driver according to claim 1, wherein: The attenuation circuit includes: a control subcircuit and a first resistor, wherein: The control subcircuit is connected to the first resistor and the power supply; The first resistor is connected to the power supply; The control subcircuit is also connected to the differential circuit; The control subcircuit is used to adjust the current value of the output end of the differential circuit.

3. The voltage mode driver according to claim 2, wherein: The control subcircuit includes: a negative feedback subcircuit, a first metal oxide semiconductor field effect transistor (MOS) tube and a second MOS tube, wherein: The first end of the negative feedback subcircuit is connected to the first end of the first resistor, and the second end of the negative feedback subcircuit is used to input a preset voltage; the third end of the negative feedback subcircuit is respectively connected to the gate of the first MOS transistor and the gate of the second MOS transistor; The drain of the first MOS transistor is connected to the first end of the negative feedback sub-circuit, and the source of the first MOS transistor is grounded; The drain of the second MOS transistor is connected to the output end of the differential circuit, and the source of the second MOS transistor is grounded.

4. The voltage mode driver according to claim 3, wherein: The size of the second MOS transistor is a first multiple of the size of the first MOS transistor, and the resistance value of the first resistor and the first multiple satisfy a preset positive correlation.

5. The voltage mode driver according to claim 3, wherein: The first MOS transistor and the second MOS transistor are both N-channel MOS transistors.

6. The voltage mode driver according to any one of claims 1 to 5, characterized in that: The differential circuit includes: a first differential sub-circuit, a second differential sub-circuit and a second resistor, wherein: A first end of the first differential subcircuit is connected to the power supply, a second end of the first differential subcircuit is grounded, and an output end of the first differential subcircuit is connected to the first end of the second resistor; A first end of the second differential subcircuit is connected to the power supply, a second end of the second differential subcircuit is grounded, an output end of the second differential subcircuit is connected to the second end of the second resistor, and the output end of the first differential subcircuit and the output end of the second differential subcircuit are used to output the differential voltage.

7. The voltage mode driver according to claim 6, wherein: The voltage mode driver further includes: a third MOS transistor and a fourth MOS transistor; Wherein, the drain of the third MOS transistor is connected to the output end of the first differential sub-circuit, and the source of the third MOS transistor is connected to the first end of the attenuation circuit; The drain of the fourth MOS transistor is connected to the output end of the second differential subcircuit, and the source of the fourth MOS transistor is connected to the first end of the attenuation circuit.

8. The voltage mode driver according to claim 6, wherein: The first differential subcircuit includes: a fifth MOS transistor, a sixth MOS transistor, a third resistor and a fourth resistor, wherein: The source of the fifth MOS transistor is connected to the power supply, and the drain of the fifth MOS transistor is connected to the first end of the third resistor; The second end of the third resistor is connected to the first end of the fourth resistor and the output end of the first differential subcircuit; The second end of the fourth resistor is connected to the drain of the sixth MOS transistor, and the source of the sixth MOS transistor is grounded.

9. The voltage mode driver according to claim 8, wherein: The second differential subcircuit includes: a seventh MOS transistor, an eighth MOS transistor, a fifth resistor and a sixth resistor, wherein: The source of the seventh MOS transistor is connected to the power supply, and the drain of the seventh MOS transistor is connected to the first end of the fifth resistor; The second end of the fifth resistor is connected to the first end of the sixth resistor and the output end of the second differential subcircuit; The second end of the sixth resistor is connected to the drain of the eighth MOS transistor, and the source of the eighth MOS transistor is grounded.

10. The voltage mode driver according to claim 9, wherein: The fifth MOS transistor and the seventh MOS transistor are both P-channel MOS transistors, and the sixth MOS transistor and the eighth MOS transistor are both N-channel MOS transistors.

11. The voltage mode driver according to any one of claims 1 to 5, characterized in that: The power supply is a drain-drain voltage VDD or a low-dropout linear regulator LDO.

12. An interface circuit, characterized in that: The voltage mode driver comprises the voltage mode driver according to any one of claims 1 to 11.

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