Memristor cross array and preparation method thereof

Abstract

The invention discloses a memristor cross array and a preparation method thereof, the memristor cross array comprises m bottom electrodes, a resistive layer and a top electrode, the number of the bottom electrodes is m, and the bottom electrodes are arranged in parallel on the same horizontal plane along a first direction; the n top electrodes are arranged above the bottom electrode in parallel along a second direction perpendicular to the first direction, and are orthogonally arranged with the bottom electrode in space to form an m * n cross array structure; the resistive layer is arranged between the bottom electrode and the top electrode, is located in an intersection area of the bottom electrode and the top electrode, and is preferably MoS2; a buffer layer, preferably AlN, is arranged between the bottom electrode and the resistive layer; a barrier layer, preferably AlN, is arranged between the resistive layer and the top electrode. According to the memristor cross array and the preparation method thereof disclosed by the invention, the switching ratio and durability of the MoS2 memristor are remarkably improved, the leakage current is effectively reduced, and the reliability of the MoS2 memristor cross array in high-density storage application is improved.

Description

Technical Field

[0001] The present invention relates to a memristor cross array and a preparation method thereof, and belongs to the technical field of non-volatile storage. Background Art

[0002] The rapid development of artificial intelligence and big data technologies has significantly increased the complexity of computing tasks and the scale of data, placing higher demands on the computing power and storage efficiency of information processing systems. However, due to the physical separation of computing and storage units, the traditional von Neumann architecture is limited by limited storage bandwidth and significant energy dissipation, making it difficult to meet the needs of high-throughput, low-power data processing. This has gradually become one of the core bottlenecks restricting system performance improvements. As a new type of non-volatile memory device, memristors not only have adjustable resistance characteristics, enabling data storage and processing within the same unit, but also can be constructed into high-density cross-array structures to meet the needs of large-scale non-volatile array storage. This structure significantly improves storage density, reduces energy consumption, and shows great application potential in integrated storage and computing systems. It is one of the key technical paths to breaking through the limitations of traditional computing architectures.

[0003] The storage performance of a memristor crossbar array is affected by multiple factors, including the selection of resistive materials, optimization of the electrode interface, and precise control of the device fabrication process. Currently, common technical solutions for optimizing the storage performance of memristors include: 1. Optimizing resistive materials: Selecting oxide semiconductors, two-dimensional materials, and other materials as the resistive layer to improve the memristor's on-off ratio, reduce the threshold voltage, and enhance device stability; 2. Improving electrode design: Using high-work-function metals or multifunctional conductive layers to optimize the interface between the electrode and the resistive layer, improving carrier injection efficiency and controllability; 3. Enhancing interface stability: Introducing a buffer layer or interface modification layer between the electrode and the resistive layer to suppress the impact of interface defects and improve the device's storage consistency and durability; 4. Optimizing the manufacturing process: By adjusting thin film deposition parameters and heat treatment conditions, the uniformity and controllability of the film are improved, thereby enhancing the repeatability and reliability of the memristor.

[0004] In the aforementioned technical solution, enhancing interface stability is crucial for improving memristor storage performance. Defects at the interface between the resistive switching layer and the electrode directly affect device operation. By introducing a buffer layer or interface modification layer, the interface electric field distribution can be optimized and interface defects can be reduced, thereby improving device stability and consistency.

[0005] However, the interface engineering solutions used in existing technologies still have certain limitations. For example, certain buffer layer materials may introduce additional resistance, affecting the resistance switching performance of the device; due to process compatibility issues, the deposition uniformity of the interface layer is poor.

[0006] Therefore, there is an urgent need to provide an optimized memristor crossbar array and its preparation method, which can improve the interface stability while ensuring the high switching ratio, low power consumption and long life of the device, so as to promote the practical application of memristors in high-density memory. Summary of the Invention

[0007] To overcome the above-mentioned problems, the inventors have proposed a memristor crossbar array, comprising: a bottom electrode 4, a resistive switching layer 7, and a top electrode 9. The bottom electrodes 4 are arranged in parallel along a first direction and on the same horizontal plane; the top electrodes 9 are arranged in parallel above the bottom electrodes along a second direction perpendicular to the first direction, spatially orthogonal to the bottom electrodes, forming an m×n crossbar array structure; the resistive switching layer 7 is disposed between the bottom electrode 4 and the top electrode 9, within the intersection region between the two electrodes.

[0008] In a preferred embodiment, the resistive switching layer is a MoS2 thin film.

[0009] In a preferred embodiment, a buffer layer 6 is provided between the bottom electrode 4 and the resistive layer 7 , and a barrier layer 8 is provided between the resistive layer 7 and the top electrode 9 . The buffer layer and the barrier layer are preferably AlN thin films.

[0010] In a preferred embodiment, the bottom electrode 4 is an inert metal electrode, preferably Pt; an adhesion layer 2 is provided between the substrate 1 and the bottom electrode 4, preferably Ti; the top electrode 9 is an active metal electrode, preferably Ag; a metal interconnection layer is provided above the top electrode 9 to connect the two lead ends of the top electrode as a welding point, preferably Ti / Pt.

[0011] In a preferred embodiment, an isolation layer 5 is provided above the bottom electrode 4 , and a passivation layer 10 is provided above the top electrode 9 . The isolation layer and the passivation layer are preferably made of SiO 2 .

[0012] The present invention also discloses a method for preparing a memristor crossbar array, comprising the following steps:

[0013] S1, preparing a SiO2 thin film on the surface of a single crystal silicon substrate to form an oxide layer, preferably by thermal oxidation;

[0014] S2, preparing an adhesion layer on the surface of the oxide layer;

[0015] S3, preparing an inert metal layer on the surface of the adhesion layer;

[0016] S4, photolithography of the inert metal layer, dry etching to form a bottom electrode pattern;

[0017] S5. Preparing a SiO2 film on the surface of the bottom electrode to form a dielectric isolation layer, preferably by plasma enhanced chemical vapor deposition;

[0018] S6, photolithography isolation layer, dry etching, forming the resistive layer window pattern;

[0019] S7, photolithography process, forming a resistive switching layer window on the isolation layer;

[0020] S8, preparing an AlN film on the surface of the isolation layer to form a buffer layer;

[0021] S9, preparing a MoS2 thin film on the surface of the buffer layer to form a resistive switching layer;

[0022] S10, preparing an AlN film on the surface of the resistive switching layer to form a barrier layer;

[0023] S11, a peeling process to form a multilayer film pattern;

[0024] S12, high temperature annealing process, the resistive switching layer thin film is crystallized to form a stable thin film;

[0025] S13, preparing an active metal layer on the surface of the multilayer film;

[0026] S14, photolithography of the active metal layer, dry etching to form a top electrode pattern;

[0027] S15, preparing a SiO2 film on the surface of the active metal layer to form a passivation layer, preferably by plasma enhanced chemical vapor deposition;

[0028] S16, photolithography passivation layer, dry etching, forming bottom electrode hole and top electrode through-hole pattern;

[0029] S17, preparing an adhesion layer and an inert metal layer on the surface of the passivation layer;

[0030] S18. Photolithography the inert metal layer and dry-etch to form a metal interconnection line pattern.

[0031] In a preferred embodiment, in S2 and S3, the adhesion layer and the bottom electrode layer are prepared on the surface of the oxide layer by magnetron sputtering.

[0032] In a preferred embodiment, in S4, the bottom electrode pattern is a plurality of strip-shaped conductive structures arranged in parallel along the first direction, and each bottom electrode has two lead ends serving as bonding points.

[0033] In a preferred embodiment, in S8, S9 and S10, a buffer layer / resistive switching layer / barrier layer is prepared on the surface of the bottom electrode by magnetron sputtering.

[0034] In a preferred embodiment, in S13, a top electrode layer is prepared on the surface of the barrier layer by magnetron sputtering.

[0035] In a preferred embodiment, in S17, an adhesion layer and an inert metal layer are prepared on the surface of the top electrode by magnetron sputtering.

[0036] In a preferred embodiment, in S18, the metal interconnection line pattern is a plurality of strip-shaped conductive structures arranged in parallel along the second direction, and each metal interconnection line is connected to two lead ends of the top electrode to serve as a bonding point.

[0037] The present invention relates to a memristor structure with Ag as the top electrode, Pt as the bottom electrode, MoS as the resistive switching layer, an AlN buffer layer introduced between the MoS2 resistive switching layer and the Pt bottom electrode, and an AlN barrier layer introduced between the top electrode layer Ag and the MoS2 resistive switching layer. The structure's conductive mechanism is primarily based on the formation and rupture of conductive filaments driven by sulfur vacancy migration. In the initial state, the sulfur vacancies are disordered, and the device is in a high-resistance state. When a forward voltage is applied, the sulfur vacancies migrate and aggregate toward the top electrode under the action of the electric field, forming conductive filaments that penetrate the upper and lower electrodes at a threshold voltage, thereby transforming the device into a low-resistance state. When a reverse voltage is applied, the conductive filaments rupture, and the device returns to a high-resistance state, completing a single resistance-state transition. Furthermore, the AlN buffer and barrier layers effectively improve interface defects between the MoS2 and Pt bottom electrodes, inhibit the irregular diffusion of active metals into the resistive switching layer, regulate the size and position of the conductive filaments, and improve the switching ratio and durability of the memristor.

[0038] The beneficial effects of the present invention include:

[0039] (1) The present invention introduces AlN thin film as the buffer layer and barrier layer of the device in the memristor cross array, takes advantage of the good lattice matching between AlN and MoS2, promotes the preferred orientation growth of MoS2 thin film, reduces interface defects, and inhibits the irregular diffusion of active metal into the resistive switching layer, thereby significantly improving the switching ratio and durability of the memristor and effectively reducing leakage current. In the IV characteristic test, the device showed good consistency and stability, and the switching ratio could reach 10 3 The above ensures a significant conductivity difference between its storage states and improves data reading accuracy. In addition, the device resistance state can remain stable for a long time (>10 4 seconds), which makes it have broad application prospects in the fields of high-density storage and neuromorphic computing.

[0040] (2) The preparation process of the memristor cross array provided by the present invention mainly involves microelectronics process and stripping process. The cross array has the advantages of simple structure, high process compatibility, high integration and low power consumption. The area of ​​the resistive switching layer formed by the cross of the upper and lower electrode strips can be as small as 4F. 2, and lays a solid foundation for its application in the field of brain-like neural computing, computing and storage integration, and high-density storage. In addition, the thin film deposition process of the application can ensure the uniformity of each layer of the device, the etching process realizes precise patterning, and the stripping process improves the flexibility of the manufacturing process, thereby improving the consistency and stability of the device and significantly optimizing the overall chip performance.

[0041] Symbol description

[0042] 1-substrate layer;

[0043] 2-oxide layer;

[0044] 3-adhesion layer

[0045] 4-bottom electrode;

[0046] 5-isolation layer;

[0047] 6-buffer layer;

[0048] 7-resistive switching layer;

[0049] 8-barrier layer;

[0050] 9-top electrode;

[0051] 10-passivation layer;

[0052] 11-metal interconnection line. BRIEF DESCRIPTION OF DRAWINGS

[0053] Figure 1 A schematic diagram of a crossbar array structure of a memristor with m rows and n columns according to a preferred embodiment of the application is shown.

[0054] Figure 2 A schematic diagram of a crossbar array structure of a memristor with 3 rows and 3 columns according to a preferred embodiment of the application is shown.

[0055] Figure 3 The I-V characteristic test results of each unit of the MoS2 memristor crossbar array with 3 rows and 3 columns in the embodiment of the application are shown. DETAILED DESCRIPTION

[0056] The application will be further described in detail below with the aid of the accompanying drawings and examples. Through these descriptions, the features and advantages of the application will become clearer and more explicit.

[0057] The word "exemplary" is used herein in the sense of being an example, illustration, or demonstration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0058] According to the present invention, a memristor cross array structure is provided, wherein the memristor cross array comprises a bottom electrode 4, a resistive switching layer 7, and a top electrode 9. The bottom electrodes 4 are arranged in parallel along a first direction and on the same horizontal plane; the top electrodes 9 are arranged in parallel above the bottom electrodes along a second direction perpendicular to the first direction, and are arranged orthogonally to the bottom electrodes in space, forming an m×n cross array structure; the resistive switching layer 7 is provided between the bottom electrode 4 and the top electrode 9, and is located in the intersection region between the two. Figure 1 shown.

[0059] According to the present invention, a memristor cross array with 3 rows and 3 columns is provided. The memristor cross array adopts a through-hole structure, such as Figure 2 shown.

[0060] According to the present invention, the bottom electrode is an inert metal electrode, and the top electrode is an active metal electrode.

[0061] In a preferred embodiment, the bottom electrode is Pt, the top electrode is Ag, and the resistive layer is MoS2.

[0062] Preferably, the bottom electrode pattern is a plurality of strip-shaped conductive structures arranged in parallel along a first direction, and each bottom electrode has two lead-out ends serving as bonding points.

[0063] Preferably, the bottom electrode layer has a thickness of 100-200 nm, for example, 130 nm.

[0064] Preferably, the thickness of the top electrode layer is 10-100 nm, for example, 50 nm.

[0065] Preferably, the thickness of the resistive switching layer is 30-400 nm, for example, 200 nm.

[0066] The inventors discovered that interface defects between the bottom electrode 4 and the resistive switching layer 7 generate leakage current, which affects the switching ratio and durability of the memristor.

[0067] According to the present invention, a buffer layer 6 is further provided between the bottom electrode 4 and the resistive switching layer 7 , and the buffer layer is an AlN thin film.

[0068] AlN and MoS2 have good lattice matching, which can promote the preferential orientation growth of MoS thin film. That is, the setting of buffer layer 6 can effectively improve the interface defects between the bottom electrode 4 and the resistive layer 7, thereby significantly improving the switching ratio and durability of the memristor and effectively reducing the leakage current.

[0069] Preferably, the buffer layer has a thickness of 10-50 nm, for example, 10 nm.

[0070] The inventors found that there is a gap between the resistive layer 7 and the top electrode 9 due to Ag+ Irregular diffusion and migration to the resistive switching layer affects the device switching ratio and reliability.

[0071] According to the present invention, a barrier layer 8 is further provided between the resistive switching layer 7 and the top electrode 9 , and the barrier layer is an AlN thin film.

[0072] Preferably, the barrier layer has a thickness of 10-50 nm, for example, 10 nm.

[0073] Similar to a traditional memristor, the memristor in the present invention further includes a substrate 1 and an oxide layer 2 , and the bottom electrode 4 is disposed above the oxide layer 2 .

[0074] In the present invention, there is no limitation on the specific structures of the substrate and the oxide layer, and those skilled in the art can freely select them according to actual needs. Generally, the substrate is Si and the oxide layer is SiO2.

[0075] Preferably, the oxide layer has a thickness of 200-400 nm, for example, 300 nm.

[0076] A large number of experiments have found that the oxide layer 2 and the bottom electrode 4 are prone to peeling or uneven growth, which is caused by poor adhesion between the two.

[0077] According to a preferred embodiment of the present invention, an adhesion layer 3 is further provided between the oxide layer 2 and the bottom electrode 4. The adhesion layer 3 is Ti. Ti has good adhesion and can promote the bottom electrode 4 to form a uniform and stable thin film on the surface of the oxide layer 2, thereby reducing the probability of peeling or uneven growth.

[0078] Preferably, the thickness of the adhesion layer is 10-30 nm, for example, 20 nm.

[0079] In a preferred embodiment, an isolation layer 5 is provided above the bottom electrode 4 , and the isolation layer is SiO 2 .

[0080] Preferably, the thickness of the isolation layer is 100-200 nm, for example, 150 nm.

[0081] In a preferred embodiment, a passivation layer 10 is further provided above the top electrode 9 , and the passivation layer is SiO 2 .

[0082] Preferably, the thickness of the passivation layer is 100-200 nm, for example, 150 nm.

[0083] In a preferred embodiment, a metal interconnection line 11 is further provided above the passivation layer 10 , and the metal interconnection line is Ti / Pt.

[0084] Preferably, the metal interconnection line pattern is a plurality of strip-shaped conductive structures arranged in parallel along the second direction, and each metal interconnection line is connected to two lead-out ends of the top electrode to serve as a bonding point.

[0085] The present invention also discloses a method for preparing a memristor crossbar array, comprising the following steps:

[0086] S1, preparing a SiO2 thin film on the surface of a single crystal silicon substrate to form an oxide layer;

[0087] S2, preparing an adhesion layer on the surface of the oxide layer;

[0088] S3, preparing an inert metal layer on the surface of the adhesion layer;

[0089] S4, photolithography of the inert metal layer, dry etching to form a bottom electrode pattern;

[0090] S5, preparing a SiO2 film on the surface of the bottom electrode to form a dielectric isolation layer;

[0091] S6, photolithography isolation layer, dry etching, forming the resistive layer window pattern;

[0092] S7, photolithography process, forming a resistive switching layer window on the isolation layer;

[0093] S8, preparing an AlN film on the surface of the isolation layer to form a buffer layer;

[0094] S9, preparing a MoS2 thin film on the surface of the buffer layer to form a resistive switching layer;

[0095] S10, preparing an AlN film on the surface of the resistive switching layer to form a barrier layer;

[0096] S11, a peeling process to form a multilayer film pattern;

[0097] S12, high temperature annealing process, the resistive switching layer thin film is crystallized to form a stable thin film;

[0098] S13, preparing an active metal layer on the surface of the multilayer film;

[0099] S14, photolithography of the active metal layer, dry etching to form a top electrode pattern;

[0100] S15, preparing a SiO2 film on the surface of the active metal layer to form a passivation layer;

[0101] S16, photolithography passivation layer, dry etching, forming bottom electrode hole and top electrode through-hole pattern;

[0102] S17, preparing an adhesion layer and an inert metal layer on the surface of the passivation layer;

[0103] S18. Photolithography the inert metal layer and dry-etch to form a metal interconnection line pattern.

[0104] In a preferred embodiment, before S1 , the wafer is cleaned using RCA technology.

[0105] In a preferred embodiment, in S1, an oxide layer is prepared on the surface of the substrate by a thermal oxidation method.

[0106] In a preferred embodiment, in S2, an adhesion layer is prepared on the surface of the oxide layer by magnetron sputtering.

[0107] More preferably, a DC magnetron sputtering method is adopted, Ar is used as the working gas, and the pressure in the chamber during sputtering is 1 Pa.

[0108] In a preferred embodiment, in S3, a bottom electrode layer is prepared on the surface of the adhesion layer by magnetron sputtering.

[0109] More preferably, radio frequency magnetron sputtering is adopted, Ar is used as the working gas, and the pressure in the chamber during sputtering is 1 Pa.

[0110] In a preferred embodiment, in S4, the bottom electrode pattern is a plurality of strip-shaped conductive structures arranged in parallel along the first direction, and each bottom electrode has two lead ends serving as bonding points.

[0111] Further preferably, cleaning is performed after S4 to remove etching residues.

[0112] In a preferred embodiment, in S5, a plasma enhanced chemical vapor deposition method is used to prepare an isolation layer on the surface of the bottom electrode.

[0113] In the present invention, the specific method for preparing the buffer layer, the resistive switching layer and the barrier layer is not limited. Those skilled in the art can choose any one of magnetron sputtering, chemical vapor deposition, atomic layer deposition and sol-gel method, preferably magnetron sputtering.

[0114] More preferably, the magnetron sputtering method is performed by radio frequency sputtering.

[0115] In a preferred embodiment, in S6, the resistive layer window is a rectangular pattern, and the lengths of two sides thereof are smaller than the width of the horizontal bottom electrode strips.

[0116] More preferably, the resistive switching layer is formed by a lift-off process.

[0117] In a preferred embodiment, cleaning is performed after S11 to remove stripping residues.

[0118] In a preferred embodiment, in S12, the annealing process is performed in a tube furnace environment with a gas pressure lower than 1.0 Pa, and the heating rate and target temperature are precisely controlled by a programmed temperature rising system, thereby promoting crystallization and forming a stable thin film.

[0119] In a preferred embodiment, in S13, a top electrode layer is prepared on the surface of the multilayer film by magnetron sputtering.

[0120] More preferably, radio frequency magnetron sputtering is used, Ar is used as the working gas, and the pressure in the chamber during sputtering is 1 Pa.

[0121] In a preferred embodiment, in S15 , a passivation layer is prepared on the surface of the top electrode by plasma enhanced chemical vapor deposition.

[0122] In a preferred embodiment, in S17, the adhesion layer is prepared on the surface of the passivation layer by magnetron sputtering.

[0123] More preferably, a DC magnetron sputtering method is adopted, Ar is used as the working gas, and the pressure in the chamber during sputtering is 1 Pa.

[0124] In a preferred embodiment, in S17, an inert metal layer is prepared on the surface of the adhesion layer by magnetron sputtering.

[0125] More preferably, radio frequency magnetron sputtering is adopted, Ar is used as the working gas, and the pressure in the chamber during sputtering is 1 Pa.

[0126] In a preferred embodiment, in S18, the metal interconnection line pattern is a plurality of strip-shaped conductive structures arranged in parallel along the second direction, and each metal interconnection line is connected to two lead ends of the top electrode to serve as a bonding point.

[0127] More preferably, cleaning is performed after S18 to remove etching residues.

[0128] Example

[0129] Example 1

[0130] A 3×3 memristor crossbar array was prepared by the following steps, including:

[0131] S1, preparing a SiO2 thin film on the surface of a single crystal silicon substrate to form an oxide layer;

[0132] S2, preparing an adhesion layer on the SiO2 surface, preferably Ti;

[0133] S3, preparing an inert metal layer on the surface of the adhesion layer, preferably Pt;

[0134] S4, photolithography of the inert metal layer, dry etching to form a bottom electrode pattern;

[0135] S5, preparing a SiO2 film on the surface of the bottom electrode to form an isolation layer;

[0136] S6, photolithography isolation layer, dry etching, forming the resistive layer window pattern;

[0137] S7, photolithography process, forming a resistive switching layer window on the isolation layer;

[0138] S8, preparing an AlN film on the surface of the isolation layer to form a buffer layer;

[0139] S9, preparing a MoS2 thin film on the surface of the buffer layer to form a resistive switching layer;

[0140] S10, preparing an AlN film on the surface of the resistive switching layer to form a barrier layer;

[0141] S11, a peeling process to form a multilayer film pattern;

[0142] S12, high temperature annealing process, the resistive switching layer thin film is crystallized to form a stable thin film;

[0143] S13, preparing an active metal layer on the surface of the multilayer film, preferably Ag;

[0144] S14, photolithography of the active metal layer, dry etching to form a top electrode pattern;

[0145] S15, preparing a SiO2 film on the surface of the active metal layer to form a passivation layer;

[0146] S16, photolithography passivation layer, dry etching, forming bottom electrode hole and top electrode through-hole pattern;

[0147] S17, preparing an adhesion layer and an inert metal layer on the surface of the passivation layer, preferably Ti / Pt

[0148] S18, photolithography the inert metal layer, and dry etching to form a metal interconnection line pattern;

[0149] Among them, before S1, RCA technology is used to clean the wafer.

[0150] In S1, SiO2 is prepared on the substrate surface by thermal oxidation method with a thickness of 300 nm.

[0151] In S2, an adhesion layer Ti is prepared on the SiO2 surface by a magnetron sputtering method. The magnetron sputtering method adopts a DC sputtering mode, and the thickness of the adhesion layer is 20 nm.

[0152] In S3 , a bottom electrode layer Pt is prepared by magnetron sputtering, wherein the magnetron sputtering adopts radio frequency sputtering, and the thickness of the bottom electrode layer is 130 nm.

[0153] In S5, a plasma enhanced chemical vapor deposition method is used to prepare an isolation layer SiO2 on the surface of the bottom electrode, with a thickness of 150 nm.

[0154] In S8, a buffer layer AlN thin film is prepared by magnetron sputtering, wherein the magnetron sputtering adopts a radio frequency sputtering method, and the thickness of the buffer layer is 10 nm.

[0155] In S9, a MoS2 thin film as a resistive switching layer is prepared by a magnetron sputtering method, wherein the magnetron sputtering method adopts a radio frequency sputtering method, and the thickness of the resistive switching layer is 200 nm.

[0156] In S10, a barrier layer AlN thin film is prepared by a magnetron sputtering method, wherein the magnetron sputtering method adopts a radio frequency sputtering method, and the thickness of the buffer layer is 10 nm.

[0157] In S13, a top electrode layer of Ag is prepared by magnetron sputtering, wherein the magnetron sputtering adopts radio frequency sputtering. The thickness of the top electrode layer is 50 nm.

[0158] In S15, a passivation layer SiO2 is prepared on the surface of the top electrode by plasma enhanced chemical vapor deposition, and the thickness of the passivation layer is 150 nm.

[0159] In S17, a magnetron sputtering method is used to prepare an adhesion layer Ti on the surface of the passivation layer. The magnetron sputtering method adopts a DC sputtering method, and the thickness of the adhesion layer is 20 nm.

[0160] In S17, an inert metal layer Pt is prepared by a magnetron sputtering method, wherein the magnetron sputtering method adopts a radio frequency sputtering method, and the thickness of the inert metal layer is 130 nm.

[0161] The final memristor cross array consists of substrate, oxide layer, adhesion layer, bottom electrode, buffer layer, resistive switching layer, barrier layer and top electrode from bottom to top: Si / SiO2 / Ti / Pt / AlN / MoS2 / AlN / Ag.

[0162] The IV characteristics of the 3×3 memristor crossbar array were tested on a test bench constructed with a semiconductor parameter analyzer (Keithley 4200-SCS, Tektronix, Solon, Ohio, USA) and a manual probe station (PW-400, Advanced, Shanghai, China). First, two probes were used to contact the top and bottom electrodes respectively. The positive scan voltage was set to 0V~3V, the negative scan voltage was set to 0V~-3V, and the limit current of the positive scan was set to 1×10 -3 A, the limit current of negative scanning is set to 1×10 -1 A, the step size of each scan is 0.05V.

[0163] The test results are as follows Figure 3 As shown in the figure, the red color is the process of turning on under the first positive bias and turning off under the negative bias, and the gray color is the process of turning on under the 100th positive bias and turning off under the negative bias. It can be seen from the figure that the absolute values ​​of the positive and negative threshold voltages of the memristor are distributed in the range of 0V to 2V, and the on-off ratio is greater than 10 3 , and the characteristics of the 9 array points tend to be consistent and can show more than 100 times of stable cycle characteristics, and more than 10 4 The resistance state remains stable within seconds, indicating that memristors have good applicability in high-density storage and neuromorphic computing applications.

[0164] The present invention has been described above with reference to preferred embodiments, but these embodiments are merely exemplary and serve only as illustrations. On this basis, various replacements and improvements can be made to the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A memristor crossbar array, characterized in that: The invention comprises a bottom electrode (4), a resistive switching layer (7) and a top electrode (9), wherein: the bottom electrode (4) comprises m electrodes arranged in parallel on the same horizontal plane along a first direction; the top electrode (9) comprises n electrodes arranged in parallel above the bottom electrode along a second direction perpendicular to the first direction and arranged orthogonally to the bottom electrode in space, forming an m×n cross array structure; the resistive switching layer (7) is arranged between the bottom electrode (4) and the top electrode (9), and is located in the cross region between the two.

2. The memristor crossbar array according to claim 1, wherein: The resistive switching layer (7) is a MoS2 thin film.

3. The memristor crossbar array according to claim 1, wherein: A buffer layer (6) is provided between the bottom electrode (4) and the resistive switching layer (7), and a barrier layer (8) is provided between the resistive switching layer (7) and the top electrode (9).

4. The memristor crossbar array according to claim 3, wherein: The buffer layer is an AlN film, and the barrier layer is an AlN film.

5. The memristor crossbar array according to claim 1, wherein: The bottom electrode (4) is an inert metal, preferably Pt; an adhesion layer (2) is provided between the substrate (1) and the bottom electrode (4), preferably Ti; the top electrode (9) is an active metal, preferably Ag; a metal interconnection line is provided above the top electrode (9) to connect the two lead ends of the top electrode as a pressure welding point, preferably Ti / Pt.

6. The memristor crossbar array according to claim 1, wherein: An isolation layer (5) is provided above the bottom electrode (4), and a passivation layer (10) is provided above the top electrode (9). The isolation layer and the passivation layer are preferably SiO2.

7. A method for preparing a memristor crossbar array, characterized in that: The following steps are involved: S1, preparing a SiO2 thin film on the surface of a single crystal silicon substrate to form an oxide layer; S2, preparing an adhesion layer on the surface of the oxide layer; S3, preparing an inert metal layer on the surface of the adhesion layer; S4, photolithography of the inert metal layer, dry etching to form a bottom electrode pattern; S5, preparing a SiO2 film on the surface of the bottom electrode to form a dielectric isolation layer; S6, photolithography isolation layer, dry etching, forming the resistive layer window pattern; S7, photolithography process, forming a resistive switching layer window on the isolation layer; S8, preparing an AlN film on the surface of the isolation layer to form a buffer layer; S9, preparing a MoS2 thin film on the surface of the buffer layer to form a resistive switching layer; S10, preparing an AlN film on the surface of the resistive switching layer to form a barrier layer; S11, a peeling process to form a multilayer film pattern; S12, high temperature annealing process, the resistive switching layer thin film is crystallized to form a stable thin film; S13, preparing an active metal layer on the surface of the multilayer film; S14, photolithography of the active metal layer, dry etching to form a top electrode pattern; S15, preparing a SiO2 film on the surface of the active metal layer to form a passivation layer; S16, photolithography passivation layer, dry etching, forming bottom electrode hole and top electrode through-hole pattern; S17, preparing an adhesion layer and an inert metal layer on the surface of the passivation layer; S18. Photolithography the inert metal layer and dry-etch to form a metal interconnection line pattern.

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