Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate which comprises a substrate and an epitaxial layer which are stacked, and the epitaxial layer has a first doping type; the split source region structure is located in the epitaxial layer, the split source region structure is a region formed by performing ion implantation on one side surface of a part of the epitaxial layer, and the split source region structure comprises a first source region and a second source region which are spaced in the direction parallel to the surface of the substrate; the plurality of gate structures are located on the surface of the substrate, and the first source region and the second source region in the same split source region are in contact with different and adjacent gate structures respectively; and the Schottky metal layer is located on the first surface region, and the first surface region is the surface of the epitaxial layer located between the first source region and the second source region in the same split source region structure. According to the invention, the technical problems of low reliability and high switching loss of a SiC MOSFET power device are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular, to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In the field of semiconductor devices, especially in the application of power electronics, silicon carbide (SiC) MOSFETs have become an integral part of power electronic systems due to their superior performance, such as high breakdown voltage, low forward voltage drop, high switching speed, and easy gate control. However, SiC MOSFETs have limitations in certain key performance aspects, particularly in terms of static breakdown resistance. Compared to traditional Si-based MOSFETs, the gate oxide layer of SiC MOSFETs is thinner, resulting in lower static breakdown resistance. This weakness can lead to damage to the gate oxide layer when the device is subjected to accidental electrostatic discharge events, thereby affecting the reliability and service life of the device.

[0003] In addition, the high-frequency operating characteristics of SiC MOSFETs also face challenges. In high-frequency applications, SiC MOSFETs may exhibit high switching losses due to high contact resistance between the gate and the source region, limiting their application in high-frequency power electronic converters. The robustness of the body diode, which acts as a path for current under reverse voltage, is also an important consideration factor, as it can cause the expansion of epitaxial layer defects under high temperature and high current conditions, thereby reducing the overall performance of the device.

[0004] Another related technical problem is the impact of the structure after integrating a Schottky diode (SBD) on the overall device withstand voltage. Although integrating an SBD can optimize the reverse conduction performance of the device, the withstand voltage capability of the Schottky junction is lower than that of the traditional PN junction, which may to some extent reduce the withstand voltage level of the entire device, limiting the application of the device in high-voltage environments.

[0005] In summary, the SiC MOSFETs in the prior art have obvious defects in terms of static breakdown resistance, switching loss in high-frequency operation, robustness of the body diode, and device withstand voltage after integrating an SBD. In view of these deficiencies, it is necessary to provide a MOSFET that is more suitable for the stringent requirements of modern power electronic systems. SUMMARY

[0006] The present application provides a semiconductor device and a preparation method thereof to solve the problems of low reliability and high switching loss of MOSFET power devices in the related art.

[0007] According to one aspect of the present application, a semiconductor device is provided, comprising:

[0008] a substrate including a layered substrate and an epitaxial layer having a first doping type;

[0009] a split source region structure in the epitaxial layer, the split source region structure being a region formed by ion implantation to a side surface of a portion of the epitaxial layer, and the split source region structure including a first source region and a second source region spaced apart in a direction parallel to the substrate surface;

[0010] a plurality of gate structures on the substrate surface, the first source region and the second source region in the same split source region structure being in contact with different and adjacent gate structures, respectively;

[0011] a Schottky metal layer on a first surface region, the first surface region being a surface of the epitaxial layer between the first source region and the second source region in the same split source region structure.

[0012] Optionally, the first source region and the second source region each include a first implant region and a second implant region, the first implant region being a region formed by ion implantation to a side surface of a portion of the epitaxial layer, the second implant region being a region formed by ion implantation to a side surface of a portion of the first implant region, the semiconductor device further including: a doped semiconductor layer on a surface of the epitaxial layer between the gate structure and the Schottky metal layer, the first source region being in contact with the doped semiconductor layer and the gate structure, respectively; a third implant region between the doped semiconductor layer and a portion of the second implant region, the third implant region being a region formed by ion implantation to a side surface of a portion of the second implant region in the first source region; wherein a portion of the first implant region and the second implant region between the third implant region and the first implant region is in contact with the gate structure, the doped semiconductor layer and the second implant region having the first doping type, the first implant region and the third implant region having the second doping type.

[0013] Optionally, a portion of the first implant region between the second implant region and the epitaxial layer has a first thickness, a portion of the second implant region between the first implant region and the third implant region has a second thickness, and the third implant region has a third thickness, the second thickness and the third thickness each being less than the first thickness.

[0014] Optionally, the semiconductor device further includes: a fourth implant region in the epitaxial layer and in contact with the Schottky metal layer, the fourth implant region being a region formed by ion implantation to a portion of the first surface region, and the fourth implant region having the second doping type.

[0015] Optionally, the fourth implant region has the same doping concentration and depth as the third implant region.

[0016] Optionally, the semiconductor device further comprises: an insulating medium layer on the side of the substrate having the epitaxial layer, a first portion of the insulating medium layer covering the gate structure, a second portion of the insulating medium layer covering the doped semiconductor layer, and a first source contact hole between the first portion and the second portion.

[0017] Optionally, the second source region contacts a third portion of the insulating medium layer and the gate structure respectively, and a second source contact hole is between the first portion and the third portion.

[0018] Optionally, the semiconductor device further comprises: a third source region in the epitaxial layer, the third source region and the second source region contacting the same gate structure respectively; and a fifth implant region in the third source region, the fifth implant region having a depth greater than the depth of the fourth implant region and the depth of the third implant region.

[0019] According to an aspect of the present application, there is provided a method for manufacturing a semiconductor device, the method comprising:

[0020] providing a substrate comprising a substrate and an epitaxial layer stacked along a first direction;

[0021] forming a split source region structure by ion implantation on a side surface of a portion of the epitaxial layer, the split source region structure comprising a first source region and a second source region spaced apart along a direction parallel to the surface of the substrate, and a surface of the epitaxial layer between the first source region and the second source region in the same split source region being a first surface region;

[0022] forming a plurality of gate structures on the substrate such that the first source region and the second source region in the same split source region contact different and adjacent gate structures respectively;

[0023] forming a Schottky metal layer on the first surface region.

[0024] Optionally, the step of forming the split source region structure comprises: forming a first implant region by ion implantation on a side surface of a portion of the epitaxial layer, and forming a second implant region by ion implantation on a side surface of a portion of the first implant region; and the method further comprises the step of: forming a third implant region and a fourth implant region by ion implantation on a side surface of a portion of the second implant region in the first source region and a portion of the first surface region simultaneously, and a portion of the first implant region and the second implant region between the third implant region and the first implant region contacting the gate structure.

[0025] According to the present application, in a semiconductor device, a split source region structure is located in an epitaxial layer, the split source region structure is a region formed by ion implantation on a side surface of a portion of the epitaxial layer, and the split source region structure includes a first source region and a second source region spaced apart in a direction parallel to the substrate surface, a Schottky metal layer is located on the first surface region, and the first surface region is the surface of the epitaxial layer located between the first source region and the second source region in the same split source region, the Schottky metal layer introduced above is in direct contact with the epitaxial layer, and a Schottky barrier diode is integrated in the device. In a conventional MOSFET, the body diode is used to provide a current conduction path when the device is reverse biased. However, the conduction mechanism of the body diode is bipolar, which may lead to the expansion of epitaxial layer defects under high heat and high current conditions, affecting the reliability and life of the device. The SBD integrated in this application is a unipolar device that can effectively avoid these problems while reducing the cost of additional parallel diodes and directly providing a reverse conduction path within the MOSFET. In addition, the integrated SBD structure can optimize the reverse recovery process and reduce switching losses, thereby improving the efficiency and performance of the device under high-frequency operating conditions. In addition, the integrated SBD structure can provide a more stable reverse conduction path by directly contacting the epitaxial layer, avoiding the thermal stress and defect expansion that may be caused by the body diode when it is turned on, thereby improving the long-term stability and reliability of the entire MOSFET device. Therefore, the integrated SBD structure in this application mainly solves the technical problems of low reliability and high switching loss of MOSFET power devices by providing a unipolar reverse conduction path, optimizing the reverse recovery characteristics, and enhancing the overall performance and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of this application. The exemplary embodiments and descriptions of this application are intended to explain this application and do not constitute an improper limitation on this application. In the accompanying drawings:

[0027] Figure 1 A schematic cross-sectional structure diagram of a semiconductor device provided according to an embodiment of the present application is shown;

[0028] Figure 2 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown;

[0029] Figure 3 A schematic cross-sectional structure diagram of a substrate is provided in a method for preparing a semiconductor device;

[0030] Figure 4 Shown in Figure 3A schematic diagram of the cross-sectional structure of the substrate after the first implantation region is formed in the epitaxial layer;

[0031] Figure 5 Shown in Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the second injection region is formed in the first injection region;

[0032] Figure 6 Shown in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the third injection region and the fourth injection region are formed in the substrate;

[0033] Figure 7 Shown in Figure 6 Schematic diagram of the cross-sectional structure of the substrate after a gate dielectric layer is formed on the substrate;

[0034] Figure 8 Shown in Figure 7 A schematic diagram of a cross-sectional structure of a substrate after a gate is formed on the gate dielectric layer;

[0035] Figure 9 Shown in Figure 8 A schematic cross-sectional structure diagram of a substrate after an insulating material layer covering a gate structure is formed on the substrate;

[0036] Figure 10 Shows the Figure 9 A schematic diagram of the cross-sectional structure of the substrate after the insulating material layer in the substrate is etched to form an insulating dielectric layer;

[0037] Figure 11 Shown in Figure 10 Schematic diagram of the cross-sectional structure of the substrate after a Schottky metal layer is formed on the first surface area.

[0038] The above drawings include the following reference numerals:

[0039] 110. Substrate; 120. Epitaxial layer; 20. Split source region structure; 201. First source region; 202. Second source region; 203. Third source region; 210. First injection region; 220. Second injection region; 30. Fourth injection region; 40. Gate structure; 410. Gate dielectric layer; 420. Gate; 50. Schottky metal layer; 60. Third injection region; 70. Doped semiconductor layer; 80. Insulating dielectric layer; 801. Insulating material layer; 810. First portion; 820. Second portion; 830. Third portion; 90. Fifth injection region; 101. First metal layer; 102. Second metal layer. DETAILED DESCRIPTION

[0040] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0041] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] As described in the background, existing SiC MOSFETs have significant deficiencies in terms of electrostatic breakdown resistance, switching losses during high-frequency operation, body diode robustness, and device withstand voltage after integrating SBDs. To address these deficiencies, it is necessary to provide a MOSFET that is more suitable for the demanding requirements of modern power electronics systems. To address these technical issues, embodiments of the present application provide a semiconductor device and a method for manufacturing the same.

[0044] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0045] According to one embodiment of the present application, a semiconductor device is provided, such as Figure 1 Shown, including:

[0046] A base, comprising a stacked substrate 110 and an epitaxial layer 120, wherein the epitaxial layer 120 has a first doping type;

[0047] A split source region structure 20 is located in the epitaxial layer 120. The split source region structure 20 is formed by ion implantation on a side surface of a portion of the epitaxial layer 120. The split source region structure 20 includes a first source region 201 and a second source region 202 spaced apart in a direction parallel to the substrate surface.

[0048] a plurality of gate structures 40 are located on the surface of the substrate, and the first source region 201 and the second source region 202 in the same split source region structure 20 are respectively in contact with different and adjacent gate structures 40;

[0049] a Schottky metal layer 50 is located on the first surface region, and the first surface region is the surface of the epitaxial layer 120 between the first source region 201 and the second source region 202 in the same split source region structure 20.

[0050] In the semiconductor device provided by the above embodiment, a plurality of split source region structures 20 are spaced apart in the epitaxial layer 120, the split source region structure 20 is a region formed by ion implantation on one side surface of part of the epitaxial layer 120, and the Schottky metal layer 50 is located on the first surface region, and the first surface region is the surface of the epitaxial layer 120 between the first source region 201 and the second source region 202 in the same split source region structure 20. The Schottky metal layer 50 introduced above directly contacts the epitaxial layer 120, and a Schottky barrier diode (SBD) structure is integrated in the device. In a conventional MOSFET, a body diode is used to provide a conduction path for current when the device is reversely biased. However, the conduction mechanism of the body diode is bipolar, which may cause the expansion of defects in the epitaxial layer 120 under high heat and large current conditions, affecting the reliability and service life of the device. The integrated SBD as a unipolar device can effectively avoid these problems, reduce the cost of an additional parallel diode, and directly provide a reverse conduction path inside the MOSFET. In addition, the integrated SBD structure can optimize the reverse recovery process, reduce switching loss, and thus improve the efficiency and performance of the device under high-frequency working conditions. Furthermore, the integrated SBD structure directly contacts the epitaxial layer 120, which can provide a more stable reverse conduction path and avoid the thermal stress and defect expansion that may be caused by the body diode when it is turned on, thereby improving the long-term stability and reliability of the entire MOSFET device.

[0051] Therefore, the integrated SBD structure in the present application mainly solves the technical problems of low reliability and high switching loss of the MOSFET power device. By providing a unipolar reverse conduction path, optimizing the reverse recovery characteristics, and enhancing the overall performance and stability of the device.

[0052] In the embodiments of the present application, the material of the substrate can be silicon carbide, which can make the device have high thermal conductivity and high breakdown field strength, and is suitable for manufacturing high-performance devices that can work in high-temperature and high-pressure environments. For example, Figure 1As shown, the base includes a substrate 110 and an epitaxial layer 120. The doping concentration of the substrate 110 is higher than the doping concentration of the epitaxial layer 120. The high doping concentration of the substrate 110 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. The substrate 110 can also absorb carriers from the epitaxial layer 120, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 120 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance. It should be noted that the semiconductor device in the embodiment of the present application is not limited to SiC MOSFET, but can also be a Si-based MOSFET. Therefore, the substrate material of the semiconductor device is not limited to silicon carbide.

[0053] In the embodiments of this application, Figure 1 As shown, the split source region structure 20 may include a first implantation region 210 and a second implantation region 220. The first implantation region 210 is formed by ion implantation into a portion of the epitaxial layer 120, and the second implantation region 220 is formed by ion implantation into a portion of the first implantation region 210. The first implantation region 210 has the second doping type, and the second implantation region 220 has the first doping type. The second implantation region 220 ensures low contact resistance with the source lead to ensure good ohmic contact, allowing for smoother current flow when the device is in the on state, thereby improving the device's conductivity and efficiency. The combination of the first implantation region 210 and the second implantation region 220 can increase current density, improve ohmic contact, and reduce contact resistance in the source region.

[0054] Specifically, the doping type of the first implantation region 210 may be P-type, the doping ion may be Al element, and the doping concentration may be 1E13~E15cm -3 The doping depth can be 360~420nm; the doping type of the second injection region 220 can be N-type, the doping ion can be N element, and the doping concentration can be 1E13~5E14cm -3 , the doping depth can be 100~150nm.

[0055] In the above embodiments, the first doping type may be N-type doping or P-type doping, and the second doping type may be P-type doping or N-type doping, for example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element may be a pentavalent element including any one of phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element may be a trivalent element including any one of boron (B), aluminum (Al), and gallium (Ga), and the embodiments of the present application are not specifically limited thereto.

[0056] In some optional embodiments, such as Figure 1As shown, the semiconductor device also includes a doped semiconductor layer 70, which is located on the surface of the epitaxial layer 120 between at least one gate structure 40 and the Schottky metal layer 50, and the first source region 201 is in contact with the doped semiconductor layer 70 and the gate structure 40 respectively; the semiconductor device also includes a third injection region 60, which is located between the doped semiconductor layer 70 and a portion of the second injection region 220, and the third injection region 60 is a region formed by ion implantation into a side surface of a portion of the second injection region 220 in the first source region 201; wherein, the doped semiconductor layer 70 and the second injection region 220 have a first doping type, and the first injection region 210 and the third injection region 60 have a second doping type.

[0057] Specifically, the above-mentioned first doping type is N-type doping and the above-mentioned second doping type is P-type doping as an example for explanation. In the direction perpendicular to the substrate, the doped semiconductor layer 70, the third injection region 60, the second injection region 220 and the first injection region 210 are arranged to form an NPNP structure, which creates a controllable current path between the gate 420 and the split source region structure 20. The formation of the above-mentioned NPNP structure is based on the electrical characteristics of the PN junction. When the voltage of the gate 420 exceeds the safe range, the NPNP structure can be started, allowing current to be released through the PN junction, thereby protecting the gate 420 oxide layer from breakdown. The NPNP structure in the embodiment of the present application significantly improves the electrostatic protection level of the gate 420, reduces the contact resistance between the gate 420 and the doped region, and thereby reduces the switching energy consumption, especially in large resistance or high frequency applications.

[0058] In the above optional implementation manner, if Figure 1 As shown, the projection area of ​​the doped semiconductor layer 70 on the surface of the third injection region 60 can be greater than 1 / 2 of the surface area of ​​the third injection region 60. By the definition of the above area relationship, one side of the doped semiconductor layer 70 and the third injection region 60 (such as P + doped region) and can have a larger contact area, thereby reducing the contact resistance between the doped semiconductor layer 70 and the third injection region 60, so that the device has lower switching energy consumption in high resistance or high frequency applications.

[0059] In the above optional implementation manner, if Figure 1 As shown, the portion of the first injection region 210 located between the second injection region 220 and the epitaxial layer 120 has a first thickness, the portion of the second injection region 220 located between the first injection region 210 and the third injection region 60 has a second thickness, and the third injection region 60 has a third thickness, and both the second thickness and the third thickness are less than the first thickness.

[0060] Specifically, taking the first doping type as N-type doping and the second doping type as P-type doping as an example, the doped semiconductor layer 70, the third implantation region 60, the second implantation region 220, and the first implantation region 210 are arranged to form an NPNP structure. The thickness relationship limits the PN region in the middle part to be thin enough to meet the voltage resistance requirement of the first implantation region 210, thereby further improving the electrostatic protection level of the gate 420. When the voltage of the gate 420 exceeds the safe range, the integrated NPNP structure is turned on, and the current is released through the PN junction, which can protect the gate oxide layer from being broken down and improve the anti-static ability of the trench gate structure.

[0061] In some optional embodiments, as shown in FIG. 6, the semiconductor device in the embodiment of the present application further includes a fourth implantation region 30. The fourth implantation region 30 is located in the epitaxial layer 120 and in contact with the Schottky metal layer 50. The fourth implantation region 30 is formed by ion implantation on part of the first surface region, and has the second doping type. Figure 1

[0062] In the above optional embodiments, the orthographic projection of the fourth implantation region 30 on the first surface region can be located at the center of the first surface region. Since the voltage resistance of the Schottky junction is usually lower than that of the PN junction, a pure Schottky interface can cause a problem of reducing the voltage resistance of the device. The fourth implantation region 30 introduced in the present application is located below the Schottky metal layer 50. This region is located in the middle part of the entire Schottky barrier and is also the part where the electric field is most concentrated. Therefore, a high-voltage-resistant region can be formed at the weakest part of the Schottky interface, thereby improving the voltage resistance performance of the device as a whole.

[0063] In the above optional embodiments, the fourth implantation region 30 can be formed by the same implantation process as the third implantation region 60. The fourth implantation region 30 and the third implantation region 60 formed by synchronous implantation have the same doping concentration and depth. The use of the synchronous implantation process reduces the steps of separately forming the two implantation regions, thereby reducing the production cost. Moreover, by forming multiple implantation regions in a single process step, the process flow is simplified, and the production yield and consistency are improved.

[0064] In the embodiment of the present application, the voltage resistance capability of the device can be further improved by optimizing the depth of the fourth implantation region 30. In some optional embodiments, the fourth implantation region 30 is located in the epitaxial layer 120 and in contact with the Schottky metal layer 50. The depth of the fourth implantation region 30 is less than the depth of the split source region structure 20. In SiC MOSFET, the voltage resistance capability of the Schottky junction is usually lower than that of the PN junction. By introducing the fourth implantation region 30 (such as P + ​The fourth implantation region 30 can be a high-doped region. In this case, a local high-doped layer can be formed in the region where the electric field is most concentrated. The high-doped layer can help to establish a stronger electric field shielding effect in the region, thereby reducing the electric field intensity at the Schottky interface and avoiding the breakdown of the Schottky junction caused by the concentration of the electric field, and further improving the withstand voltage level of the entire device. In the embodiment of the present application, the depth of the fourth implantation region 30 is set to be less than the depth of the split source region structure 20, so that the shallow fourth implantation region 30 can enhance the stability of the Schottky junction without significantly affecting other performance parameters of the device, and ensure that the integrated SBD structure can still maintain its function under high voltage conditions.

[0065] It should be noted that the fourth implantation region 30 located below the Schottky metal layer 50 is not necessarily a high-doped region. When the fourth implantation region 30 is a P + doped region, the P + doped region can form a lower resistance region, which can help to reduce the local electric field intensity and prevent the breakdown of the Schottky junction caused by excessive concentration of the electric field.

[0066] For example, the material of the Schottky metal layer 50 is selected from any one or more of nickel (Ni), molybdenum (Mo), palladium (Pd), platinum (Pt), titanium (Ti) and tungsten (W), but is not limited to the above-mentioned types, and the present application does not make specific limitations.

[0067] In the embodiment of the present application, as shown in Figure 1 The gate structure 40 includes a gate dielectric layer 410 and a gate 420. The gate dielectric layer 410 is located on the surface of the substrate and contacts the split source region structure 20. The gate 420 is located on the side of the gate dielectric layer 410 away from the substrate. The gate structure 40 can control the formation and closing of the channel by applying a voltage, thereby determining the on and off states of the device.

[0068] Specifically, the material of the gate dielectric layer 410 can be an oxide or a nitride, such as SiO2 and Si3N4, and the thickness can be 0.03-0.08 μm. The material of the gate 420 can be polysilicon. The types and thicknesses of the gate dielectric layer 410 and the gate 420 are not specifically limited in the embodiment of the present application.

[0069] In the embodiment of the present application, as shown in Figure 1As shown, the semiconductor device also includes an insulating dielectric layer 80, a first metal layer 101 and a second metal layer 102. The insulating dielectric layer 80 is located on the side of the substrate having the epitaxial layer 120. The first portion 810 of the insulating dielectric layer 80 covers the gate structure 40, and the second portion 820 of the insulating dielectric layer 80 covers the doped semiconductor layer 70. A first source contact hole is provided between the first portion 810 and the second portion 820. The second source region 202 contacts the third portion 830 of the insulating dielectric layer 80 and the gate structure 40, respectively, and a second source contact hole is provided between the first portion 810 and the third portion 830.

[0070] Specifically, the material of the above-mentioned insulating dielectric layer 80 can be oxide and / or nitride, such as SiO2 and Si3N4, and a source contact hole is formed therein that penetrates to the source structure, and part of the first metal layer 101 is filled in the above-mentioned source contact hole. The above-mentioned first source contact hole penetrates to the surface of the split source region structure 20 (i.e., the first source region 201) located between the gate structure 40 and the doped semiconductor layer 70, and the above-mentioned second source contact hole penetrates to the surface of the split source region structure 20 (i.e., the second source region 202) located between the gate structure 40 and the insulating dielectric layer 80.

[0071] Specifically, by depositing metal materials, the first metal layer 101 formed in the source contact hole forms a good ohmic contact with the split source structure 20 (specifically, the second injection region 220 therein), ensuring that current can efficiently flow from the external circuit to the source of the device. In SiC MOSFET devices, ohmic contact metals can include Ni (nickel), Ti (titanium), Al (aluminum), Cu (copper), Ag (silver), etc. These metals form contact with the SiC material of the split source structure 20, reducing contact resistance and improving current transmission efficiency.

[0072] Specifically, by depositing a metal material, an ohmic contact can be formed between the formed second metal layer 102 and the SiC substrate 110 through appropriate metal deposition and processing, ensuring efficient current flow from the drain of the device. Similarly, the metal selection here can also take into account good contact performance with the SiC material and ensure low contact resistance at high current density.

[0073] In some optional embodiments, such as Figure 1As shown, the fourth injection region 30 is located between the first source region 201 and the second source region 202. The above-mentioned symmetrical arrangement helps to balance the electric field on both sides of the device and reduce the impact of electric field distortion on device performance. The symmetrical fourth injection region 30 can ensure that the current is evenly distributed on both sides of the device, avoiding local damage caused by current concentration. The symmetrical design in the embodiment of the present application improves the withstand voltage and current carrying capacity of the device, while reducing switching losses and improving the overall performance of the device. In other embodiments, the width and position of the fourth injection region 30 can be adjusted to further optimize the electric field distribution and solve the problem of reduced withstand voltage of the structure after integrating SBD.

[0074] In some optional embodiments, such as Figure 1 As shown, the semiconductor device also includes: a third source region 203, located in the epitaxial layer 120, and the third source region 203 and the second source region 202 are respectively in contact with the same gate structure 40; a fifth injection region 90, located in the third source region 203, and the depth of the fifth injection region 90 is greater than the depth of the fourth injection region 30 and the depth of the third injection region 60.

[0075] Specifically, the fifth implantation region 90 (such as P + doped region) is used to prevent device latch-up. The principle of the fifth injection region 90 to prevent device latch-up is mainly based on the control of parasitic transistors (i.e., parasitic NPN or PNP structures) inside the semiconductor device. Latch-up effect is a parasitic phenomenon that is undesirable in certain circumstances. It may cause high current to flow through the device and cause damage. In SiC MOSFET devices, this effect is usually caused by the positive feedback mechanism of the parasitic NPN or PNP transistor being triggered. When the gate 420 voltage is abnormal or an ESD (electrostatic discharge) event occurs, if the parasitic transistor inside the device (for example, an NPN structure composed of an N-type epitaxial layer 120, a P-type first injection region 210, and an N-type second injection region 220) is inadvertently activated, a low-resistance path may be formed, causing a large amount of current to flow through the device uncontrollably, causing overheating and possible permanent damage. The fifth injection region 90 (such as P + The introduction of the fifth injection region 90 provides sufficient holes (P-type carriers) to neutralize the excess electrons generated in the N-type region, thereby breaking the positive feedback mechanism of the parasitic transistor. Furthermore, the introduction of the fifth injection region 90 modifies the electric field distribution within the device, rendering the electric field strength in certain regions insufficient to trigger the parasitic transistor to turn on, thereby preventing latch-up. This fifth injection region 90 ensures that even during the initial stages of latch-up, current is guided and controlled through a predetermined path (typically one designed for low impedance), preventing a sudden surge in current and thus protecting the device from damage.

[0076] According to the embodiments of the present application, a preparation method of a semiconductor device is provided for preparing the semiconductor device as described above, as shown in the following. Figure 2 The preparation method comprises the following steps:

[0077] In step S1, a substrate is provided, which comprises a substrate and an epitaxial layer stacked along a first direction;

[0078] In step S2, ion implantation is performed on one side surface of the epitaxial layer to form a split source region structure, which comprises a first source region and a second source region spaced apart along a direction parallel to the surface of the substrate, and a surface of the epitaxial layer between the first source region and the second source region in the same split source region is a first surface region;

[0079] In step S3, a plurality of gate structures are formed on the substrate, so that the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures;

[0080] In step S4, a Schottky metal layer is formed on the first surface region.

[0081] In the preparation method provided in the above embodiments, ion implantation is performed on one side surface of the epitaxial layer to form a split source region structure in the epitaxial layer, a surface of the epitaxial layer between the first source region and the second source region in the same split source region is a first surface region, ion implantation is performed on part of the first surface region to form a fourth implantation region, and a Schottky metal layer is formed on the first surface region. The Schottky metal layer introduced above directly contacts the epitaxial layer, and a Schottky barrier diode (SBD) structure is integrated in the device. In a conventional MOSFET, a body diode is used to provide a conduction path for current when the device is in reverse bias. However, the conduction mechanism of the body diode is bipolar, which may cause the expansion of epitaxial layer defects under high heat and large current conditions, affecting the reliability and life of the device. The integrated SBD as a unipolar device can effectively avoid these problems, while reducing the cost of an additional parallel diode, and directly providing a reverse conduction path inside the MOSFET. In addition, the integrated SBD structure can optimize the reverse recovery process to reduce switching loss, thereby improving the efficiency and performance of the device under high-frequency operating conditions. Furthermore, the integrated SBD structure directly contacts the epitaxial layer, which can provide a more stable reverse conduction path, avoiding the thermal stress and defect expansion that may be caused by the body diode when turned on, thereby improving the long-term stability and reliability of the entire MOSFET device.

[0082] The following will describe in more detail exemplary embodiments of the method for preparing a semiconductor device according to the embodiments of the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0083] First, proceed to step S1: Figure 3 As shown, a substrate is provided, which includes a substrate 110 and an epitaxial layer 120 stacked along a first direction.

[0084] In some optional embodiments, the present application further includes the steps of forming the aforementioned base: providing a substrate 110 made of silicon carbide; and forming an epitaxial layer 120 on the substrate 110 using an epitaxial process. Specifically, the epitaxial layer 120 may be made of silicon carbide, and the material of the substrate 110 includes, but is not limited to, semiconductor materials such as silicon, silicon carbide, and gallium nitride, which are not specifically limited in this application.

[0085] In the above optional embodiment, the doping type of the substrate 110 and the epitaxial layer 120 is not specifically limited in the embodiment of the present application. Specifically, the above semiconductor device can be a SiC MOSFET, and the substrate 110 and the epitaxial layer 120 in the silicon carbide device can have the same doping type. For example, the substrate 110 is a highly doped N + Type silicon carbide material, and the substrate 110 has a drain, and the epitaxial layer 120 is lightly doped N - type silicon carbide material, and the epitaxial layer 120 includes a drift region, in which a source is formed.

[0086] After providing a base including a substrate 110 and an epitaxial layer 120, step S2 is performed: Figure 4 and Figure 5 As shown, ion implantation is performed on a side surface of a portion of the epitaxial layer 120 to form a split source region structure 20 . The split source region structure 20 includes a first source region 201 and a second source region 202 spaced apart in a direction parallel to the substrate surface.

[0087] Furthermore, step S2 may also include: Figure 6 As shown, ion implantation is performed on a portion of the first surface region to form a fourth implantation region 30 . The first surface region is the surface of the epitaxial layer 120 located between the first source region 201 and the second source region 202 in the same split source region structure 20 .

[0088] The fourth implantation region 30 is formed in the epitaxial layer 120 and is in contact with the Schottky metal layer 50, and the orthographic projection of the fourth implantation region 30 on the first surface region can be located at the center of the first surface region. Since the withstand voltage of the Schottky junction is generally lower than that of the PN junction, a pure Schottky interface can cause a problem of reduced device withstand voltage. The fourth implantation region 30 introduced in the present application is located below the Schottky metal layer 50, and the region is located in the middle part of the entire Schottky barrier and is also the part where the electric field is most concentrated, so that a high-voltage-resistant region can be formed at the weakest part of the Schottky interface, thereby improving the withstand voltage performance of the device as a whole.

[0089] In some optional embodiments, the steps of forming the split source region structure 20 and the fourth implantation region 30 include: as shown in Figure 4 and Figure 5 performing ion implantation on one side surface of part of the epitaxial layer 120 to form a first implantation region 210, and performing ion implantation on one side surface of part of the first implantation region 210 to form a second implantation region 220; as shown in Figure 6 performing ion implantation on one side surface of part of the second implantation region 220 in the first source region 201 and part of the first surface region to form a third implantation region 60 and a fourth implantation region 30, and part of the first implantation region 210 and the second implantation region 220 located between the third implantation region 60 and the first implantation region 210 is in contact with the gate structure 40.

[0090] Specifically, the above-mentioned first doping type is N-type doping, and the above-mentioned second doping type is P-type doping. The ion implantation step constructs a complex doping region structure and forms an NPNP structure for improving the electrostatic protection level of the gate 420. By accurately controlling the energy and dose of implantation, doping regions of the required depth and concentration can be formed in the epitaxial layer 120, and the combination of these doping regions forms an NPNP structure which can be activated to release excess electrostatic energy when the voltage of the gate 420 is too high, thereby protecting the gate oxide layer. The technology in the embodiments of the present application significantly enhances the anti-static ability of the gate 420, reduces the switching energy consumption, and especially in high-frequency and high-resistance applications.

[0091] In the above-optional embodiments, the fourth implantation region 30 and the third implantation region 60 are formed by the same implantation process. The use of a synchronous implantation process reduces the steps of separately forming the two implantation regions, thereby reducing production costs, and by forming multiple implantation regions in a single process step, the process flow is simplified, and the production yield and consistency are improved.

[0092] After the steps of forming the split source region structure 20 and the fourth implantation region 30, step S3 is performed: as shown in Figures 7 to 10As shown, a gate structure 40 is formed on the substrate. The gate structure 40 is located on the surface of the substrate and contacts the split source region structure 20 .

[0093] After forming the split source region structure 20 and the fourth implantation region 30, the preparation method in the embodiment of the present application may include: Figure 7 As shown, a gate dielectric layer 410 is formed on the substrate surface in contact with the split source region structure 20, and then as shown in FIG. Figure 8 As shown, a gate 420 is formed on the gate dielectric layer 410; then as shown in FIG. Figure 9 and Figure 10 As shown, one side of the substrate having the epitaxial layer 120 is covered with an insulating material layer 801, and the insulating material layer 801 is etched to form an insulating dielectric layer 80 having a source contact hole, wherein a source contact hole is formed that passes through to the source structure, and a portion of the first metal layer 101 is filled in the above-mentioned source contact hole. The above-mentioned first source contact hole passes through to the surface of the split source region structure 20 (i.e., the first source region 201) located between the gate structure 40 and the doped semiconductor layer 70, and the above-mentioned second source contact hole passes through to the surface of the split source region structure 20 (i.e., the second source region 202) located between the gate structure 40 and the insulating dielectric layer 80.

[0094] Exemplarily, the gate 420 formed in the above step S3 is made of N-type polysilicon material, and the materials of the gate dielectric layer 410 and the insulating material layer 801 are SiO2, but are not limited to the above types and are not specifically limited in this application.

[0095] After forming the gate structure 40, step S4 is performed: Figure 11 As shown, a Schottky metal layer 50 is formed on a first surface region, which is a surface of the epitaxial layer 120 located between the first source region 201 and the second source region 202 in the same split source region structure 20 .

[0096] Specifically, the steps of forming the above-mentioned Schottky metal layer 50 include: depositing a metal material on the substrate to cover a first surface area on the surface of the gate dielectric layer 410 and the epitaxial layer 120, then covering with a mask layer, and patterning the mask layer to expose the metal material on the surface of the gate dielectric layer 410, and then etching the exposed metal material. The remaining metal material is located on the first surface area to form the Schottky metal layer 50.

[0097] Exemplarily, the material of the Schottky metal layer 50 is selected from any one or more of nickel (Ni), molybdenum (Mo), palladium (Pd), platinum (Pt), titanium (Ti) and tungsten (W), but is not limited to the above types and is not specifically limited in this application.

[0098] After the step of forming the Schottky metal layer 50, as shown in FIG. Figure 1As shown, a metal material is deposited on the side of the substrate having the insulating dielectric layer 80, and a first metal layer 101 formed in the source contact hole forms a good ohmic contact with the split source region structure 20 (specifically, the second injection region 220 therein), thereby ensuring that current can efficiently flow from the external circuit into the source of the device; and a metal material is deposited on the side of the substrate having the substrate 110 to form a second metal layer 102. Through appropriate metal deposition and processing, an ohmic contact can also be formed between the second metal layer 102 and the SiC substrate 110, thereby ensuring that current can efficiently flow out of the drain of the device.

[0099] Illustratively, the materials of the first metal layer 101 and the second metal layer 102 are selected from any one or more of nickel (Ni), molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu), but are not limited to the above types, and this application does not make specific limitations.

[0100] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0101] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: A base, comprising a stacked substrate and an epitaxial layer, wherein the epitaxial layer has a first doping type; a split source region structure located in the epitaxial layer, the split source region structure being a region formed by ion implantation into a portion of a surface of one side of the epitaxial layer, and comprising a first source region and a second source region spaced apart in a direction parallel to the substrate surface; a plurality of gate structures, located on the surface of the substrate, wherein the first source region and the second source region in the same split source region are in contact with different and adjacent gate structures respectively; The Schottky metal layer is located on a first surface region, where the first surface region is a surface of the epitaxial layer located between the first source region and the second source region in the same split source region structure.

2. The semiconductor device according to claim 1, wherein The first source region and the second source region each include a first implantation region and a second implantation region, the first implantation region being a region formed by ion implantation into a portion of a side surface of the epitaxial layer, and the second implantation region being a region formed by ion implantation into a portion of a side surface of the first implantation region, the semiconductor device further comprising: a doped semiconductor layer located on a surface of the epitaxial layer between at least one of the gate structures and the Schottky metal layer, wherein the first source region is in contact with the doped semiconductor layer and the gate structure, respectively; a third implantation region, located between the doped semiconductor layer and a portion of the second implantation region, the third implantation region being formed by ion implantation into a surface of a portion of the second implantation region in the first source region; The first injection region and a portion of the second injection region located between the third injection region and the first injection region are in contact with the gate structure, the doped semiconductor layer and the second injection region have the first doping type, and the first injection region and the third injection region have the second doping type.

3. The semiconductor device according to claim 2, wherein A portion of the first injection region located between the second injection region and the epitaxial layer has a first thickness, a portion of the second injection region located between the first injection region and the third injection region has a second thickness, and the third injection region has a third thickness, and both the second thickness and the third thickness are smaller than the first thickness.

4. The semiconductor device according to claim 2 or 3, characterized in that Also includes: A fourth implantation region is located in the epitaxial layer and contacts the Schottky metal layer. The fourth implantation region is formed by ion implantation into a portion of the first surface region, and the fourth implantation region has a second doping type.

5. The semiconductor device according to claim 4, wherein The fourth implantation region has the same doping concentration and depth as the third implantation region.

6. The semiconductor device according to claim 4, wherein Also includes: An insulating dielectric layer is located on the side of the substrate having the epitaxial layer, a first portion of the insulating dielectric layer covers the gate structure, a second portion of the insulating dielectric layer covers the doped semiconductor layer, and a first source contact hole is defined between the first portion and the second portion.

7. The semiconductor device according to claim 6, wherein: The second source region is in contact with a third portion of the insulating dielectric layer and the gate structure respectively, and a second source contact hole is provided between the first portion and the third portion.

8. The semiconductor device according to claim 6, wherein Also includes: a third source region located in the epitaxial layer, wherein the third source region and the second source region are respectively in contact with the same gate structure; A fifth injection region is located in the third source region, and a depth of the fifth injection region is greater than a depth of the fourth injection region and a depth of the third injection region.

9. A method for preparing a semiconductor device, characterized in that: For preparing a semiconductor device according to any one of claims 1 to 8, the preparation method comprises: Providing a substrate, the substrate comprising a substrate and an epitaxial layer stacked along a first direction; Ion implantation is performed on a side surface of a portion of the epitaxial layer to form a split source region structure, wherein the split source region structure includes a first source region and a second source region spaced apart in a direction parallel to the substrate surface, and a surface of the epitaxial layer located between the first source region and the second source region in the same split source region is a first surface region; forming a plurality of gate structures on the substrate so that the first source region and the second source region in the same split source region are in contact with different and adjacent gate structures respectively; A Schottky metal layer is formed on the first surface region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The steps of forming the split source region structure include: Performing ion implantation on a portion of a side surface of the epitaxial layer to form a first implantation region, and performing ion implantation on a portion of a side surface of the first implantation region to form a second implantation region; The preparation method further comprises the following steps: Ion implantation is performed simultaneously on a side surface of a portion of the second injection region in the first source region and a portion of the first surface area to form a third injection region and a fourth injection region, and the first injection region and the portion of the second injection region located between the third injection region and the first injection region are in contact with the gate structure.

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