Semiconductor devices and their fabrication methods

Abstract

This application discloses a semiconductor device and its fabrication method. The semiconductor device includes: a substrate comprising a stacked substrate and an epitaxial layer, the epitaxial layer having a first doping type; a split source region structure located in the epitaxial layer, the split source region structure being a region formed by ion implantation of a portion of one surface of the epitaxial layer, and the split source region structure including a first source region and a second source region spaced apart along a direction parallel to the substrate surface; multiple gate structures located on the substrate surface, the first source region and the second source region in the same split source region respectively contacting different and adjacent gate structures; and a Schottky metal layer located on a first surface region, the first surface region being the surface of the epitaxial layer located between the first source region and the second source region in the same split source region structure. This application solves the technical problems of low reliability and high switching losses in SiC MOSFET power devices.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for fabricating the same. Background Technology

[0002] In the field of semiconductor devices, especially in power electronic applications, silicon carbide (SiC) MOSFETs have become an indispensable part of power electronic systems due to their superior performance, such as high breakdown voltage, low forward voltage drop, high switching speed, and ease of gate control. However, SiC MOSFETs have limitations in some key performance aspects, particularly in terms of electrostatic discharge (ESD) resistance. Compared to traditional Si-based MOSFETs, SiC MOSFETs have a thinner gate oxide layer, resulting in lower ESD resistance. This weakness means that when the device is subjected to an accidental ESD event, the gate oxide layer may be damaged, thus affecting the reliability and lifespan of the device.

[0003] Furthermore, the high-frequency operating characteristics of SiC MOSFETs also face challenges. In high-frequency applications, due to the high contact resistance between the gate and source regions, SiC MOSFETs may exhibit high switching losses, limiting their application in high-frequency power electronic converters. The robustness of the body diode is also an important consideration. It acts as the current path under reverse voltage, but under high temperature and high current conditions, it may induce the propagation of epitaxial layer defects, thereby degrading the overall performance of the device.

[0004] Another related technical issue is the impact of the integrated Schottky diode (SBD) structure on the overall device voltage withstand capability. Although integrating an SBD can optimize the reverse conduction performance of the device, the voltage withstand capability of a Schottky junction is lower than that of a traditional PN junction. This may reduce the overall voltage withstand level of the device to some extent, limiting its application in high-voltage environments.

[0005] In summary, existing SiC MOSFETs exhibit significant shortcomings in terms of electrostatic discharge (ESD) immunity, high-frequency switching losses, body diode robustness, and device breakdown voltage after SBD integration. To address these deficiencies, a newer MOSFET is needed that is more suitable for the stringent requirements of modern power electronic systems. Summary of the Invention

[0006] This application provides a semiconductor device and its fabrication method to solve the problems of low reliability and high switching losses in MOSFET power devices in related technologies.

[0007] According to one aspect of this application, a semiconductor device is provided, comprising:

[0008] The substrate includes a stacked substrate and an epitaxial layer, the epitaxial layer having a first doping type;

[0009] A split source region structure is located in the epitaxial layer. The split source region structure is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface.

[0010] Multiple gate structures are located on the substrate surface, and the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures;

[0011] A Schottky metal layer is located on a first surface region, which is the surface of the epitaxial layer located between the first source region and the second source region in the same split source region structure.

[0012] Optionally, both the first source region and the second source region include a first implantation region and a second implantation region. The first implantation region is a region formed by ion implantation of a portion of one side surface of the epitaxial layer, and the second implantation region is a region formed by ion implantation of a portion of one side surface of the first implantation region. The semiconductor device further includes: a doped semiconductor layer located on the surface of the epitaxial layer between at least one of the gate structures and the Schottky metal layer, wherein the first source region is in contact with the doped semiconductor layer and the gate structure; and a third implantation region located between the doped semiconductor layer and a portion of the second implantation region, wherein the third implantation region is a region formed by ion implantation of a portion of one side surface of the second implantation region in the first source region. The portion of the first implantation region and the portion of the second implantation region located between the third implantation region and the first implantation region is in contact with the gate structure. The doped semiconductor layer and the second implantation region have the first doping type, and the first implantation region and the third implantation region have the second doping type.

[0013] Optionally, the portion of the first injection region located between the second injection region and the epitaxial layer has a first thickness, the portion of the second injection region located between the first injection region and the third injection region has a second thickness, and the third injection region has a third thickness, wherein both the second thickness and the third thickness are less than the first thickness.

[0014] Optionally, the semiconductor device further includes: a fourth implantation region located in the epitaxial layer and in contact with the Schottky metal layer, the fourth implantation region being a region formed by ion implantation of a portion of the first surface region, and the fourth implantation region having a second doping type.

[0015] Optionally, the fourth implantation region has the same doping concentration and depth as the third implantation region.

[0016] Optionally, the semiconductor device further includes: an insulating dielectric layer located on one side of the substrate having the epitaxial layer, a first portion of the insulating dielectric layer covering the gate structure, a second portion of the insulating dielectric layer covering the doped semiconductor layer, and a first source contact hole between the first portion and the second portion.

[0017] Optionally, the second source region is in contact with the third portion in the insulating dielectric layer and the gate structure, respectively, and a second source contact hole is provided between the first portion and the third portion.

[0018] Optionally, the semiconductor device further includes: a third source region located in the epitaxial layer, wherein the third source region and the second source region are respectively in contact with the same gate structure; and a fifth implantation region located in the third source region, wherein the depth of the fifth implantation region is greater than the depth of the fourth implantation region and the depth of the third implantation region.

[0019] According to one aspect of this application, a method for fabricating a semiconductor device is provided, the method comprising:

[0020] A substrate is provided, the substrate comprising a substrate and an epitaxial layer stacked along a first direction;

[0021] Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a split source region structure. The split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface. The surface of the epitaxial layer located between the first source region and the second source region in the same split source region is a first surface region.

[0022] Multiple gate structures are formed on the substrate such that the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures;

[0023] A Schottky metal layer is formed on the first surface region.

[0024] Optionally, the step of forming the split source region structure includes: performing ion implantation on one side surface of a portion of the epitaxial layer to form a first implantation region, and performing ion implantation on one side surface of a portion of the first implantation region to form a second implantation region; the fabrication method further includes the following steps: simultaneously performing ion implantation on one side surface of a portion of the second implantation region in the first source region and a portion of the first surface region to form a third implantation region and a fourth implantation region, wherein the portion of the first implantation region and the second implantation region located between the third implantation region and the first implantation region is in contact with the gate structure.

[0025] According to this application, in a semiconductor device, a split source region structure is located in the epitaxial layer. This split source region structure is a region formed by ion implantation onto one side surface of a portion of the epitaxial layer. The split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface. A Schottky metal layer is located on the first surface region, which is the surface of the epitaxial layer located between the first and second source regions within the same split source region. The introduced Schottky metal layer is in direct contact with the epitaxial layer, thus integrating a Schottky barrier diode into the device. The integrated SBD (Side Diode) structure addresses the issues of low reliability and high switching losses in traditional MOSFETs. While the body diode provides a current conduction path when the device is reverse biased, its bipolar conduction mechanism can lead to epitaxial layer defect propagation under high heat and high current conditions, impacting device reliability and lifespan. The integrated SBD, a unipolar device, effectively avoids these problems and reduces the cost of additional parallel diodes by providing a direct reverse conduction path within the MOSFET. Furthermore, the integrated SBD structure optimizes the reverse recovery process, reducing switching losses and improving device efficiency and performance at high frequencies. Additionally, the direct contact with the epitaxial layer provides a more stable reverse conduction path, preventing thermal stress and defect propagation that can occur with the body diode during conduction, thus enhancing the long-term stability and reliability of the entire MOSFET device. Therefore, the integrated SBD structure in this application primarily solves the technical problems of low reliability and high switching losses in MOSFET power devices by providing a unipolar reverse conduction path and optimizing reverse recovery characteristics, thereby enhancing the overall device performance and stability. Attached Figure Description

[0026] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 A cross-sectional structural schematic diagram of a semiconductor device according to an embodiment of this application is shown;

[0028] Figure 2 A schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application is shown;

[0029] Figure 3 A schematic cross-sectional structure of a substrate is shown in a method for fabricating a semiconductor device.

[0030] Figure 4 It shows in Figure 3A schematic diagram of the cross-sectional structure of the matrix after the first injection region is formed in the epitaxial layer;

[0031] Figure 5 It shows in Figure 4 A schematic diagram of the cross-sectional structure of the matrix after the second injection region is formed in the first injection region;

[0032] Figure 6 It shows in Figure 5 A schematic diagram of the cross-sectional structure of the matrix after the formation of the third and fourth injection regions in the matrix;

[0033] Figure 7 It shows in Figure 6 A schematic diagram of the cross-sectional structure of the substrate after the gate dielectric layer is formed on the substrate;

[0034] Figure 8 It shows in Figure 7 A schematic cross-sectional view of the substrate formed on the gate dielectric layer in the diagram.

[0035] Figure 9 It shows in Figure 8 A schematic diagram of the cross-sectional structure of the substrate after an insulating material layer covering the gate structure is formed on the substrate.

[0036] Figure 10 It shows that Figure 9 A schematic diagram of the cross-sectional structure of the substrate after the insulating material layer is etched to form the insulating dielectric layer;

[0037] Figure 11 It shows in Figure 10 A schematic diagram of the cross-sectional structure of the substrate after a Schottky metal layer is formed on the first surface region.

[0038] The above figures include the following reference numerals:

[0039] 110, Epitaxial layer; 120, Substrate; 20, Split source region structure; 201, First source region; 202, Second source region; 203, Third source region; 210, First implantation region; 220, Second implantation region; 30, Fourth implantation region; 40, Gate structure; 410, Gate dielectric layer; 420, Gate; 50, Schottky metal layer; 60, Third implantation region; 70, Doped semiconductor layer; 80, Insulating dielectric layer; 801, Insulating material layer; 810, First portion; 820, Second portion; 830, Third portion; 90, Fifth implantation region; 101, First metal layer; 102, Second metal layer. Detailed Implementation

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0042] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] As described in the background section, existing SiC MOSFETs exhibit significant drawbacks in terms of electrostatic discharge (ESD) immunity, high-frequency switching losses, robustness of the body diode, and breakdown voltage after integrating a signal diode (SBD). To address these shortcomings, there is a need for a MOSFET that is more suitable for the stringent requirements of modern power electronic systems. To solve the aforementioned technical problems, embodiments of this application provide a semiconductor device and a method for fabricating the same.

[0044] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0045] According to one embodiment of this application, a semiconductor device is provided, such as... Figure 1 As shown, it includes:

[0046] The substrate includes a stacked substrate 120 and an epitaxial layer 110, the epitaxial layer 110 having a first doping type;

[0047] The split source region structure 20 is located in the epitaxial layer 110. The split source region structure 20 is a region formed by ion implantation on one side surface of a portion of the epitaxial layer 110, and the split source region structure 20 includes a first source region 201 and a second source region 202 spaced apart along a direction parallel to the substrate surface.

[0048] Multiple gate structures 40 are located on the substrate surface, and the first source region 201 and the second source region 202 in the same split source region structure 20 are in contact with different and adjacent gate structures 40 respectively.

[0049] Schottky metal layer 50 is located on a first surface region, which is the surface of epitaxial layer 110 located between first source region 201 and second source region 202 in the same split source region structure 20.

[0050] In the semiconductor device provided in the above embodiments, multiple split source region structures 20 are spaced apart in the epitaxial layer 110. Each split source region structure 20 is a region formed by ion implantation onto one side surface of a portion of the epitaxial layer 110. A Schottky metal layer 50 is located on a first surface region, which is the surface of the epitaxial layer 110 between the first source region 201 and the second source region 202 in the same split source region structure 20. The introduced Schottky metal layer 50 is in direct contact with the epitaxial layer 110, thus integrating a Schottky barrier diode in the device. The integrated SBD (Side Diode) structure addresses these issues in traditional MOSFETs. While the body diode provides a current conduction path when the device is reverse biased, its bipolar conduction mechanism can lead to the propagation of defects in the epitaxial layer 110 under high heat and high current conditions, impacting device reliability and lifespan. The integrated SBD, a unipolar device, effectively avoids these problems and reduces the cost associated with additional parallel diodes, providing a direct reverse conduction path within the MOSFET. Furthermore, the integrated SBD structure optimizes the reverse recovery process, reducing switching losses and improving device efficiency and performance under high-frequency operating conditions. Additionally, the integrated SBD structure, through direct contact with the epitaxial layer 110, provides a more stable reverse conduction path, avoiding thermal stress and defect propagation that may occur when the body diode is on, thus enhancing the long-term stability and reliability of the entire MOSFET device.

[0051] Therefore, the integrated SBD structure in this application mainly solves the technical problems of low reliability and high switching loss of MOSFET power devices. By providing a unipolar reverse conduction path, it optimizes the reverse recovery characteristics and enhances the overall performance and stability of the device.

[0052] In this embodiment, the substrate material can be silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figure 1As shown, the substrate includes a substrate 120 and an epitaxial layer 110. The doping concentration of the substrate 120 is higher than that of the epitaxial layer 110. The higher doping concentration of the substrate 120 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 120 can absorb carriers from the epitaxial layer 110, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 110 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance. It should be noted that the semiconductor device in this embodiment is not limited to a SiC MOSFET, but can also be a Si-based MOSFET. Therefore, the substrate material of the semiconductor device is not limited to silicon carbide.

[0053] In the embodiments of this application, such as Figure 1 As shown, the split source region structure 20 may include a first implantation region 210 and a second implantation region 220. The first implantation region 210 is a region formed by ion implantation of a portion of one surface of the epitaxial layer 110, and the second implantation region 220 is a region formed by ion implantation of a portion of one surface of the first implantation region 210. The first implantation region 210 has a second doping type, and the second implantation region 220 has a first doping type. The second implantation region 220 ensures low contact resistance with the source lead to ensure good ohmic contact, making current transmission smoother in the on-state and improving the conductivity and efficiency of the device. The combination of the first implantation region 210 and the second implantation region 220 can increase current density, improve ohmic contact, and reduce the contact resistance of the source region.

[0054] Specifically, the doping type of the first implantation region 210 can be P-type, the dopant ion can be Al, and the doping concentration can be 1E13~E15cm. -3 The doping depth can be 360~420nm; the doping type of the second implantation region 220 can be N-type, the doping ion can be nitrogen element, and the doping concentration can be 1E13~5E14cm. -3 The doping depth can be 100~150nm.

[0055] In the above embodiments, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping. For example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). The embodiments of this application do not specifically limit the type of doping.

[0056] In some alternative implementations, such as Figure 1As shown, the semiconductor device further includes a doped semiconductor layer 70, which is located on the surface of an epitaxial layer 110 between at least one gate structure 40 and a Schottky metal layer 50. The first source region 201 is in contact with the doped semiconductor layer 70 and the gate structure 40, respectively. The semiconductor device also includes a third implantation region 60, which is located between the doped semiconductor layer 70 and a portion of the second implantation region 220. The third implantation region 60 is a region formed by ion implantation of one side surface of a portion of the second implantation region 220 in the first source region 201. The doped semiconductor layer 70 and the second implantation region 220 have a first doping type, and the first implantation region 210 and the third implantation region 60 have a second doping type.

[0057] Specifically, the following example illustrates the first doping type as N-type doping and the second doping type as P-type doping. In the direction perpendicular to the substrate, the doped semiconductor layer 70, the third implantation region 60, the second implantation region 220, and the first implantation region 210 are arranged to form an NPNP structure, creating a controllable current path between the gate 420 and the split source region structure 20. The formation of the NPNP structure is based on the electrical characteristics of a PN junction. When the gate 420 voltage exceeds the safe range, the NPNP structure can activate, allowing current to be released through the PN junction, thereby protecting the gate 420 oxide layer from breakdown. The NPNP structure in this embodiment significantly improves the electrostatic discharge protection level of the gate 420 and reduces the contact resistance between the gate 420 and the doped region, thereby reducing switching power consumption, especially in high-resistance or high-frequency applications.

[0058] In the above optional implementations, such as Figure 1 As shown, the projected area of ​​the doped semiconductor layer 70 on the surface of the third implantation region 60 can be greater than half the area of ​​the surface of the third implantation region 60. By defining the area relationship described above, one side of the doped semiconductor layer 70 and the third implantation region 60 (e.g., P...) are connected. + The doped region has a large contact area, which reduces the contact resistance between the doped semiconductor layer 70 and the third implantation region 60, enabling the device to have low switching power consumption in high resistance or high frequency applications.

[0059] In the above optional implementations, such as Figure 1 As shown, the portion of the first injection region 210 located between the second injection region 220 and the epitaxial layer 110 has a first thickness, the portion of the second injection region 220 located between the first injection region 210 and the third injection region 60 has a second thickness, and the third injection region 60 has a third thickness. Both the second thickness and the third thickness are less than the first thickness.

[0060] Specifically, taking the first doping type as N-type doping and the second doping type as P-type doping as examples, the doped semiconductor layer 70, the third implantation region 60, the second implantation region 220 and the first implantation region 210 are arranged to form an NPNP structure. By limiting the thickness relationship, the PN region in the middle part is thin enough to meet the voltage withstand requirement of the first implantation region 210 and further improve the electrostatic discharge protection level of the gate 420. When the voltage of the gate 420 exceeds the safe range, the integrated NPNP structure will be turned on, and the current will be released through the PN junction, which can protect the gate oxide layer from being broken down and improve the antistatic capability of the trench gate structure.

[0061] In some alternative implementations, such as Figure 1 As shown, the semiconductor device in this embodiment further includes a fourth implantation region 30, which is located in the epitaxial layer 110 and in contact with the Schottky metal layer 50. The fourth implantation region 30 is a region formed by ion implantation of a portion of the first surface region, and the fourth implantation region 30 has a second doping type.

[0062] In the above optional embodiments, the orthographic projection of the fourth injection region 30 on the first surface region can be located at the center of the first surface region. Since the breakdown voltage of the Schottky junction is usually lower than that of the PN junction, the pure Schottky interface will cause the device breakdown voltage to decrease. The fourth injection region 30 introduced in this application is located below the Schottky metal layer 50. This region is located in the middle part of the entire Schottky barrier and is also the part where the electric field is most concentrated. Thus, a high voltage-resistant region can be formed at the weakest point of the Schottky interface, thereby improving the overall breakdown voltage performance of the device.

[0063] In the above optional embodiments, the fourth implantation region 30 can be formed in the same implantation step as the third implantation region 60. The fourth implantation region 30 formed by simultaneous implantation has the same doping concentration and depth as the third implantation region 60. Using a simultaneous implantation process reduces the steps of forming these two implantation regions separately, thereby reducing production costs. Furthermore, by forming multiple implantation regions in a single process step, the process flow is simplified, and production yield and consistency are improved.

[0064] In this embodiment, the breakdown voltage of the device can be further improved by optimizing the depth of the fourth injection region 30. In some optional embodiments, the fourth injection region 30 is located in the epitaxial layer 110 and contacts the Schottky metal layer 50, and the depth of the fourth injection region 30 is less than the depth of the split source region structure 20. In SiC MOSFETs, the breakdown voltage of the Schottky junction is typically lower than that of the PN junction. By introducing a fourth injection region 30 (such as P...) near the Schottky interface... +The doped region can form a locally highly doped layer in the region where the electric field is most concentrated. This highly doped layer helps to establish a stronger electric field shielding effect in the region, thereby reducing the electric field strength at the Schottky interface, avoiding Schottky junction breakdown caused by electric field concentration, and thus improving the breakdown voltage level of the entire device. In this embodiment, by setting the depth of the fourth injection region 30 to be less than the depth of the split source region structure 20, the shallow fourth injection region 30 can enhance the stability of the Schottky junction without significantly affecting other performance parameters of the device, ensuring that the integrated SBD structure can still maintain its function under high voltage conditions.

[0065] It should be noted that the fourth implantation region 30 located below the Schottky metal layer 50 is not necessarily a highly doped region. When the fourth implantation region 30 is P... + In the doped region, P + The doped region can form a lower resistance region, which helps to reduce the local electric field strength and prevent the electric field from being too concentrated, thus causing the Schottky junction to break down.

[0066] For example, the material of the Schottky metal layer 50 is selected from one or more of nickel (Ni), molybdenum (Mo), palladium (Pd), platinum (Pt), titanium (Ti) and tungsten (W), but is not limited to the above types, and this application does not make any specific limitation.

[0067] In the embodiments of this application, such as Figure 1 As shown, the gate structure 40 includes a gate dielectric layer 410 and a gate 420. The gate dielectric layer 410 is located on the surface of the substrate and is in contact with the split source region structure 20. The gate 420 is located at least on the side of the gate dielectric layer 410 facing away from the substrate. The gate structure 40 can control the formation and shutdown of the channel by applying a voltage, thereby determining the on and off states of the device.

[0068] Specifically, the material of the gate dielectric layer 410 can be oxide, nitride, etc., such as SiO2 and Si3N4, and the thickness can be 0.03~0.08μm. The material of the gate 420 can be polysilicon. The embodiments of this application do not specifically limit the type and thickness of the gate dielectric layer 410 and the gate 420.

[0069] In the embodiments of this application, such as Figure 1As shown, the semiconductor device further includes an insulating dielectric layer 80, a first metal layer 101, and a second metal layer 102. The insulating dielectric layer 80 is located on one side of the substrate with an epitaxial layer 110. A first portion 810 of the insulating dielectric layer 80 covers the gate structure 40, and a second portion 820 of the insulating dielectric layer 80 covers the doped semiconductor layer 70. A first source contact hole is provided between the first portion 810 and the second portion 820. A second source region 202 is in contact with a third portion 830 of the insulating dielectric layer 80 and the gate structure 40, respectively. A second source contact hole is provided between the first portion 810 and the third portion 830.

[0070] Specifically, the material of the insulating dielectric layer 80 can be an oxide and / or a nitride, such as SiO2 and Si3N4, wherein a source contact hole is formed that extends to the source structure, a portion of the first metal layer 101 is filled in the source contact hole, the first source contact hole extends to the surface of the split source region structure 20 (i.e., the first source region 201) located between the gate structure 40 and the doped semiconductor layer 70, and the second source contact hole extends to the surface of the split source region structure 20 (i.e., the second source region 202) located between the gate structure 40 and the insulating dielectric layer 80.

[0071] Specifically, by depositing metal material, the first metal layer 101 formed in the source contact hole forms a good ohmic contact with the split source region structure 20 (specifically the second injection region 220 therein), ensuring that current can flow efficiently from the external circuit into the source of the device. In SiC MOSFET devices, the ohmic contact metal can include Ni (nickel), Ti (titanium), Al (aluminum), Cu (copper), Ag (silver), etc. These metals, by forming a contact with the SiC material of the split source region structure 20, can reduce contact resistance and improve current transmission efficiency.

[0072] Specifically, by depositing a metallic material, an ohmic contact can also be formed between the formed second metal layer 102 and the SiC substrate through appropriate metal deposition and processing, ensuring efficient current flow from the device drain. Similarly, the choice of metal here also takes into account good contact performance with the SiC material and ensuring low contact resistance at high current densities.

[0073] In some alternative implementations, such as Figure 1As shown, the fourth injection region 30 is located between the first source region 201 and the second source region 202. This symmetrical arrangement helps to balance the electric field on both sides of the device, reducing the impact of electric field distortion on device performance. The symmetrical fourth injection region 30 ensures that the current is evenly distributed on both sides of the device, avoiding localized damage caused by current concentration. The symmetrical design in this embodiment improves the device's withstand voltage and current carrying capacity, while reducing switching losses and enhancing the overall performance of the device. In other embodiments, the electric field distribution can be further optimized by adjusting the width and position of the fourth injection region 30, solving the problem of reduced structural withstand voltage after integrating the SBD.

[0074] In some alternative implementations, such as Figure 1 As shown, the semiconductor device further includes: a third source region 203 located in the epitaxial layer 110, and the third source region 203 and the second source region 202 are respectively in contact with the same gate structure 40; a fifth implantation region 90 located in the third source region 203, and the depth of the fifth implantation region 90 is greater than the depth of the fourth implantation region 30 and the depth of the third implantation region 60.

[0075] Specifically, the aforementioned fifth injection region 90 (e.g., P) + The fifth injection region 90 is used to prevent device latch-up. The principle behind preventing latch-up is primarily based on the control of parasitic transistors (i.e., parasitic NPN or PNP structures) within the semiconductor device. Latch-up is an undesirable parasitic phenomenon that can lead to high current flow through the device and cause damage. In SiC MOSFET devices, this effect is typically caused by the triggering of a positive feedback mechanism in a parasitic NPN or PNP transistor. When the gate voltage is abnormal or an ESD (electrostatic discharge) event occurs, if the parasitic transistors inside the device (e.g., an NPN structure consisting of an N-type epitaxial layer 110, a P-type first injection region 210, and an N-type second injection region 220) are unintentionally activated, a low-resistance path may form, causing a large amount of current to flow uncontrollably through the device, resulting in overheating and potential permanent damage. The fifth injection region 90 (e.g., P...) + The introduction of the doped region provides sufficient holes (P-type carriers) to neutralize the extra electrons generated in the N-type region, thereby breaking the positive feedback mechanism of the parasitic transistor. Furthermore, the introduction of the fifth injection region 90 alters the electric field distribution within the device, ensuring that the electric field strength in certain regions is insufficient to trigger the conduction of the parasitic transistor, thus preventing latch-up. The aforementioned fifth injection region 90 ensures that even at the initial stage of latch-up, the current is guided and controlled through a predetermined path (typically designed with low impedance), preventing sudden and significant current increases and protecting the device from damage.

[0076] According to an embodiment of this application, a method for fabricating a semiconductor device is provided, for fabricating the aforementioned semiconductor device, such as... Figure 2 As shown, the preparation method includes:

[0077] Step S1, providing a substrate, the substrate comprising a substrate and an epitaxial layer stacked along a first direction;

[0078] Step S2: Ion implantation is performed on one side surface of part of the epitaxial layer to form a split source region structure. The split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface. The surface of the epitaxial layer located between the first source region and the second source region in the same split source region is the first surface region.

[0079] Step S3: Form multiple gate structures on the substrate so that the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures;

[0080] Step S4: A Schottky metal layer is formed on the first surface region.

[0081] In the fabrication method provided in the above embodiments, ion implantation is performed on one side surface of a portion of the epitaxial layer to form a split source region structure in the epitaxial layer. The surface of the epitaxial layer located between the first source region and the second source region in the same split source region is designated as the first surface region. Ion implantation is performed on a portion of the first surface region to form a fourth implantation region, and a Schottky metal layer is formed on the first surface region. The introduced Schottky metal layer is in direct contact with the epitaxial layer, thus integrating a Schottky barrier diode in the device. The integrated SBD (Side Diode) structure addresses these issues in traditional MOSFETs. While the body diode provides a current conduction path when the device is reverse biased, its bipolar conduction mechanism can lead to epitaxial layer defect propagation under high heat and high current conditions, impacting device reliability and lifespan. The integrated SBD, a unipolar device, effectively avoids these problems and reduces costs associated with additional parallel diodes, providing a direct reverse conduction path within the MOSFET. Furthermore, the integrated SBD structure optimizes the reverse recovery process, reducing switching losses and improving device efficiency and performance under high-frequency operating conditions. Additionally, the integrated SBD structure, through direct contact with the epitaxial layer, provides a more stable reverse conduction path, avoiding thermal stress and defect propagation that may occur when the body diode is on, thus enhancing the long-term stability and reliability of the entire MOSFET device.

[0082] Exemplary embodiments of the method for fabricating a semiconductor device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0083] First, proceed to step S1: as follows Figure 3 As shown, a substrate is provided, the substrate including a substrate 120 and an epitaxial layer 110 stacked along a first direction.

[0084] In some optional embodiments, this application further includes the step of forming the above-mentioned substrate: providing a substrate 120 made of silicon carbide; and forming an epitaxial layer 110 on the substrate 120 using an epitaxial process. Specifically, the material of the epitaxial layer 110 may include silicon carbide, and the material of the substrate 120 includes, but is not limited to, semiconductor materials such as silicon, silicon carbide, and gallium nitride. This application does not impose specific limitations on these materials.

[0085] In the above optional embodiments, the doping type of the substrate 120 and the epitaxial layer 110 is not specifically limited in this application embodiment. Specifically, the above semiconductor device can be a SiC MOSFET, and the substrate 120 and the epitaxial layer 110 in the silicon carbide device can have the same doping type. For example, the substrate 120 is a highly doped N-type semiconductor. + The substrate 120 is a lightly doped N-type silicon carbide material with a drain electrode, and the epitaxial layer 110 is a lightly doped N-type silicon carbide material. - The material is silicon carbide, and the epitaxial layer 110 includes a drift region in which a source electrode is formed.

[0086] After providing a substrate including substrate 120 and epitaxial layer 110, step S2 is performed: as follows Figure 4 and Figure 5 As shown, a split source region structure 20 is formed by ion implantation on one side surface of a portion of the epitaxial layer 110. The split source region structure 20 includes a first source region 201 and a second source region 202 spaced apart along a direction parallel to the substrate surface.

[0087] Furthermore, step S2 may also include: Figure 6 As shown, a fourth implantation region 30 is formed by ion implantation of a portion of the first surface region. The first surface region is the surface of the epitaxial layer 110 located between the first source region 201 and the second source region 202 in the same split source region structure 20.

[0088] In the above preparation method, a fourth implantation region 30 is formed. The fourth implantation region 30 is located in the epitaxial layer 110 and is in contact with the Schottky metal layer 50. The orthogonal projection of the fourth implantation region 30 on the first surface region can be located at the center of the first surface region. Since the breakdown voltage of the Schottky junction is usually lower than that of the PN junction, the pure Schottky interface will cause the device breakdown voltage to decrease. The fourth implantation region 30 introduced in this application is located below the Schottky metal layer 50. This region is located in the middle part of the entire Schottky barrier and is also the part where the electric field is most concentrated. Thus, a high-voltage resistant region can be formed at the weakest point of the Schottky interface, thereby improving the overall breakdown voltage performance of the device.

[0089] In some alternative embodiments, the steps of forming the above-described split source region structure 20 and the above-described fourth injection region 30 include: as follows Figure 4 and Figure 5 As shown, ion implantation is performed on one side surface of a portion of the epitaxial layer 110 to form a first implantation region 210, and ion implantation is performed on one side surface of a portion of the first implantation region 210 to form a second implantation region 220; as Figure 6 As shown, ion implantation is performed on one side surface of a portion of the second implantation region 220 in the first source region 201 and a portion of the first surface region to form a third implantation region 60 and a fourth implantation region 30. The portion of the first implantation region 210 and the second implantation region 220 located between the third implantation region 60 and the first implantation region 210 is in contact with the gate structure 40.

[0090] Specifically, the above-mentioned first doping type is N-type doping and the second doping type is P-type doping, as examples. The above-mentioned ion implantation step constructs a complex doped region structure, forming an NPNP structure, which is used to improve the electrostatic discharge (ESD) protection level of the gate 420. By precisely controlling the implantation energy and dosage, doped regions of the required depth and concentration can be formed in the epitaxial layer 110. The combination of these doped regions forms an NPNP structure. When the gate 420 voltage is too high, the NPNP structure can be activated to release excess ESD energy and protect the gate 420 oxide layer. The technology in the embodiments of this application significantly enhances the ESD protection capability of the gate 420 and reduces switching power consumption, especially in high-frequency and high-resistance applications.

[0091] In the above optional embodiments, the fourth injection region 30 and the third injection region 60 are formed by the same injection process. The synchronous injection process reduces the steps of forming these two injection regions separately, thereby reducing production costs. Furthermore, by forming multiple injection regions in a single process step, the process flow is simplified, and the production yield and consistency are improved.

[0092] After the steps of forming the above-mentioned split source region structure 20 and the above-mentioned fourth injection region 30, step S3 is performed: as follows Figures 7 to 10As shown, a gate structure 40 is formed on the substrate, the gate structure 40 is located on the substrate surface and is in contact with the split source region structure 20.

[0093] After the steps of forming the above-mentioned splitting source region structure 20 and the above-mentioned fourth injection region 30, the preparation method in the embodiments of this application may include: as follows Figure 7 As shown, a gate dielectric layer 410 in contact with the split source region structure 20 is formed on the substrate surface, and then as follows... Figure 8 As shown, a gate 420 is formed on the gate dielectric layer 410; then as... Figure 9 and Figure 10 As shown, an insulating material layer 801 is covered on one side of the substrate with an epitaxial layer 110, and the insulating material layer 801 is etched to form an insulating dielectric layer 80 with a source contact hole, wherein a source contact hole is formed that extends to the source structure, a portion of the first metal layer 101 is filled in the source contact hole, the first source contact hole extends to the surface of the split source region structure 20 (i.e., the first source region 201) located between the gate structure 40 and the doped semiconductor layer 70, and the second source contact hole extends to the surface of the split source region structure 20 (i.e., the second source region 202) located between the gate structure 40 and the insulating dielectric layer 80.

[0094] For example, the gate 420 formed in step S3 above is an N-type polysilicon material, and the gate dielectric layer 410 and the insulating material layer 801 are made of SiO2, but are not limited to the above types. This application does not make any specific limitations.

[0095] After forming the gate structure 40 described above, step S4 is performed: as follows Figure 11 As shown, a Schottky metal layer 50 is formed on a first surface region, which is the surface of the epitaxial layer 110 located between the first source region 201 and the second source region 202 in the same split source region structure 20.

[0096] Specifically, the steps for forming the Schottky metal layer 50 include: depositing a metal material on a substrate to cover a first surface region of the gate dielectric layer 410 and the epitaxial layer 110, then covering a mask layer and patterning the mask layer to expose the metal material on the surface of the gate dielectric layer 410, then etching the exposed metal material, and the remaining metal material located on the first surface region to form the Schottky metal layer 50.

[0097] For example, the material of the Schottky metal layer 50 is selected from one or more of nickel (Ni), molybdenum (Mo), palladium (Pd), platinum (Pt), titanium (Ti) and tungsten (W), but is not limited to the above types, and this application does not make any specific limitation.

[0098] After the step of forming the Schottky metal layer 50 described above, as Figure 1As shown, a metal material is deposited on one side of the substrate with an insulating dielectric layer 80. The first metal layer 101 formed in the source contact hole forms a good ohmic contact with the split source region structure 20 (specifically the second injection region 220 therein), ensuring that the current can flow into the source of the device efficiently from the external circuit. Furthermore, a metal material is deposited on one side of the substrate with a substrate 120 to form a second metal layer 102. The second metal layer 102 and the SiC substrate can also form an ohmic contact through appropriate metal deposition and processing, ensuring that the current flows out efficiently from the drain of the device.

[0099] For example, the materials of the first metal layer 101 and the second metal layer 102 are selected from one or more of nickel (Ni), molybdenum (Mo), titanium (Ti), aluminum (Al) and copper (Cu), but are not limited to the above types, and this application does not make any specific limitation.

[0100] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0101] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A semiconductor device, characterized in that, include: The substrate includes a stacked substrate and an epitaxial layer, the epitaxial layer having a first doping type; A split source region structure is located in the epitaxial layer. The split source region structure is a region formed by ion implantation on one side surface of a portion of the epitaxial layer, and the split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface. Multiple gate structures are located on the substrate surface, and the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures; A Schottky metal layer is located on a first surface region, which is the surface of the epitaxial layer situated between the first source region and the second source region in the same split source region structure. Both the first source region and the second source region include a first implantation region and a second implantation region. The first implantation region is a region formed by ion implantation of a portion of one surface of the epitaxial layer, and the second implantation region is a region formed by ion implantation of a portion of one surface of the first implantation region. The semiconductor device further includes: A doped semiconductor layer is located on the surface of the epitaxial layer between at least one of the gate structures and the Schottky metal layer, and the first source region is in contact with the doped semiconductor layer and the gate structure, respectively; The third implantation region is located between the doped semiconductor layer and a portion of the second implantation region. The third implantation region is a region formed by ion implantation of one side surface of a portion of the second implantation region in the first source region. Wherein, the portion of the first injection region and the second injection region located between the third injection region and the first injection region is in contact with the gate structure, the doped semiconductor layer and the second injection region have the first doping type, and the first injection region and the third injection region have the second doping type.

2. The semiconductor device according to claim 1, characterized in that, The portion of the first injection region located between the second injection region and the epitaxial layer has a first thickness, the portion of the second injection region located between the first injection region and the third injection region has a second thickness, and the third injection region has a third thickness, wherein both the second thickness and the third thickness are less than the first thickness.

3. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: The fourth implantation region is located in the epitaxial layer and is in contact with the Schottky metal layer. The fourth implantation region is a region formed by ion implantation of a portion of the first surface region, and the fourth implantation region has a second doping type.

4. The semiconductor device according to claim 3, characterized in that, The fourth injection region has the same doping concentration and depth as the third injection region.

5. The semiconductor device according to claim 3, characterized in that, Also includes: An insulating dielectric layer is located on one side of the substrate having the epitaxial layer, a first portion of the insulating dielectric layer covers the gate structure, a second portion of the insulating dielectric layer covers the doped semiconductor layer, and a first source contact hole is provided between the first portion and the second portion.

6. The semiconductor device according to claim 5, characterized in that, The second source region is in contact with the third portion in the insulating dielectric layer and the gate structure, respectively, and a second source contact hole is provided between the first portion and the third portion.

7. The semiconductor device according to claim 5, characterized in that, Also includes: The third source region is located in the epitaxial layer, and the third source region and the second source region are respectively in contact with the same gate structure; The fifth injection region is located within the third source region, and the depth of the fifth injection region is greater than the depth of the fourth injection region and the depth of the third injection region.

8. A method for fabricating a semiconductor device, characterized in that, The method for preparing the semiconductor device according to any one of claims 1 to 7 comprises: A substrate is provided, the substrate comprising a substrate and an epitaxial layer stacked along a first direction; Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a split source region structure. The split source region structure includes a first source region and a second source region spaced apart along a direction parallel to the substrate surface. The surface of the epitaxial layer located between the first source region and the second source region in the same split source region is a first surface region. Multiple gate structures are formed on the substrate such that the first source region and the second source region in the same split source region are respectively in contact with different and adjacent gate structures; A Schottky metal layer is formed on the first surface region.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The steps for forming the splitting source region structure include: Ion implantation is performed on one side surface of a portion of the epitaxial layer to form a first implantation region, and ion implantation is performed on one side surface of a portion of the first implantation region to form a second implantation region; The preparation method further includes the following steps: Ion implantation is performed simultaneously on one side surface of a portion of the second implantation region in the first source region and on a portion of the first surface region to form a third implantation region and a fourth implantation region. The portion of the first implantation region and the second implantation region located between the third implantation region and the first implantation region is in contact with the gate structure.

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