Test backboard and manufacturing method thereof

Abstract

The invention relates to a test backboard and a manufacturing method thereof. The test backboard comprises a substrate; the plurality of pad group units are arranged on the substrate, each pad group unit comprises a first pad unit and a second pad, one first pad unit comprises at least two first pads, and the distances between the first pads in one first pad unit and the corresponding second pads are different; and the bonding pad group unit is configured to be matched with the light-emitting chips with at least two sizes. The first bonding pad is used for bonding with a first electrode of the light-emitting chip, and the second bonding pad is used for bonding with a second electrode of the light-emitting chip. The distances between the first bonding pads in one first bonding pad unit and the corresponding second bonding pads are different, so that the bonding pad group unit can be bonded with the light-emitting chips of at least two sizes, the light-emitting chips of at least two sizes can be tested on one test backboard during testing, the application range of the test backboard is expanded, the test cost is reduced, and the test efficiency is improved. And the resource optimization is realized.

Description

Technical Field

[0001] The present application relates to the field of LED displays, and in particular to a test backplane and a manufacturing method thereof. Background Art

[0002] Micro-LED (Micro Light Emitting Diode) is a device that reduces the pixel size of traditional LEDs from millimeter level to micron level. Its pixel size usually does not exceed 100μm. It has the advantages of higher resolution, lower power consumption, longer life, fast response and high reliability. It has broad application prospects in many fields such as high-resolution display, wearable optoelectronic devices, optical communications, biomedical testing, etc. During the production process of LED chips, the photoelectric performance of LED chips needs to be tested. However, the current photoelectric performance test of LED chips usually uses a test device of one model that can only test LED chips of one size. Therefore, each time a size of LED chip is tested, a new test device needs to be made, which increases the production cost.

[0003] Therefore, how to reduce the performance testing cost of LED chips is an urgent problem to be solved. Summary of the Invention

[0004] In view of the deficiencies of the above-mentioned related technologies, the purpose of this application is to provide a test backplane and a manufacturing method thereof, aiming to solve the problem of high cost of performance testing of LED chips.

[0005] A test backplane, comprising:

[0006] substrate;

[0007] A plurality of pad group units are provided on the substrate, the pad group units including a first pad unit and a second pad, one of the first pad units including at least two first pads, and the spacing between each first pad and the corresponding second pad in one of the first pad units is different, and the pad group unit is configured to match at least two sizes of light-emitting chips.

[0008] In the aforementioned test backplane, the first pad is used to bond to the first electrode of the light-emitting chip, and the second pad is used to bond to the second electrode of the light-emitting chip. The spacing between each first pad and the corresponding second pad in a first pad unit is different, allowing the pad group unit to bond to light-emitting chips of at least two sizes. During testing, at least two sizes of light-emitting chips can be tested on a single test backplane, expanding the applicability of the test backplane, reducing testing costs, and achieving greater resource optimization.

[0009] Based on the same inventive concept, the present application also provides a method for manufacturing the test backplane as described above, comprising:

[0010] A plurality of pad group units are arranged on the substrate, the pad group units include the first pad units and the second pads, one first pad unit includes at least two first pads, and the spacing between each first pad and the corresponding second pad in one first pad unit is different.

[0011] In the manufacturing method of the above-mentioned test backplane, the spacing between each first soldering pad in a first soldering pad unit and the corresponding second soldering pad is different, so that the soldering pad group unit can be bonded with at least two sizes of light-emitting chips. During testing, at least two sizes of light-emitting chips can be tested on one test backplane, which expands the application scope of the test backplane, reduces the testing cost, and achieves better optimization of resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 A schematic structural diagram of a test backplane provided in an embodiment of the present application;

[0013] Figure 2 A schematic diagram of a structure in which first solder pads are isolated from each other provided in an embodiment of the present application;

[0014] Figure 3 A schematic structural diagram of a first pad unit provided in an embodiment of the present application including two first pads;

[0015] Figure 4 A schematic diagram of a structure in which a first pad is provided on both sides of a second pad according to an embodiment of the present application;

[0016] Figure 5 A schematic diagram of a structure in which a first pad is arranged on the same side as a second pad provided in an embodiment of the present application;

[0017] Figure 6 A schematic structural diagram of a second pad corresponding to three first pad units provided in an embodiment of the present application;

[0018] Figure 7 A schematic structural diagram of a second pad corresponding to a first pad unit provided in an embodiment of the present application;

[0019] Figure 8 A schematic structural diagram of a second soldering pad corresponding to a first soldering pad provided in an embodiment of the present application;

[0020] Figure 9 A schematic structural diagram of a backplane provided in an embodiment of the present application including an insulating layer;

[0021] Figure 10 A schematic diagram of the structure of simultaneously bonding three sizes of light-emitting chips to the test backplane provided in an embodiment of the present application;

[0022] Figure 11 This is a schematic diagram of the structure of a test backplane provided in an embodiment of the present application with only one size of light-emitting chip bonded thereto;

[0023] Figure 12 A flow chart of a method for manufacturing a test backplane provided in another optional embodiment of the present application;

[0024] Description of reference numerals:

[0025] 1-substrate; 2-first solder pad; 3-second solder pad; 4-pad group unit; 5-first solder pad unit; 6-light-emitting chip; 7-first insulating layer; 8-window; 9-second insulating layer. DETAILED DESCRIPTION

[0026] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0028] During the manufacturing process of LED chips, the photoelectric performance of the LED chips needs to be tested. However, the photoelectric performance test of LED chips usually requires a test device of one model to test only one size of LED chips. Therefore, each time a size of LED chip is tested, a new test device needs to be made, thereby increasing the production cost.

[0029] Based on this, the present application hopes to provide a solution that can solve the above technical problems, the details of which will be explained in the subsequent embodiments.

[0030] This embodiment provides a test backplane, which is used for testing the photoelectric performance of light-emitting chips. Figures 1-11 As shown, the test backplane includes a substrate 1 and a plurality of pad group units 4 arranged on the substrate 1 .

[0031] In this embodiment, the pad group unit 4 includes a first pad unit 5 and a second pad 3, a first pad unit 5 includes at least two first pads 2, and the spacing between each first pad 2 and the corresponding second pad 3 in a first pad unit 5 is different, and the pad group unit 4 is configured to match at least two sizes of light-emitting chips 6.

[0032] It can be understood that a first pad unit 5 includes at least two first pads 2, such as Figure 3 As shown, a first pad unit 5 may include two first pads 2; or Figure 2 As shown, a first pad unit 5 includes three first pads 2; a first pad unit 5 may also include four first pads 2, or more. Moreover, in a pad group unit 4, as shown in FIG. Figures 1-3 As shown, each first pad 2 may be located on the same side of the second pad 3, or may be as shown in FIG. Figure 4 As shown, the first pads 2 are arranged on both sides of the second pad 3 as needed. For example, when the first pad unit 5 includes two first pads 2, the two first pads 2 are located on the same side of the second pad 3, or one is located on one side of the second pad 3 and the other is located on the other side of the second pad 3. This embodiment does not impose any specific restrictions on this. In this embodiment, the spacing between each first pad 2 and the corresponding second pad 3 in a first pad unit 5 is different. Specifically, the spacing between the side a of the first pad 2 close to the second pad 3 and the side b of the corresponding second pad 3 close to the first pad 2 can be different. In this embodiment, the spacing between the first pad 2 and the second pad 3 in a first pad unit 5 has at least two sizes, and the size can match the size of the light-emitting chip 6 to be tested, so that the pad group unit 4 can be bonded with light-emitting chips 6 of at least two sizes. During testing, a light-emitting chip 6 of one size can be bonded to the first pad 2 and the second pad 3 of the corresponding spacing size. Thus, at least two sizes of light emitting chips 6 can be tested on one test backplane, which expands the application range of the test backplane, reduces testing costs, and achieves better resource optimization. In this embodiment, the size of the light emitting chip 6 can be the distance between the first electrode and the second electrode of the light emitting chip 6.

[0033] This embodiment does not impose any specific restrictions on the material of the substrate 1. It can be made of a transparent material, such as glass, ceramic, or sapphire, or an opaque material, such as a PCB. This embodiment also does not impose any specific restrictions on the material of the first and second solder pads 2 and 3. They can be well bonded to the electrodes of the light-emitting chip 6. For example, in one example, the material of the first and second solder pads 2 and 3 can include, but is not limited to, at least one of Cr, Ni, Al, Ti, Au, Pt, W, Pb, Rh, Sn, Cu, and Ag. This embodiment does not impose any specific restrictions on the polarity y of the first and second solder pads 2 and 3. For example, the first solder pad 2 can be positive and the second solder pad 3 can be negative, or the first solder pad 2 can be negative and the second solder pad 3 can be positive. The light-emitting chip 6 tested on the test backplane in this embodiment can be, but is not limited to, any of Mini LED (sub-millimeter light-emitting diode) and Micro LED (micron-scale light-emitting diode).

[0034] In some embodiments, adjacent first pads 2 in each first pad unit 5 are electrically connected. When electrically connected, the light-emitting chips 6 bonded to one first pad unit 5 can be simultaneously lit for testing, making testing more convenient. This embodiment does not limit the specific method of electrically connecting adjacent first pads 2. For example, they can be electrically connected to each other through metal wires, or as shown in FIG. Figure 1 、 Figure 3 、 Figure 7 As shown, the first pads 2 in a first pad unit 5 can also be directly made into an integrated structure.

[0035] In other embodiments, adjacent first pads 2 in each first pad unit 5 are isolated from each other. When isolated from each other, the light-emitting chips 6 bonded to a first pad unit 5 can be individually lit for testing, which can make the test control more accurate. In this embodiment, the specific method of isolating adjacent first pads 2 from each other is not limited, for example, Figure 2 、 Figure 5 、 Figure 6 As shown, adjacent first pads 2 may be independently provided to form isolation, or an insulator may be provided between adjacent first pads 2 to form isolation.

[0036] In this embodiment, if Figures 1-3As shown, the side a of the first pad 2 in each first pad unit 5 close to the second pad 3 is combined to form a step surface. It can be understood that the step surface in this embodiment is a step-shaped surface, which is similar to the shape of a ladder, thereby forming a first pad unit 5 with different spacings between each first pad 2 and the corresponding second pad 3. At this time, the first pads 2 in each first pad unit 5 are all located on the same side of the second pad 3. However, it is not limited to this, and different spacings between the first pad 2 and the second pad 3 can also be formed by other settings. In this embodiment, the side of the first pad 2 in each first pad unit 5 away from the second pad 3 is all located in the same plane, which makes it easier to make the first pad 2. At this time, the smaller the spacing between the first pad 2 and the second pad 3, the larger the bonding area of ​​the corresponding first pad 2; in some application scenarios, such as Figure 6 As shown, the surface c of the first pad 2 away from the second pad 3 in each first pad unit 5 can also be combined to form a stepped surface. In this case, the bonding area of ​​each first pad 2 can be made the same, saving materials.

[0037] In a first pad unit 5 of this embodiment, as Figures 1-3 As shown, the spacing between each first pad 2 and the second pad 3 may be gradually increased or decreased in a step-by-step manner along the setting direction of the second pad 3. However, this is not limited to the above, and the specific arrangement may be as required, for example, Figure 5 As shown, when a first pad unit 5 includes three first pads 2 and all are located on the same side of the second pad 3, the distance between the middle first pad 2 and the corresponding second pad 3 may be the largest.

[0038] In some embodiments, the pad group unit 4 may include a first pad unit 5 and a second pad 3, and a surface of the second pad 3 close to the first pad unit 5 is a plane. Figure 7 As shown, when the first pad unit 5 includes three first pads 2, one second pad 3 corresponds to the three first pads 2, and the spacing between the three first pads 2 and the second pad 3 is different. The surface b of the second pad 3 closest to the first pad unit 5 is flat, which makes it easier to control the size of the spacing between the first pad 2 and the second pad 3. During manufacturing, the flat surface of the second pad 3 can be used as a reference.

[0039] In some embodiments, the pad group unit 4 may also include a first pad unit 5 and at least two second pads 3, and the sides of each second pad 3 close to the first pad unit 5 are located in the same plane. Figure 8As shown, when the first pad unit 5 includes three first pads 2, a pad group unit 4 can include three second pads 3. The first pads 2 correspond to the second pads 3 in a one-to-one manner, and the spacing between the three first pads 2 and the corresponding second pads 3 is different. In this case, the light-emitting chip 6 can also be illuminated. The side b of each second pad 3 adjacent to the first pad unit 5 is located in the same plane, which also facilitates the size control of the spacing between the first pad 2 and the second pad 3.

[0040] In some embodiments, Figures 1-3 As shown, the pad group unit 4 may include one second pad 3 and at least two first pad units 5, and a surface b of the second pad 3 adjacent to the first pad unit 5 is a flat surface. For example, when a pad group unit 4 includes three first pad units 5, one second pad 3 corresponds to three first pad units 5, i.e., the three first pad units 5 share the same second pad 3. In this case, the light-emitting chip 6 can still be illuminated, and the arrangement of the pads on the substrate 1 is also simpler.

[0041] In this embodiment, if Figure 9 As shown, the test backplane may include a first pad layer and a second pad layer, the first pad layer is composed of a first pad 2, the second pad layer is composed of a second pad 3, a first insulating layer 7 is arranged between the first pad layer and the second pad layer, and the first insulating layer 7 is provided with a window 8 for bonding the light-emitting chip 6. In this way, a double-layer metal backplane can be formed, and the production of the pads is simpler. This embodiment does not impose any specific restrictions on the material of the insulating layer, which can form insulation between the first pad 2 and the second pad 3. In addition, a second insulating layer 9 can be provided on the second pad 3 layer to prevent accidental contact of the second pad 3 layer. At this time, windows 8 need to be provided on the two insulating layers to expose the first pad 2 and the second pad 3 for bonding the light-emitting chip 6. In this embodiment, the first pad 2 and the second pad 3 can be at the same height or not, and can be set according to needs. When they are not at the same height, as shown in FIG. Figure 9 As shown, when the heights are the same, the thickness of the first pad layer is greater than that of the second pad layer. A first insulating layer 7 is still provided between the first pad layer and the second pad layer, and the portion where the first insulating layer 7 covers the first pad 2 is a convex structure.

[0042] In the above-mentioned test backplane, the first pad 2 is used to bond with the first electrode of the light-emitting chip 6, and the second pad 3 is used to bond with the second electrode of the light-emitting chip 6. The spacing between each first pad 2 and the corresponding second pad 3 in a first pad unit 5 is different, so that the pad group unit 4 can be bonded with light-emitting chips 6 of at least two sizes. In some application scenarios, such as Figure 10 As shown, two or more light-emitting chips 6 can be bonded simultaneously on a test backplane. At this time, at least two sizes of light-emitting chips 6 can be tested simultaneously on a test backplane. In other application scenarios, such as Figure 11As shown, only one size of light emitting chip 6 can be bonded on a test backboard, and then another size of light emitting chip 6 can be bonded on the test backboard for testing. The test backboard has a wider range of applications, reduces testing cost, and optimizes resources.

[0043] Another optional embodiment of the present application is as follows:

[0044] The embodiment provides a manufacturing method of the test backboard, comprising the following steps:

[0045] A plurality of pad group units 4 are arranged on the substrate 1, and each pad group unit 4 comprises a first pad unit 5 and a second pad 3. Each first pad unit 5 comprises at least two first pads 2, and the spacing between each first pad 2 in a first pad unit 5 and the corresponding second pad 3 is different.

[0046] It can be understood that the specific arrangement of the pad group units 4 on the substrate 1 in the embodiment is the same as that in the previous embodiment, and will not be repeated here.

[0047] In some embodiments, as shown, the step of arranging a plurality of pad group units 4 on the substrate 1 comprises the following steps: Figure 12

[0048] S1: arranging a first pad layer on the substrate.

[0049] The first pad layer in the embodiment comprises a plurality of first pads 2, and the specific manufacturing of the first pad layer can be completed by using but not limited to the following steps: first, a metal film layer is plated on the substrate 1; then, a photoresist layer is coated on the metal film layer; then, the photoresist is exposed and developed to expose the unnecessary part of the metal film layer; the unnecessary part of the metal film layer exposed is etched; and finally, the photoresist is removed to form the first pad layer comprising a plurality of first pads 2.

[0050] S2: arranging an insulating layer on the first pad layer.

[0051] The insulating layer in the embodiment can be formed by using but not limited to an evaporation method.

[0052] S3: arranging a second pad layer on the insulating layer.

[0053] The second pad layer in the embodiment comprises a plurality of second pads 3, and the specific manufacturing of the second pad layer can also be completed by using but not limited to the following steps: first, a metal film layer is plated on the insulating layer; then, a photoresist layer is coated on the metal film layer; then, the photoresist is exposed and developed to expose the unnecessary part of the metal film layer; the unnecessary part of the metal film layer exposed is etched; and finally, the photoresist is removed to form the second pad layer comprising a plurality of second pads 3.

[0054] ​S4: a plurality of windows for exposing the first pads are provided on the insulating layer.

[0055] This embodiment can form a double-layer metal back plate through the above manufacturing steps, and the manufacturing of the pad is simpler. In addition, in order to prevent the second pad layer from being accidentally contacted, such as Figure 9 As shown, another insulating layer may be provided on the second pad layer. When opening a window, a window 8 needs to be provided on the two insulating layers to expose the first pad 2 and the second pad 3 for bonding the light emitting chip 6 .

[0056] In the manufacturing method of the above-mentioned test backplane, the spacing between each first soldering pad 2 and the corresponding second soldering pad 3 in a first soldering pad unit 5 is different, so that the soldering pad group unit 4 can be bonded with at least two sizes of light-emitting chips 6. During testing, at least two sizes of light-emitting chips 6 can be tested on one test backplane, which expands the application range of the test backplane, reduces the testing cost, and achieves better optimization of resources.

[0057] It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to this application.

Claims

1. A test backplane, characterized in that: include: substrate; A plurality of pad group units are provided on the substrate, the pad group units including a first pad unit and a second pad, one of the first pad units including at least two first pads, and the spacing between each first pad and the corresponding second pad in one of the first pad units is different, and the pad group unit is configured to match at least two sizes of light-emitting chips.

2. The test backplane according to claim 1, wherein: Adjacent first pads in each first pad unit are electrically connected.

3. The test backplane according to claim 1, wherein: Adjacent first pads in each first pad unit are isolated from each other.

4. The test backplane according to any one of claims 1 to 3, wherein: A surface of the first pad in each of the first pad units that is close to the second pad is combined to form a stepped surface.

5. The test backplane according to claim 4, wherein: In each of the first pad units, a surface of the first pad away from the second pad is located in the same plane.

6. The test backplane according to any one of claims 1 to 3, wherein: The pad group unit includes a first pad unit and a second pad, and a surface of the second pad close to the first pad unit is a plane; Alternatively, the pad group unit includes one first pad unit and at least two second pads, and a surface of each of the second pads close to the first pad unit is located in the same plane.

7. The test backplane according to any one of claims 1 to 3, characterized in that: The pad group unit includes one second pad and at least two first pad units, and a surface of the second pad close to the first pad unit is a plane.

8. The test backplane according to any one of claims 1 to 3, wherein: The test backplane includes a first pad layer and a second pad layer, wherein the first pad layer is composed of the first pads, and the second pad layer is composed of the second pads. An insulating layer is provided between the first pad layer and the second pad layer, and the insulating layer is provided with a window for bonding the light-emitting chip.

9. A method for manufacturing a test backplane according to any one of claims 1 to 8, characterized in that: include: A plurality of pad group units are arranged on the substrate, the pad group units include the first pad units and the second pads, one first pad unit includes at least two first pads, and the spacing between each first pad and the corresponding second pad in one first pad unit is different.

10. The method for manufacturing a test backplane according to claim 9, wherein: The providing a plurality of pad group units on the substrate comprises: Disposing a first pad layer on the substrate, wherein the first pad layer includes a plurality of first pads; providing an insulating layer on the first pad layer; Disposing a second pad layer on the insulating layer, wherein the second pad layer includes a plurality of second pads; A plurality of windows for exposing the first pads are provided on the insulating layer.

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