Test pattern selection method and device and model generation method and device

Abstract

The embodiment of the invention provides a test pattern selection method and device and a model generation method and device. The test pattern selection method comprises the steps of obtaining a test layout; the test layout comprises at least one candidate test pattern; each candidate test pattern is obtained after screening based on a label and a preset detection frame; the label is used for marking a pattern expected to test the chip, and the preset detection frame is used for providing a detection space so as to screen the pattern with the label; extracting features of each candidate test pattern, and determining categories of the candidate test patterns based on the features of the candidate test patterns; the features are used for describing attributes of the candidate test patterns; and selecting a target test pattern from each type of determined candidate test patterns according to modeling data requirements of the optical proximity correction model. According to the test pattern selection method provided by the embodiment of the invention, the number of the target test patterns can be reduced while the coverage rate is ensured, and the precision of the optical proximity correction model is ensured.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor integrated circuit manufacturing and testing, and in particular to a test pattern selection method, a model generation method and device. BACKGROUND

[0002] In an optical proximity correction model, a large number of test patterns of different features are needed to build the optical proximity correction model to ensure sufficient model coverage; different sizes of key dimensions and other modeling data need to be covered in each test pattern of a feature to ensure the accuracy of the built optical proximity correction model, which requires the selected test patterns to have sufficient coverage of the actual design patterns.

[0003] Currently, the method for selecting test patterns in the industry is based on experience, which often makes it difficult to ensure that the modeling data in the test patterns has sufficient coverage, thereby leading to the need for additional modeling data in the later stage, which prolongs the modeling cycle; there may also be a large number of similar test patterns selected, resulting in redundant metrology data; it is difficult to maintain the minimum number of test patterns while ensuring the coverage of the test patterns; at the same time, the selection of test patterns based on experience may result in the selection of non-existent test patterns, which in turn leads to the mispositioning of the measurement points of the test patterns and increases the invalid measurement. SUMMARY

[0004] Therefore, embodiments of the present application provide a test pattern selection method, a model generation method and device to ensure sufficient model coverage and model accuracy.

[0005] To solve the above problems, embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a test pattern selection method, comprising:

[0007] obtaining a test layout; the test layout comprising: at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark patterns expected to be tested on a chip, and the preset detection frame is used to provide a detection space to screen patterns with labels;

[0008] extracting features of each candidate test pattern, and determining the category of the candidate test pattern based on the features of the candidate test pattern; the features are used to describe the attributes of the candidate test pattern;

[0009] In each category of the determined candidate test patterns, a corresponding target test pattern is selected according to the modeling data requirements of the optical proximity correction model.

[0010] In a second aspect, an embodiment of the present application provides an optical proximity correction model generation method, comprising:

[0011] obtaining a target test pattern; the target test pattern is determined based on the test pattern selection method in the first aspect;

[0012] establishing an optical proximity correction model based on the target test pattern.

[0013] In a third aspect, an embodiment of the present application provides a test pattern selection device, comprising:

[0014] a layout obtaining module, configured to obtain a test layout; the test layout comprises at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark patterns expected to be tested on a chip, and the preset detection frame is used to provide a detection space to screen patterns with the label;

[0015] a feature extraction and classification determination module, configured to extract features of each candidate test pattern, and determine a category of the candidate test pattern based on the features of the candidate test pattern; the features are used to describe attributes of the candidate test pattern;

[0016] a screening module, configured to select a corresponding target test pattern from each category of candidate test patterns determined according to modeling data requirements of an optical proximity correction model.

[0017] In a fourth aspect, an embodiment of the present application provides an optical proximity correction model generation device, comprising:

[0018] a target test pattern obtaining module, configured to obtain a target test pattern; the target test pattern is determined based on the test pattern selection device in the third aspect;

[0019] a model establishing module, configured to establish an optical proximity correction model based on the target test pattern.

[0020] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a memory and a processor; the memory stores a program; the processor invokes the program stored in the memory to execute the test pattern selection method or the optical proximity correction model generation method.

[0021] In a sixth aspect, an embodiment of the present application provides a storage medium, which stores a program; the program is executed to implement the test pattern selection method or the optical proximity correction model generation method.

[0022] In a seventh aspect, an embodiment of the present application provides a computer program product, comprising a computer program, which, when executed, implements the test pattern selection method or the optical proximity correction model generation method.

[0023] The test pattern selection method provided by an embodiment of the present application comprises: obtaining a test layout; the test layout comprises at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark patterns expected to be tested on a chip, and the preset detection frame is used to provide a detection space to screen patterns with the label; features of each candidate test pattern are extracted, and the category of the candidate test pattern is determined based on the features of the candidate test pattern; the features are used to describe the attributes of the candidate test pattern; and a corresponding target test pattern is selected from each category of candidate test patterns according to modeling data requirements of an optical proximity correction model.

[0024] The test pattern selection method provided by an embodiment of the present application can first classify test patterns based on features of the test patterns from the test layout, then select target test patterns based on test patterns of each category, ensure that there are no a large number of similar features in the classified candidate test patterns, and further ensure the coverage rate of the optical proximity correction model target test patterns for test patterns of different categories, so that the modeling cycle of the optical proximity correction model can be shortened without supplementing modeling data in the later period; the selection is further performed in the candidate test patterns of each category, so that the modeling requirements of the optical proximity correction model can be met under the condition that different categories of test patterns provide sufficient coverage, and the optical proximity correction model established in this way can further improve the accuracy; meanwhile, the classified candidate test patterns are pre-screened, the appearance of a large number of similar or unusable patterns is reduced, so that the number of target test patterns can be reduced while covering different types of features and meeting the modeling requirements of the optical proximity correction model, and the modeling speed of the optical proximity correction model is further accelerated. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0026] Figure 1 A flowchart of the test pattern selection method provided by an embodiment of the present application;

[0027] Figure 2aA test pattern 1 of a test layout provided for an embodiment of the present application;

[0028] Figure 2b A test pattern 2 of a test layout provided for another embodiment of the present application;

[0029] Figure 3 A flow chart of a method for generating an OPC model provided for another embodiment of the present application;

[0030] Figure 4 A structural schematic diagram of a selection device for a test pattern provided for an embodiment of the present application;

[0031] Figure 5 A structural schematic diagram of a device for generating an OPC model provided for another embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without any creative work fall within the protection scope of the present application.

[0033] An Optical Proximity Correction (OPC) model is a key technology for compensating optical proximity effects in a photolithography process in semiconductor manufacturing.

[0034] Before introducing the selection method of the test pattern provided for the embodiments of the present application, the principle and application of the OPC model are introduced first.

[0035] Principle of the OPC model

[0036] Optical proximity effects are the distortion of patterns in a photolithography process due to factors such as optical diffraction, interference and photoresist chemical reaction. The OPC model adjusts the mask pattern to compensate for these distortions so that the pattern formed on the silicon wafer finally is consistent with the design pattern. The OPC model is mainly divided into two categories:

[0037] 1. Rule-Based OPC (RB-OPC):

[0038] Depending on a pre-defined rule set, a series of rules are manually created to correct proximity effects according to the experience and rules of the photolithography process.

[0039] Suitable for specific processes and simple cases, but difficult to cover complex cases, and need to manually adjust the rules when the process changes.

[0040] 2. Model-Based OPC (MB-OPC):

[0041] Use physical models or simulation tools to simulate optical effects in the lithography process, such as beam propagation, diffraction, etc.

[0042] More flexible, can predict effects in complex cases, and automatically make corrections.

[0043] MB-OPC is further divided into Edge-Based OPC (EB-OPC) and Pixel-Based OPC (PB-OPC).

[0044] Application of OPC model

[0045] 1. Improve lithography accuracy:

[0046] OPC model compensates for optical proximity effects to ensure that the pattern formed on the wafer is highly consistent with the design pattern, thereby improving lithography accuracy.

[0047] 2. Optimize mask design:

[0048] OPC model adjusts mask patterns, such as adding sub-resolution assist features (SRAF) or changing pattern edge shape, to improve imaging quality.

[0049] 3. Improve manufacturing yield:

[0050] By reducing pattern distortion and defects, OPC model helps improve the yield and reliability of semiconductor manufacturing.

[0051] Test patterns of optical proximity correction (OPC) model are applied to test chips as follows:

[0052] 1. Used for model calibration and verification

[0053] Optical proximity correction model needs to be calibrated and verified for its accuracy through actual test patterns. Test patterns usually contain various feature sizes and layouts, and these patterns can be measured after exposure on actual wafers to evaluate the correction effect of the model. In this way, it can be ensured that the OPC model can accurately compensate for the optical proximity effect (OPE) in the actual lithography process, thereby improving the lithography accuracy.

[0054] 2. Optimize lithography process

[0055] Test patterns are used to simulate complex situations in actual chip manufacturing, helping to optimize lithography process parameters. For example, through test patterns, pattern fidelity under different exposure conditions can be evaluated, thus optimizing parameters such as light source shape, mask configuration, etc. This is crucial for improving the yield and performance of chip manufacturing.

[0056] 3. Improve model accuracy

[0057] The design of test patterns is very critical, as they directly affect the accuracy of the model. By actually exposing and measuring test patterns under the same process conditions, a large amount of data can be collected for the fitting and optimization of the model. This enables the OPC model to more accurately predict and compensate for various errors in the lithography process.

[0058] 4. Evaluate and improve OPC technology

[0059] Test patterns can help evaluate the effectiveness of OPC technology, especially when dealing with complex two-dimensional layout designs. For example, test patterns can be used to evaluate the performance of OPC technology under extreme conditions and drive technology improvements.

[0060] 5. Reduce manufacturing costs

[0061] By optimizing the OPC model using test patterns, the accuracy and reliability of chip manufacturing can be improved without increasing additional manufacturing costs. This helps reduce chip defects caused by lithography errors, thereby reducing manufacturing costs.

[0062] Therefore, test patterns for optical proximity correction models are an indispensable part of the chip manufacturing process, as they are used to calibrate and verify OPC models, optimize lithography processes, improve model accuracy, evaluate the effectiveness of OPC technology, and reduce manufacturing costs.

[0063] The embodiment of the present application provides a test pattern selection method, and a flowchart thereof is shown as follows: Figure 1 The method comprises the following steps:

[0064] S101, acquiring a test layout; the test layout comprises at least one candidate test pattern.

[0065] Each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark patterns expected to be tested on a chip, and the preset detection frame is used to provide a detection space to screen patterns with labels.

[0066] The label used to mark the pattern expected to be tested on the chip refers to a pattern that is expected to be tested on the chip. This is because the label is only a description of the pattern, and the candidate test pattern is the basis for actually performing lithography experiments and model verification. If the pattern has a label but does not have actual pattern information that can be tested on the chip, lithography experiments cannot be performed, and the correction effect of the OPC model cannot be verified. Therefore, the determination of the candidate test pattern only by the label is prone to the case that the pattern does not have a test function.

[0067] Based on this, in the embodiments of the present application, for the pattern with a label, a preset detection frame is further used for screening to ensure that the candidate test pattern has an actual test function.

[0068] The obtained test layout can be, for example, the test layout itself or a data file of the test layout; the test layout itself is a physical design in the chip design stage and contains test patterns and circuits; the data file of the test layout is a digital representation of the test layout and is used to manufacture a mask plate; the data file of the test layout can be, for example, a file stored in a GDSII format.

[0069] In S102, features of each candidate test pattern are extracted, and a category of the candidate test pattern is determined based on the features of the candidate test pattern; the features are used to describe attributes of the candidate test pattern.

[0070] The attributes of the candidate test pattern can include geometric features, complexity or other related attributes.

[0071] When classifying the candidate test pattern, the candidate test pattern can be grouped according to geometric features, complexity or other related attributes, so as to more systematically design experiments, optimize models and ensure the coverage of the OPC model.

[0072] The geometric features can be:

[0073] Line width and pitch: the line width and pitch of the candidate test pattern are very important parameters in the lithography process. The patterns can be classified into different categories according to the range of the line width and pitch, for example, patterns with a line width less than a certain threshold are classified into one category, and patterns with a pitch greater than a certain threshold are classified into another category.

[0074] Shape: the shape (such as straight line, curve, polygon, circle, etc.) of the candidate test pattern also affects the lithography result. Therefore, the patterns can be classified into different categories according to the shape, for example, all straight line patterns are classified into one category, and all circular patterns are classified into another category.

[0075] Arrangement: the arrangement (such as periodic arrangement, random arrangement, etc.) of the candidate test pattern also affects the lithography result. The patterns can be classified into different categories according to the arrangement.

[0076] Complexity refers to:

[0077] Graphic complexity: Some candidate test graphics may contain multiple geometric elements or complex shapes, indicating higher complexity. Candidate test graphics can be divided into different categories based on their complexity. For example, simple graphics (such as a single line) can be grouped into one category, while complex graphics (such as polygons) can be grouped into another.

[0078] Pattern density: The density of candidate test patterns (i.e., the number of patterns per unit area) also affects the lithography results. Candidate test patterns can be divided into different categories based on their density.

[0079] For example, the result of classifying the candidate test patterns based on their features may be:

[0080] Category 1: Linear graphics with a line width less than 100nm.

[0081] Category 2: Circular patterns with a spacing greater than 200nm.

[0082] Category 3: Graphics with complex shapes (such as polygon combinations).

[0083] Category 4: Highly densely arranged graphics.

[0084] S103 : In each determined candidate test pattern category, a corresponding target test pattern is selected according to the modeling data requirements of the optical proximity correction model.

[0085] Each category of candidate test patterns includes multiple candidate test patterns. Each candidate test pattern has specific characteristics that meet the requirements of that category. For example, in the aforementioned category 1, which includes straight line patterns with a line width less than 100 nm, the candidate test patterns in category 1 may include straight line patterns of various line widths less than 100 nm.

[0086] After completing the classification of candidate test patterns, the characteristics of the candidate test patterns can be organized and understood more systematically. That is, classification only divides the candidate test patterns into groups with similar characteristics, but the classification process does not directly consider the specific needs of OPC model building.

[0087] Each classified category may contain a large number of candidate test patterns, but not all of these candidate test patterns are suitable for OPC modeling. The OPC model needs to cover a variety of possible lithography scenarios to ensure the accuracy and reliability of the model. Although the classified candidate test patterns have been grouped by features, not all candidate test patterns are representative or critical. Therefore, based on the modeling data requirements of the OPC model, candidate test patterns that can cover critical scenarios are further screened out. The screened target test patterns are used as modeling data for constructing the OPC model, thereby ensuring the quality and representativeness of the modeling data and improving the accuracy and reliability of the OPC model.

[0088] The test layout for the optical proximity correction (OPC) model is a key tool for calibrating and validating the OPC model. The design and selection methods of the test layout directly affect the accuracy and effectiveness of the OPC model. The following details the definition, design methods, and selection principles of the OPC test layout:

[0089] OPC test patterns are a collection of patterns designed specifically for calibrating and validating OPC models. These patterns are used to collect experimental data to optimize empirical parameters in the OPC model, ensuring accurate compensation for optical proximity effects during the lithography process.

[0090] Design Method of OPC Test Layout

[0091] 1. One-dimensional (1D) and two-dimensional (2D) test patterns:

[0092] One-dimensional test pattern: usually a relatively long line, used to test changes in line width and spacing.

[0093] Two-dimensional test pattern: A pattern with corners or endpoints used to test more complex lithography effects.

[0094] The design of one-dimensional and two-dimensional test patterns needs to consider the adjacent configuration of lines and patterns with different orientations.

[0095] 2. Model-based test pattern generation:

[0096] Using optical models (such as the partially coherent imaging model) and photoresist reaction models, the edge correction amount is dynamically calculated to generate corrected mask data. The OPC model is adjusted by comparing simulated exposure and actual exposure patterns.

[0097] 3. Test graphics optimization:

[0098] Optimize test layout by reducing the number of test patterns while ensuring coverage of all key process nodes.

[0099] The Monte Carlo method is used to perform permutations and combinations within a preset graphic frame according to a certain filling probability to generate a two-dimensional OPC test pattern.

[0100] OPC test layout selection principles

[0101] 1. Key feature size coverage:

[0102] When selecting test patterns, include patterns that are close to the design rule limits, such as minimum line width and minimum spacing.

[0103] Test patterns should cover the range from the smallest design feature size to larger sizes.

[0104] 2. Impact of environmental graphics:

[0105] Consider the surrounding graphics around the target graphics that have a serious optical proximity effect on it.

[0106] When correcting the target pattern, the environmental pattern must be considered to simulate the lithographic imaging of the target pattern.

[0107] 3. Test the diversity of graphics:

[0108] The test patterns should include patterns with varying line width and period, independent patterns under dark and bright fields, and discontinuous patterns under dark and bright fields.

[0109] Through a variety of test patterns, it is ensured that the OPC model can adapt to different lithography conditions.

[0110] 4. Validity of experimental data:

[0111] The test pattern must be designed to ensure that the data collected is effective for calibrating the OPC model.

[0112] The effectiveness of the test pattern is verified by comparing the actual exposure and simulated exposure patterns.

[0113] Application of OPC test layout

[0114] 1. Model calibration:

[0115] Use the data collected from the test layout to calibrate the empirical parameters in the OPC model.

[0116] By adjusting the model parameters, the error between the actual exposure pattern and the simulated exposure pattern is minimized.

[0117] 2. Model Validation:

[0118] Verify the accuracy and reliability of the OPC model under different process conditions.

[0119] Ensure that the OPC model can effectively compensate for the optical proximity effect and improve lithography accuracy.

[0120] By properly designing and selecting OPC test layouts, the accuracy and reliability of OPC models can be significantly improved, thereby enabling smaller and more complex integrated circuit designs in semiconductor manufacturing.

[0121] Test patterns are widely used in the field of semiconductor manufacturing, running through all aspects of chip design, manufacturing, testing and process optimization. The following are specific applications of test patterns in the field of semiconductor manufacturing:

[0122] 1. Photolithography process development and optimization

[0123] Function: Test patterns are used to evaluate the accuracy and stability of the lithography process and help optimize lithography parameters.

[0124] Specific applications:

[0125] Resolution test: Evaluate the minimum resolution of the photolithography process by designing line and space patterns of different sizes.

[0126] Process window test: Design a series of test patterns under different exposure doses and focal length conditions to evaluate the process window of the lithography process.

[0127] Proximity effect test: Evaluate the optical proximity effect (such as line width variation and pattern deformation) by designing patterns with different densities and layouts.

[0128] 2. Optical Proximity Correction (OPC) Model Development and Verification

[0129] Function: Test graphics provide experimental data for the development and verification of OPC models to ensure the accuracy and reliability of the models.

[0130] Specific applications:

[0131] Model training: The OPC model is trained using the results of lithography test patterns to enable it to accurately predict the optical effects during the lithography process.

[0132] Model verification: Compare the simulation results of the OPC model with the actual lithography results to verify the accuracy of the model and make necessary adjustments.

[0133] Model optimization: Through different types of test patterns, the parameters of the OPC model are optimized to improve the adaptability and accuracy of the model.

[0134] 3. Chip function and performance testing

[0135] Function: Test patterns are used to verify the functionality and performance of the chip against design requirements.

[0136] Specific applications:

[0137] Logic function test: Design specific logic circuit test patterns to verify the correctness of the chip's logic functions.

[0138] Memory function test: Design memory cell test patterns to verify the read / write functions and data retention capabilities of the memory chip.

[0139] Analog function test: Design test patterns for amplifiers, filters, and other analog circuits to verify the chip's analog functions.

[0140] Speed and power consumption test: Design high-speed signal transmission and high-load test patterns to evaluate the chip's speed and power consumption.

[0141] 4. Process optimization and reliability evaluation

[0142] Function: Test patterns are used to optimize manufacturing processes and evaluate the reliability of the chip under different environmental conditions.

[0143] Specific applications:

[0144] High and low temperature test: Design test patterns that can work in high and low temperature environments to evaluate the chip's temperature characteristics.

[0145] Radiation test: Design test patterns that can work in radiation environments to evaluate the chip's radiation resistance.

[0146] Lifetime test: Design long-term running test patterns to evaluate the chip's service life and reliability.

[0147] 5. Design rule verification

[0148] Function: Test patterns are used to verify the effectiveness and rationality of design rules to ensure the manufacturability of the design.

[0149] Specific applications:

[0150] Minimum size test: Design test patterns with minimum line width and spacing to verify the minimum size limit of the design rules.

[0151] Density and layout test: Design test patterns with different densities and layouts to verify the density and layout requirements of the design rules.

[0152] Process compatibility test: Design test patterns under various process conditions to verify the process compatibility of the design rules.

[0153] Test patterns have a wide range of applications in the semiconductor manufacturing industry, from optimizing processes such as lithography and etching, to testing chip functionality and performance, to defect detection and quality control. By designing and using test patterns appropriately, the precision, yield, and reliability of semiconductor manufacturing can be improved, ensuring the performance of chips in actual applications.

[0154] Test patterns are processed in the form of data files, which are important for recording and analyzing various measurement data in test patterns. They usually include the following categories:

[0155] 1. Geometric information of test patterns

[0156] Pattern ID: A unique identifier for each test pattern.

[0157] Pattern type: The type of test pattern (such as lines, holes, corners, etc.).

[0158] Size information: The size of the pattern, such as line width, pitch, area, etc.

[0159] Position information: The coordinate position of the pattern in the layout (such as X and Y coordinates).

[0160] Layer information: The process layer where the pattern is located (such as polysilicon layer, metal layer, etc.).

[0161] 2. Measurement data

[0162] Critical dimension (CD): The key dimension of the pattern, such as line width, hole diameter, etc.

[0163] Pitch: The distance between adjacent patterns.

[0164] Line edge roughness (LER): The irregularity of the pattern edge.

[0165] Line width uniformity (LWU): The range of variation in the line width of the pattern.

[0166] Overlay accuracy: The alignment accuracy of patterns between different layers.

[0167] Other relevant dimensions: Such as the height, depth, etc. of the pattern (if applicable).

[0168] 3. Process parameters

[0169] Exposure dose: The exposure energy used in the lithography process.

[0170] Focal length: The focal point position of the light beam in the lithography process.

[0171] Photoresist thickness: The thickness of the photoresist.

[0172] Developing time: time of developing process.

[0173] Etching time: time of etching process.

[0174] 4. Measurement device information

[0175] Device ID: unique identifier of measurement device.

[0176] Measurement time: specific timestamp of data measurement.

[0177] Measurement method: measurement technique used (e.g. scanning electron microscope SEM, atomic force microscope AFM, etc.).

[0178] Measurement accuracy: accuracy or resolution of measurement device.

[0179] 5. Environmental conditions

[0180] Temperature: environmental temperature at measurement.

[0181] Humidity: environmental humidity at measurement.

[0182] Cleanliness: cleanliness level of measurement environment.

[0183] By reasonably designing and recording the data file of the test layout, the process development, optimization and quality control in semiconductor manufacturing can be effectively supported.

[0184] In one embodiment, each candidate test pattern is obtained by screening the patterns in the test layout based on the label and the preset detection frame, and can include:

[0185] For the pattern with the label in the test layout, it is determined whether there is pattern information of the test chip in the preset detection frame corresponding to the pattern with the label.

[0186] If not, the pattern is deleted; if yes, the pattern is determined as a candidate test pattern.

[0187] The processed initial test layout is taken as the test layout.

[0188] Further, the label is located at the bottom of the pattern in the test layout; and the determination of whether there is pattern information of the test chip in the preset detection frame corresponding to the pattern with the label includes:

[0189] For the pattern with the label in the layout, a preset detection frame is determined from the bottom of the label to a region away from the bottom of the label by a first value in the direction of the top of the pattern.

[0190] In the preset detection frame, it is judged whether there is test chip pattern information; the area is the detection space.

[0191] The judgment process of the candidate test pattern can be, for example, as shown in Figure 2a and Figure 2b In Figure 2a and Figure 2b , A represents a pattern in a layout, a block diagram B below the pattern A, that is, the bottom, is a label, and a region C from the bottom of the block diagram B to the bottom of the block diagram B in the top direction Y of the pattern is a preset detection frame.

[0192] The first value can be 11um.

[0193] In the foregoing step 102, the characteristics of the candidate test pattern can include, for example, geometric characteristics, functional characteristics, process characteristics, and layout characteristics:

[0194] As described above, the geometric characteristics can include, for example, the shape, size, symmetry, and repetition of the test pattern.

[0195] The specific size of the candidate test pattern, such as line width, pitch, pattern area, etc. Symmetry: whether the candidate test pattern has symmetry, such as symmetric line pairs or symmetric geometric patterns. Repetition: whether the candidate test pattern has repeated structures, such as repeated lines or patterns.

[0196] The functional characteristics can include, for example, purpose, measurement parameter, and test target.

[0197] Purpose: the main function of the test pattern, such as alignment mark, size measurement, bridge detection, electrical property test, etc.

[0198] Measurement parameter: specific parameters for measurement of the test pattern, such as critical dimension (CD), alignment accuracy, electrical performance, etc.

[0199] Test target: specific manufacturing process or performance index targeted by the test pattern, such as lithography resolution, etching accuracy, doping concentration, etc.

[0200] The process characteristics can include, for example, manufacturing process, material, and interlayer relationship.

[0201] Manufacturing process: specific manufacturing process involved in the test pattern, such as lithography, etching, doping, multi-layer interconnection, etc.

[0202] Material: material used by the test pattern, such as polysilicon, metal, oxide, etc.

[0203] Interlayer relationship: position and relationship of the test pattern in a multi-layer structure, such as interlayer alignment, interlayer isolation, etc.

[0204] Layout features may include, for example, location, density, and distribution.

[0205] Location: The specific position of the test pattern in the chip layout, such as edge, center, specific area, etc.

[0206] Density: The distribution density of the test pattern, such as high density, low density, etc.

[0207] Distribution: The distribution manner of the test pattern, such as uniform distribution, concentrated distribution, etc.

[0208] Based on the different categories of candidate test pattern features mentioned above, different methods can be used to extract the features of the candidate test pattern:

[0209] Extracting geometric features, functional features, process features, and layout features of candidate test patterns is a key step in semiconductor manufacturing and testing, and each feature extraction method has its specific technology and tools. The following is a detailed method introduction:

[0210] 1. Extract geometric features

[0211] Geometric features mainly describe the shape, size, and position information of the candidate test pattern. The extraction method includes:

[0212] (1) Size measurement

[0213] Tools: Layout design software (such as Cadence Virtuoso, Mentor Graphics Calibre) or special measurement tools (such as CD-SEM).

[0214] Method:

[0215] Line width: Measure the width of the line, usually directly measured by the measurement tool of the layout design software or CD-SEM.

[0216] Pitch: Measure the pitch between adjacent lines.

[0217] Aperture size: Measure the diameter or side length of the circular or rectangular aperture.

[0218] Pattern area: Calculate the area of the candidate test pattern, which can be achieved by the calculation function of the layout design software.

[0219] (2) Shape analysis

[0220] Tools: Layout design software or image processing tools (such as MATLAB, OpenCV).

[0221] Method:

[0222] Perimeter: Calculate the perimeter of the candidate test pattern.

[0223] Shape Factor: Calculate shape factor, such as circularity (Circularity = 4π × Area / Perimeter2).

[0224] Directionality: Determine the main axis direction of the pattern by principal component analysis (PCA).

[0225] 2. Extract process features

[0226] Process features describe the process impact that the candidate test pattern may be subjected to during manufacturing, such as photolithography, etching, and ion implantation, etc. The extraction methods include:

[0227] (1) Photolithography process features

[0228] Tool: Optical simulation software (such as ASML PROLITH, DiffractEM). Calculate the light intensity distribution of the candidate test pattern during the photolithography process through optical simulation.

[0229] (2) Etching process features

[0230] Tool: Etching simulation software or actual etching test. Measure the etching rate of different materials through experiments.

[0231] As can be seen, the extraction of features of the candidate test pattern requires the selection of appropriate methods and tools according to specific needs. Geometric features can be extracted by layout design software and measurement tools; functional features can be extracted by logic simulation, memory testing, and circuit simulation; process features can be extracted by optical simulation, etching test, and ion implantation test; layout features can be extracted by layout design software and image processing tools. By comprehensive application of these methods, the characteristics of the test pattern can be comprehensively evaluated, providing strong support for semiconductor manufacturing and testing.

[0232] Determining the category of the candidate test pattern according to its features is a typical pattern recognition and classification problem. For example, the following methods can be used:

[0233] 1. Traditional machine learning method

[0234] Feature extraction: First, extract geometric features, functional features, process features, and layout features, etc. from the candidate test pattern.

[0235] Feature selection: Select features that are helpful for classification, which can use methods such as chi-square test, mutual information, etc.

[0236] Classification algorithm: Use machine learning classification algorithms such as support vector machine (SVM), random forest (RandomForest), K-nearest neighbor (K-NN), logistic regression (Logistic Regression), etc. for classification.

[0237] 2. Deep learning methods

[0238] Convolutional Neural Network (CNN): Automatically extract image features and classify using CNN. CNN can learn local and global features of candidate test patterns, suitable for image classification tasks.

[0239] Recurrent Neural Network (RNN): If the candidate test pattern has sequential properties, RNN can be used for classification.

[0240] 3. Clustering methods

[0241] Unsupervised learning: If the category of the candidate test pattern is unknown, unsupervised learning methods such as K-Means, DBSCAN, etc. can be used for clustering, and then the category can be determined according to the clustering results.

[0242] 4. Feature matching method

[0243] Template matching: If the category of the candidate test pattern is known, template matching method can be used to match the candidate test pattern with the template image of the known category, and determine the category of the candidate test pattern.

[0244] 5. Practical applications

[0245] Optimization of lithography process: According to the geometric features and process features of the candidate test pattern, the category of the candidate test pattern is determined, and the lithography process is optimized.

[0246] Functional verification: According to the functional features and electrical features of the candidate test pattern, the category of the candidate test pattern is determined, and the function and performance of the candidate test pattern are verified.

[0247] By reasonably selecting and combining these methods, the category of the test image can be effectively determined, and strong support can be provided for semiconductor manufacturing and testing.

[0248] In the foregoing step 102, the step of determining the category of the candidate test pattern based on the features of the candidate test pattern can be realized by a pattern classification algorithm, which belongs to the above-mentioned deep learning method. In the present application, the category of the candidate test pattern can also be determined according to the features of the candidate test pattern by any means, and the present application embodiment does not limit this.

[0249] Graph Classification is an important task in Graph Neural Networks (GNNs), which aims to assign input graph-structured data to predefined categories.

[0250] The steps of the pattern classification algorithm are a systematic process, from data preparation to model deployment, each step is crucial. Through reasonable design and optimization, an efficient and accurate pattern classification model can be developed to meet the needs of practical applications.

[0251] Determining the category of the candidate test pattern based on the features of the candidate test pattern can include:

[0252] Determining the features of the measurement points of the candidate test pattern based on the features of the candidate test pattern;

[0253] Determining the category of the candidate test pattern using the determined features of the measurement points.

[0254] In semiconductor manufacturing and testing, "measurement points of test patterns" refer to specific locations selected on test patterns for measuring and evaluating geometric features, process parameters, or electrical properties, etc. The selection of these measurement points is crucial for ensuring the accuracy and reliability of test results. Here are the details about test pattern measurement points:

[0255] Measurement points can evaluate process quality, measure geometric features such as line width, spacing, aperture size, etc. to evaluate the quality of processes such as lithography, etching, etc. They can also detect defects by measuring electrical properties or geometric features of measurement points to detect defects that may occur during the manufacturing process (such as short circuits, open circuits, particle contamination, etc.). And optimize process parameters, by analyzing the data of measurement points, optimize the process parameters of lithography, etching, ion implantation, etc. to improve the process window and yield.

[0256] The following principles can be considered when selecting measurement points:

[0257] Representative: Measurement points should be able to represent the key features and process conditions of the entire test pattern or chip.

[0258] Uniform distribution: Measurement points should be evenly distributed on the test pattern to ensure the comprehensiveness and consistency of the measurement results.

[0259] Key area priority: Preferentially select areas that are sensitive to process or have a greater impact on function as measurement points.

[0260] Repeatability: The selection of measurement points should have repeatability, making it easy to measure and compare multiple times.

[0261] Measurability: Measurement points should be able to be measured by existing measurement equipment (such as CD-SEM, AFM, optical measurement tools, etc.).

[0262] According to the measurement content and purpose, measurement points can be divided into the following types:

[0263] (1) Geometric measurement points

[0264] Geometric feature measurement points for measuring geometric features of test patterns, such as:

[0265] Line width measurement points: measure the width of lines.

[0266] Pitch measurement points: measure the pitch between adjacent lines.

[0267] Aperture measurement points: measure the diameter or side length of circular or rectangular apertures.

[0268] Pattern area measurement points: measure the area of test patterns.

[0269] Perimeter measurement points: measure the perimeter of test patterns.

[0270] (2) Electrical measurement points

[0271] Electrical property measurement points for measuring electrical properties of test patterns, such as:

[0272] Resistance measurement points: measure the resistance value of test patterns.

[0273] Capacitance measurement points: measure the capacitance value of test patterns.

[0274] Threshold voltage measurement points: measure the threshold voltage of transistors.

[0275] Leakage current measurement points: measure the leakage current of test patterns.

[0276] (3) Process measurement points

[0277] Process quality and stability evaluation points for evaluating the quality and stability of manufacturing processes, such as:

[0278] Lithography measurement points: evaluate the resolution and process window of lithography processes.

[0279] Etching measurement points: evaluate the selectivity and uniformity of etching processes.

[0280] Ion implantation measurement points: evaluate the doping concentration and depth distribution of ion implantation processes.

[0281] (4) Defect detection measurement points

[0282] Defect detection points for detecting defects that may occur during manufacturing, such as:

[0283] Short circuit detection measurement points: detect whether short circuits exist between test patterns.

[0284] Open circuit detection measurement points: detect whether open circuits exist in test patterns.

[0285] Particle contamination measurement points: detect whether particle contamination exists on the surface of test patterns.

[0286] The arrangement method of the measurement points should be designed according to the category of the candidate test patterns and the measurement purpose.

[0287] The test pattern measurement points are important tools for evaluating the quality of semiconductor manufacturing processes and the performance of chips. By reasonably selecting and arranging the measurement points and using appropriate measurement equipment, the characteristics and performance of the test patterns can be effectively evaluated, providing strong support for semiconductor manufacturing and testing.

[0288] In the above step 103, the modeling data requirements include: feature size control data requirements; the feature size control data includes: critical dimension and center-to-center distance.

[0289] On the basis of the above-mentioned modeling data requirements, the test pattern selection method provided by the embodiment of the application can select the target test pattern again under each category, and the basis for the re-selection is the critical dimension and the center-to-center distance; therefore, different sizes of critical dimensions can be covered in the candidate test patterns of each category, and the selected target test pattern has sufficient coverage of the actual design pattern, so as to ensure the accuracy of the model.

[0290] Specifically, the critical dimension includes: line width, pitch, aperture size, pattern area, line edge roughness, line width uniformity, registration accuracy, pattern height, and pattern depth.

[0291] In the optical proximity correction (OPC) model, critical dimension (CD) and center-to-center distance (Pitch) are two important concepts that play a key role in the photolithography process.

[0292] CD (Critical Dimension) refers to the feature size that needs to be strictly controlled in the design and manufacturing process of semiconductor manufacturing, such as the gate width of a transistor, the minimum line width, etc. CD is used to ensure that the actual pattern formed in the photolithography process is consistent with the design pattern.

[0293] Pitch (center-to-center distance) refers to the distance between adjacent patterns, including horizontal pitch and vertical pitch. In the OPC model, pitch is one of the important parameters that affect the photolithography effect, because it determines the mutual influence between patterns. By adjusting the pitch, the resolution and uniformity of the photolithography pattern can be optimized.

[0294] As can be seen, CD and Pitch are indispensable parameters in the OPC model, which directly affect the quality of the photolithography pattern and the stability of the process.

[0295] In one embodiment, taking the aforementioned CD and Pitch as an example, the aforementioned target test pattern meets the modeling data requirements, i.e., the aforementioned target test pattern meets the specific selection requirements for different CD and Pitch.

[0296] Specifically, the step S103 can be implemented by the following manner, for example:

[0297] According to the measurement points in the candidate test patterns, a data set containing key data and non-key data is formed; the key data is the measurement point which has a great influence on the precision of the OPC model and can represent the edge case of the process window; the non-key data is the measurement point which has a small influence on the OPC model and is for the stable area in the center of the process window.

[0298] Taking the feature size control data including CD and Pitch as an example, the closer the CD and Pitch are to the process limit, the more the measurement point can represent the edge case of the process window, and the more the measurement point can represent the edge case of the process window, the greater the influence of the measurement point on the precision of the OPC model.

[0299] According to the screening reference data set, the data set formed by each type of candidate test pattern is screened to obtain the target test pattern. The modeling data requirement of the OPC model is used to indicate that the most valuable screening reference data set is established for the OPC model.

[0300] In the above step S103, the present application can realize, in each type of candidate test pattern determined, according to the modeling data requirement of the OPC model, screening of the corresponding target test pattern by a machine learning algorithm. The machine learning algorithm includes a neural network model. Training the neural network model includes the following steps:

[0301] Step 1: Divide the data set formed by each type of historical test pattern into a training set and a test set according to a ratio of 7:3.

[0302] Step 2: In the neural network model, different weights are assigned to the key data and non-key data in the data set formed by the candidate test pattern, and the weight of the key data is greater than the weight of the non-key data.

[0303] Step 3: According to the training set, the neural network model is trained to obtain a trained screening model.

[0304] Step 4: The trained screening model is tested using the test set to determine the recall rate and precision rate of the test pattern screened by the trained screening model.

[0305] Step 5: According to the recall rate and the precision rate, a screening reference data set is determined, and according to the screening reference data set, the data set formed by each type of candidate test pattern is screened to obtain the target test pattern.

[0306] The recall rate refers to the proportion of the correctly screened test patterns among all the test patterns meeting the screening reference data set. It reflects how many actually relevant test patterns the screening model can cover.

[0307] Precision refers to the proportion of actual compliance with the screening benchmark data set among all screened test patterns. It reflects the accuracy of the screening model.

[0308] Step 6: During training and testing, the classification threshold and weight of key data and non-key data are iteratively adjusted to screen out the most valuable target test patterns for the optical proximity correction model.

[0309] The implementation and application of machine learning algorithms usually involve a series of standardized steps that ensure the systematicity and effectiveness of the entire process from data preparation to model deployment.

[0310] Machine learning algorithms can be specifically selected and used according to the type of problem. For example:

[0311] For classification problems: logistic regression, support vector machine (SVM), decision tree, random forest, gradient boosting tree (GBDT), neural network, etc.

[0312] For clustering problems: K-Means, hierarchical clustering, DBSCAN, etc.

[0313] Through reasonable design and optimization, efficient and accurate machine learning models can be developed to meet actual application requirements.

[0314] After the above S103 step, the target test pattern can be stored in CSV (Comma-Separated Values) format, and the CSV measurement file is a common data storage format widely used for storing and exchanging measurement data, especially in the fields of semiconductor manufacturing, lithography, metrology, etc. CSV files store data in plain text format, with each row representing a data record and fields separated by commas.

[0315] In the calibration process of the OPC (optical proximity correction) model, the data in the CSV measurement file can be used to verify and optimize the model parameters.

[0316] The CSV measurement file is a simple and powerful data storage and exchange format widely used in the fields of semiconductor manufacturing and lithography. By reasonably designing and processing CSV files, measurement data can be effectively stored, exchanged and analyzed, providing support for process optimization and quality control.

[0317] Based on the same inventive concept, the embodiments of the present application also provide an optical proximity correction model generation method, the flow chart of which is as shown in Figure 3 , which comprises:

[0318] S301, obtaining a target test pattern.

[0319] The target test pattern is selected based on the selection method of the test pattern in any of the preceding embodiments.

[0320] S302, based on the target test pattern, an optical proximity correction model is established.

[0321] The method for generating an optical proximity correction model provided in the embodiments of the present application selects a target test pattern by using the selection method of the test pattern, and establishes the optical proximity correction model based on the target test pattern, thereby shortening the modeling cycle and improving the accuracy of the optical proximity correction model.

[0322] Based on the same inventive concept, the embodiments of the present application also provide a selection device for a test pattern, a structural block diagram of which is shown in Figure 4 The selection device for a test pattern comprises:

[0323] A layout acquisition module 41 is configured to acquire a test layout; the test layout comprises at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark patterns expected to be tested on a chip, and the preset detection frame is used to provide a detection space to screen patterns with the label;

[0324] A feature extraction and classification determination module 42 is configured to extract features of each candidate test pattern, and determine the category of the candidate test pattern based on the features of the candidate test pattern; the features are used to describe the attributes of the candidate test pattern;

[0325] A screening module 43 is configured to select a corresponding target test pattern from each category of the determined candidate test patterns according to the modeling data requirements of the optical proximity correction model.

[0326] Based on the same inventive concept, the embodiments of the present application also provide a device for generating an optical proximity correction model, a structural block diagram of which is shown in Figure 5 The device for generating an optical proximity correction model comprises:

[0327] A target test pattern acquisition module 51 is configured to acquire a target test pattern; the target test pattern is selected by the selection device for a test pattern;

[0328] A model establishment module 52 is configured to establish an optical proximity correction model based on the target test pattern.

[0329] Based on the same inventive concept, the embodiments of the present application also provide an electronic device comprising a memory and a processor; the memory stores a program; the processor invokes the program stored in the memory to execute the selection method for a test pattern or the method for generating an optical proximity correction model.

[0330] Based on the same inventive concept, the embodiment of the present application further provides a storage medium, which stores a program, and the program is executed to realize the test pattern selection method or the optical proximity correction model generation method.

[0331] Based on the same inventive concept, the embodiment of the present application further provides a computer program product, which comprises a computer program, and the computer program is executed to realize the test pattern selection method or the optical proximity correction model generation method.

[0332] The electronic device of the embodiment of the present application includes but is not limited to a mobile communication device, an ultra-mobile personal computer device, a portable entertainment device, a server and other electronic devices with data interaction function, wherein the mobile communication device includes but is not limited to a smart phone and a multimedia phone, the ultra-mobile personal computer device includes but is not limited to a tablet computer, the portable entertainment device includes but is not limited to an electronic book and a handheld game console, and the server includes but is not limited to a computer device.

[0333] The above describes the multiple embodiment schemes provided by the embodiment of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiment schemes disclosed and published by the embodiment of the present application.

[0334] Although the embodiment of the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A method for selecting a test pattern, characterized in that: include: Get the test layout; The test layout includes: at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark a pattern expected to be tested on the chip, and the preset detection frame is used to provide a detection space for screening patterns with a label; Extracting features of each candidate test pattern and determining the category of the candidate test pattern based on the features of the candidate test pattern; the features are used to describe the attributes of the candidate test pattern; In each determined type of candidate test patterns, a corresponding target test pattern is selected according to the modeling data requirements of the optical proximity correction model.

2. The method for selecting a test pattern according to claim 1, wherein: Each candidate test pattern is obtained by screening the patterns in the test layout based on the label and the preset detection frame, including: For a graphic with a label in the test layout, determining whether there is graphic information of a test chip within a preset detection box corresponding to the graphic with the label; If not, the pattern is deleted; if so, the pattern is determined to be a candidate test pattern; The processed initial test layout is used as the test layout.

3. The test pattern selection method according to claim 2, characterized in that: The label is located at the bottom of a graphic in the test layout; and for the graphic with the label in the test layout, determining whether there is graphic information of the test chip within a preset detection box corresponding to the graphic with the label, includes: For a graphic with a label in the layout, determine whether there is graphic information of a test chip within a preset detection frame formed by an area starting from the bottom of the label and a first value away from the top of the graphic; the area is the detection space.

4. The method for selecting a test pattern according to claim 1, wherein: The step of determining the category of the candidate test pattern based on the features of the candidate test pattern is implemented by a pattern classification algorithm.

5. The method for selecting a test pattern according to claim 1, wherein: The features include: geometric features, functional features, process features and layout features.

6. The method for selecting a test pattern according to claim 1, wherein: The determining the category of the candidate test pattern based on the features of the candidate test pattern includes: determining features of measurement points of the candidate test pattern based on the features of the candidate test pattern; The category of the candidate test pattern is determined using the determined features of the measurement points.

7. The test pattern selection method according to claim 1, characterized in that: The modeling data requirements include: feature size control data requirements.

8. The method for selecting a test pattern according to claim 7, wherein: The feature size control data includes: critical size and center distance.

9. The method for selecting a test pattern according to claim 8, wherein: The critical dimensions include: line width, spacing, aperture size, pattern area, line edge roughness, line width uniformity, registration accuracy, pattern height and pattern depth.

10. The test pattern selection method according to claim 1, characterized in that: The method of selecting the corresponding target test pattern from each determined candidate test pattern category according to the modeling data requirements of the optical proximity correction model is implemented by a machine learning algorithm.

11. The test pattern selection method according to claim 1, wherein: The modeling data requirements of the optical proximity correction model are used to indicate the most valuable screening benchmark data set for building the optical proximity correction model; The method of screening out a corresponding target test pattern from each determined candidate test pattern category according to the modeling data requirements of the optical proximity correction model includes: According to the measurement points in the candidate test pattern, a data set including key data and non-key data is formed; According to the screening benchmark data set, a data set formed by each type of candidate test patterns is screened to obtain a target test pattern.

12. A method for generating an optical proximity correction model, characterized in that: include: Get the target test pattern; The target test pattern is selected based on the test pattern selection method according to any one of claims 1 to 11; An optical proximity correction model is established based on the target test pattern.

13. A test pattern selection device, characterized in that: include: Layout acquisition module, used to obtain the test layout; The test layout includes: at least one candidate test pattern; wherein each candidate test pattern is obtained by screening patterns in the test layout based on a label and a preset detection frame; the label is used to mark a pattern expected to be tested on the chip, and the preset detection frame is used to provide a detection space for screening patterns with a label; A feature extraction and classification determination module is used to extract features of each candidate test pattern; and determine the category of the candidate test pattern based on the features of the candidate test pattern; the features are used to describe the attributes of the candidate test pattern; The screening module is used to select a corresponding target test pattern from each determined candidate test pattern according to the modeling data requirements of the optical proximity correction model.

14. An optical proximity correction model generation device, characterized in that: include: A target test pattern acquisition module is used to acquire a target test pattern; The target test pattern is selected based on the test pattern selection device according to claim 13; The model building module is used to build an optical proximity correction model based on the target test pattern.

15. An electronic device comprising a memory and a processor, characterized in that: The memory stores a program, and the processor calls the program stored in the memory to execute the test pattern selection method according to any one of claims 1 to 11 or the optical proximity correction model generation method according to claim 12.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed, the test pattern selection method according to any one of claims 1 to 11 or the optical proximity correction model generation method according to claim 12 is implemented.

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