Buffer insertion method, system, device, medium and product

Abstract

The present application relates to the physical design of semiconductor chips and integrated circuits, in particular to a buffer insertion method, system, device, medium and product. The buffer insertion method steps are as follows: inputting a steiner tree, traversing it in postorder; when a leaf node is traversed, obtaining the polarity requirement, the agreed arrival time and the load capacitance of the leaf node, and generating an initial candidate solution; the candidate solution includes parallel identification state and positive and negative polarity solution information. When a non-leaf node is traversed, according to the candidate solution type of the downstream node, all possible candidate solutions of inserting buffers or inverters are generated and added to the candidate solution list of the non-leaf node, and finally the positive polarity solution with the maximum agreed arrival time is selected from the candidate solution list of the root node, the generation path of the solution is traced back, the insertion positions of the buffers and inverters are extracted, and the buffer insertion scheme is output. The system, computer device, computer readable storage medium and computer program product of the present application have the same beneficial effects as the buffer insertion method.

Description

TECHNICAL FIELD

[0001] The present application relates to the physical design of semiconductor chips and integrated circuits, in particular to the timing correction link in the physical design process, and particularly to a buffer insertion method, system, device, medium and product. BACKGROUND

[0002] In the physical design phase of integrated circuits, as the process size continues to shrink, the interconnection line resistance increases sharply, while the interlayer dielectric constant decreases relatively slowly, resulting in the dominance of interconnection line delay caused by interconnection lines in the total path delay. Especially at advanced process nodes, interconnection line delay accounts for more than 50% of the total delay or even higher. Therefore, effectively optimizing interconnection line delay is one of the core challenges to achieve high-performance chip design and ensure timing convergence.

[0003] Buffer insertion technology is a core means to address this challenge. The basic principle is to insert a buffer unit, usually a non-inverting buffer or an inverter, at a long interconnection line or a high-load fanout point, to divide the large interconnection capacitance and fanout load into several smaller segments, reduce the effective load capacitance of the driving unit, and improve its driving ability; and to shape and restore the attenuated and distorted signal, effectively reducing the interconnection line delay.

[0004] However, in the buffer optimization insertion process, existing technologies usually rely on a pre-determined fixed Steiner tree topology for optimization. The topology generation phase does not consider the polarity requirements of the fanout end, resulting in the algorithm being forced to insert inverters at the branch nodes of the tree structure to correct the polarity signal in complex scenarios where the polarity requirements of the multiple fanout ends are inconsistent. This passive compensation mechanism can cause excessive insertion of inverters, which can directly degrade the timing margin of the critical path due to the inherent delay of the inverters and the additional wiring load, and the redundant inverters significantly increase the unit area overhead, exacerbating wiring congestion and power consumption.

[0005] There is an urgent need for a solution that can break the fixed topology restriction and actively optimize the interconnection tree structure while considering the signal polarity requirements during the buffer insertion process. SUMMARY

[0006] To solve the technical problem that existing buffer insertion technology is based on fixed topology restriction and cannot adapt to the polarity requirements of the fanout end, and is prone to forced insertion of excessive inverters to maintain the correctness of the signal polarity, the present application provides a buffer insertion method, system, device, medium and product.

[0007] The technical problem of the present application is solved by providing a buffer insertion method, comprising the following steps: inputting an initial Steiner tree, a polarity requirement list of leaf nodes and a design constraint file; performing post-order traversal on the Steiner tree; when a leaf node is traversed, obtaining the polarity requirement of the leaf node, and obtaining the committed arrival time and load capacitance of the leaf node from the design constraint file to generate an initial candidate solution; wherein the candidate solution includes a parallel state identifier, positive polarity solution information and negative polarity solution information; the parallel state identifier is used to indicate that the candidate solution is a positive polarity solution, a negative polarity solution or a positive-negative parallel solution; the positive polarity solution information and the negative polarity solution information respectively contain the committed arrival time and the load capacitance of the node when the candidate solution is a positive polarity solution or a negative polarity solution; when a non-leaf node is traversed, according to the candidate solution type of the downstream node, all possible candidate solutions of inserting a buffer or an inverter are generated, and the committed arrival time and the load capacitance corresponding to each candidate solution are updated; when the non-leaf node is a branch node, intermediate candidate solutions are generated, and all intermediate candidate solutions are added to the candidate solution list of the branch node; when the non-leaf node is a root node, all non-positive polarity solutions in the newly generated candidate solutions are converted into positive polarity solutions, the original positive polarity solutions and the converted positive polarity solutions jointly generate final candidate solutions, and all final candidate solutions are added to the candidate solution list of the root node; a positive polarity solution with the maximum committed arrival time is selected from the candidate solution list of the root node, the generation path of the positive polarity solution is traced back in reverse, the buffer and inverter insertion positions recorded in the path are extracted, and a buffer insertion scheme is output.

[0008] Preferably, when the parallel state identifier of the candidate solution is true, the positive polarity solution information and the negative polarity solution information both contain the corresponding committed arrival time and load capacitance, and the candidate solution at this time is a parallel solution pair; wherein the committed arrival time of the whole candidate solution is the minimum value of the committed arrival times of the positive polarity solution and the negative polarity solution, and the load capacitance of the whole is the sum of the load capacitances containing the positive polarity solution and the negative polarity solution.

[0009] When the parallel state identifier of the candidate solution is false, the positive polarity solution information and the negative polarity solution information are non-empty only one, that is, only one contains the corresponding committed arrival time and load capacitance; when the positive polarity solution information is non-empty, the candidate solution is a positive polarity solution; when the negative polarity solution information is non-empty, the candidate solution is a negative polarity solution; wherein the committed arrival time and the load capacitance of the whole candidate solution are the committed arrival time and the load capacitance of the corresponding polarity solution.

[0010] Preferably, when an edge is traversed, the committed arrival time and the load capacitance of the candidate solution of the downstream node are updated according to the candidate solution type of the downstream node connected by the edge, and the updated candidate solution is transmitted to the upstream node connected by the edge.

[0011] The committed arrival time update formula is:

[0012]

[0013] The load capacitance update formula is:

[0014]

[0015] The node u and the node v are connected to form an edge, the node u is a downstream node of the node v, Q(v) is the committed arrival time of the node v, Q(u) is the committed arrival time of the node u, C(v) is the load capacitance of the node v, C(u) is the load capacitance of the node u, unit_r is the resistance of a unit length of a conductor, unit_c is the capacitance of a unit length of a conductor, and l is the edge length of the edge;

[0016] When the candidate solution of the node u is a single-polarity solution, the committed arrival time and the load capacitance corresponding to the polarity solution of the node u are updated through the update formula, and a new candidate solution is generated and transmitted to the node v; when the candidate solution of the node u is a parallel solution, the update formula is independently applied to the positive and negative polarity solutions of the node u respectively, and the committed arrival time and the load capacitance corresponding to the positive and negative polarity solutions are obtained respectively, and a new candidate solution is generated and transmitted to the node v.

[0017] Preferably, when the non-leaf node has and only has one downstream node, a new candidate solution is generated by performing at least one of the following operations on the candidate solution of the downstream node:

[0018] No buffer or inverter is inserted, and the original candidate solution is maintained and transmitted to the non-leaf node; a buffer is inserted to generate a new candidate solution; an inverter is inserted to generate a new candidate solution; when the candidate solution is a parallel solution, a new candidate solution is generated through a degeneration operation; or, after the degeneration operation, an inverter is inserted to generate a new candidate solution;

[0019] When the candidate solution is inserted into the buffer and / or the inverter, the update formula of the committed arrival time is:

[0020]

[0021] The update formula of the load capacitance is:

[0022]

[0023] The node u is a downstream node of the node v, Q(v) is the committed arrival time of the node v, Q(u) is the committed arrival time of the node u, Q_Delay(buf) is the inherent delay of the buffer or the inverter, C(v) is the load capacitance of the node v, and C(buf) is the input capacitance of the buffer or the inverter.

[0024] Preferably, when the non-leaf node is a root node, at least one of the following operations is performed on the non-positive polarity solution in the generated new candidate solution to generate a final candidate solution: when the candidate solution is a negative polarity solution, an inverter is inserted to reverse the polarity; and when the candidate solution is a parallel solution, a degeneration operation is performed to degenerate into a positive polarity solution.

[0025] Preferably, when the non-leaf node has two downstream nodes, all possible new candidate solutions of inserting buffers or inverters are generated by a branch solution merging algorithm, wherein the branch solution merging algorithm comprises at least one of the following operations: merging solutions of the same polarity in the two downstream node candidate solutions; merging the candidate solution of the first downstream node after degenerating it into a single polarity solution by a degeneration operation, and the candidate solution of the second downstream node; merging the candidate solutions of the two downstream nodes after degenerating them into single polarity solutions by degeneration operations; inserting an inverter after degenerating the candidate solution of the first downstream node into a single polarity solution by a degeneration operation, and merging it with the candidate solution of the second downstream node.

[0026] Preferably, the degeneration operation comprises the following steps: extracting a positive polarity solution or a negative polarity solution of a parallel solution pair; inserting an inverter to generate a negative polarity solution from a positive polarity solution, or inserting an inverter to generate a positive polarity solution from a negative polarity solution; and merging solutions of the same polarity.

[0027] Preferably, when the non-leaf node is traversed, after all possible candidate solutions are generated and added to the candidate solution list, the following steps are further included: in the candidate solution list, deleting a suboptimal candidate solution whose scheduled arrival time is less than or equal to that of other candidate solutions, and whose load capacitance is greater than or equal to that of other candidate solutions; or, only deleting a candidate solution whose scheduled arrival time is less than or equal to that of other candidate solutions.

[0028] The application further provides a buffer insertion system, which comprises a user terminal and a micro-service terminal in communication connection; the micro-service terminal receives a to-be-processed command input by the user terminal, and executes the steps of the buffer insertion system according to the to-be-processed command.

[0029] The application further provides a computer device, which comprises a storage, a processor, and a computer program stored on the storage; the processor executes the computer program to realize the steps of the buffer insertion method.

[0030] The application further provides a computer readable storage medium, which stores a computer program; the computer program realizes the steps of the buffer insertion method when executed by a processor.

[0031] The application further provides a computer program product, which comprises a computer program; the computer program realizes the steps of the buffer insertion method when executed by a processor.

[0032] Compared with the prior art, the buffer insertion method, system, device, medium and product provided by the application have the following advantages:

[0033] 1.The buffer insertion method provided by the embodiment of the present application overcomes the problem that the existing buffer insertion technology is based on fixed topology limitation, and when the initial tree topology fails to adapt to the fan-out end polarity requirement, the algorithm is forced to insert excessive inverters to maintain the correctness of signal polarity. Specifically, the buffer insertion method performs post-order traversal on the Steiner tree, and in the process of traversing each node, a parallel solution mechanism is introduced, that is, candidate solutions with different polarities are allowed to be retained and passed at each branch node, and the logical solution space of the fixed Steiner tree is expanded through virtual branches.

[0034] Specifically, the candidate solution includes a parallel state identifier for representing a polarity state, and positive polarity solution information and negative polarity solution information. By saving the positive polarity solution information and the negative polarity solution information in the candidate solution respectively to form a parallel solution pair, a single physical wire is used to carry multiple logical polarity paths through virtual branches, and the space of the candidate solution is expanded without changing the actual wiring.

[0035] Further, all possible intermediate candidate solutions of buffer or inverter insertion are generated at the branch node, at this time, the candidate solution can be a parallel solution or a non-parallel solution, which guarantees the delay of polarity decision and reduces the insertion of redundant inverters.

[0036] Based on the intermediate candidate solution, a final candidate solution of positive polarity is generated at the root node, and the positive polarity solution with the maximum agreed arrival time is selected; all non-positive polarity solutions are converted into positive polarity solutions to ensure that the buffer / inverter insertion scheme conforms to the root node polarity. Finally, the solution with the maximum agreed arrival time is selected to maximize the timing margin under the condition of meeting the timing constraint, while ensuring that the scheme is consistent with the root node polarity.

[0037] The buffer insertion method breaks the limitation of fixed topology and realizes the consideration of signal polarity requirement and active optimization of interconnection tree structure in the buffer insertion process.

[0038] 2.The buffer insertion method provided by the embodiment of the present application, by including a parallel state identifier, positive polarity solution information and negative polarity solution information in the candidate solution, and including an agreed arrival time and a load capacitance in the positive and negative polarity solution information, enables a candidate solution to store solutions of both positive and negative polarity requirements, so that the signal polarity selection is no longer restricted by the physical wiring path. When the candidate solution is a parallel solution, the minimum value in the agreed arrival time is selected as the agreed arrival time of the overall candidate solution, which guarantees the conservativeness of timing analysis and avoids underestimating the critical path delay due to downstream path polarity conflict; further, the sum of the load capacitances of the positive polarity solution and the negative polarity solution is taken as the overall load capacitance, which provides a true capacitance benchmark for upstream node drive strength calculation.

[0039] 3. The buffer insertion method provided by the embodiment of the present application, when a side is traversed, the committed arrival time and the load capacitance of the candidate solution of the downstream node connected by the side are updated according to the candidate solution type of the downstream node connected by the side, and the updated candidate solution is transmitted to the upstream node connected by the side. The committed arrival time and the load capacitance are updated by introducing the resistance and the capacitance of the side, the interconnection line delay and the load effect are accurately quantified, a real load environment is provided for the driving capability evaluation of the upstream node, and the distortion of the downstream physical effect is avoided.

[0040] 4. The buffer insertion method provided by the embodiment of the present application, when the non-leaf node has and only has one downstream node, the candidate solution of the downstream node is maintained as the original candidate solution, a new solution is generated by inserting a buffer, a new solution is generated by inserting an inverter, and a new solution is generated by degeneration operation on the parallel solution or a new solution is generated by degeneration operation and insertion of an inverter after the degeneration operation. Through the above-mentioned generation of candidate solutions, all possible buffer or inverter insertion modes can be included in the candidate solutions, more comprehensive candidate solutions are provided for subsequent candidate solution selection, and buffer or inverter insertion schemes are avoided.

[0041] 5. The buffer insertion method provided by the embodiment of the present application, when the non-leaf node is a root node, the generated new candidate solution is traversed to find all non-positive polarity solutions. When the candidate solution is a negative polarity solution, an inverter is inserted to reverse the polarity, or when the candidate solution is a parallel solution, the parallel solution is degenerated into a positive polarity solution through degeneration operation. Through the conversion of the non-positive polarity solution into the positive polarity solution, it can be ensured that the output candidate solution conforms to the root node polarity, the conflict between the root node output signal polarity and the global driving circuit demand is avoided, and the logic function error or timing collapse caused by the polarity mismatch is prevented.

[0042] 6. The buffer insertion method provided by the embodiment of the present application, when the non-leaf node has double downstream nodes, the double downstream nodes are merged through a branch solution merging algorithm, and the merged positive polarity solution and / or negative polarity solution and / or parallel solution is inserted into a buffer to obtain all possible candidate solutions of the inserted buffer and inverter. Through the branch solution merging algorithm, the candidate solutions of the two downstream nodes are combined in a permutation and combination manner, it is ensured that all candidate solutions of the two downstream nodes and the insertion schemes of the possible inverters are merged, buffers are inserted on the basis of the merged solutions, more comprehensive candidate solutions are provided, and buffer or inverter insertion schemes are avoided.

[0043] 7. The buffer insertion method provided by the embodiment of the present application, the parallel solution pair is degenerated into a positive polarity solution or a negative polarity solution through degeneration operation, and the parallel solution pair is merged into a same polarity solution, so that the candidate solutions of the subsequent double downstream branch nodes are conveniently merged.

[0044] 8. The buffer insertion method provided by the embodiment of the present application, by deleting the inferior candidate solutions with the arrival time less than or equal to other candidate solutions and the load capacitance greater than or equal to other candidate solutions in the candidate solution list, the inferior candidate solutions are deleted in advance before traversing to the upstream node, the calculation complexity of the candidate solutions in the transmission and merging process is significantly reduced, and the implementation efficiency of the buffer insertion method is greatly improved.

[0045] 9. The embodiment of the present application further provides a buffer insertion system, the system comprising a user terminal and a micro service terminal in communication connection; the micro service terminal receives a to-be-processed command input by the user terminal, and executes the steps of the above buffer insertion method according to the to-be-processed command.

[0046] It should be noted that the buffer insertion system provided by the present application has the same beneficial effects as the above buffer insertion method, which will not be repeated here.

[0047] 10. The embodiment of the present application further provides a computer device, comprising a storage, a processor and a computer program stored on the storage, the processor executes the computer program to realize the steps of the above buffer insertion method.

[0048] It should be noted that the computer device provided by the present application has the same beneficial effects as the above buffer insertion method, which will not be repeated here.

[0049] 11. The embodiment of the present application further provides a computer readable storage medium, which stores a computer program, the computer program realizes the steps of the above buffer insertion method when executed by a processor.

[0050] It should be noted that the computer readable storage medium provided by the present application has the same beneficial effects as the above buffer insertion method, which will not be repeated here.

[0051] 12. The embodiment of the present application further provides a computer program product, comprising a computer program, the computer program realizes the steps of the above buffer insertion method when executed by a processor.

[0052] It should be noted that the computer program product provided by the present application has the same beneficial effects as the above buffer insertion method, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0054] Figure 1 is the overall flowchart of the van Ginneken algorithm in the prior art.

[0055] Figure 2 is the buffer insertion scheme effect diagram of the non-polar-aware interconnection tree in the prior art.

[0056] Figure 3 is one of the buffer insertion scheme effect diagrams finally output by the buffer insertion method provided by the present application.

[0057] Figure 4 is the flowchart of steps S1 to S6 in the buffer insertion method provided by the embodiment of the present application.

[0058] Figure 5 is the flowchart of the non-leaf node generating a new candidate solution in the buffer insertion method provided by the embodiment of the present application.

[0059] Figure 6 is the flowchart of steps S31 and S51 in the buffer insertion method provided by the embodiment of the present application.

[0060] Figure 7 is the overall flowchart of the buffer insertion method provided by the embodiment of the present application.

[0061] Figure 8 is the framework diagram of the buffer insertion system provided by the embodiment of the present application.

[0062] Figure 9 is the framework diagram of the computer device provided by the embodiment of the present application.

[0063] Figure 10 is the framework diagram of the computer readable storage medium provided by the embodiment of the present application.

[0064] Figure 11 is the framework diagram of the computer program product provided by the embodiment of the present application.

[0065] Explanation of the attached drawings:

[0066] 1. Buffer insertion system; 11. User end; 12. Micro-service end;

[0067] 2. Computer device; 21. Storage; 22. Processor;

[0068] 3. Computer readable storage medium;

[0069] 4. Computer program product;

[0070] 100. Computer program. DETAILED DESCRIPTION

[0071] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present application and should not be used to limit the present application.

[0072] In the embodiments provided by the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0073] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure or characteristic related to the embodiment is included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0074] In various embodiments of the present application, it should be understood that the size of the serial number of the above processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0075] In the flowcharts and block diagrams of the drawings of the present application, the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present application are illustrated. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code containing one or more executable instructions for implementing a specified logic function. It should also be noted that in some alternative implementations, the functions indicated in the blocks can also occur in a different order from that indicated in the drawings. For example, two blocks indicated in succession can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, based on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for executing the specified functions or operations, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0076] First, please refer to Figure 1In the prior art, in order to realize the buffer insertion to optimize the interconnection line delay, a dynamic programming algorithm is proposed by van Ginneken et al. The algorithm aims to find the optimal buffer and inverter insertion position by dynamic programming to minimize the interconnection line delay under the given interconnection line topology, usually a fixed Steiner tree.

[0077] In the van Ginneken algorithm, a fixed Steiner tree topology is usually provided, and a post-order traversal is performed on the Steiner tree.

[0078] When a leaf node is traversed, an initial candidate solution is created, wherein the initial candidate solution includes the committed arrival time and the load capacitance of the leaf node.

[0079] When an edge is traversed, the candidate solution list of the child node is propagated along the wire, and the effect of the resistance-capacitance delay and the capacitance on the committed arrival time and the load capacitance is considered.

[0080] When a non-leaf node is traversed, the possibility of inserting a buffer or an inverter at the node is considered. For each candidate solution of the current node, each possible buffer and / or inverter in the library is tried to be inserted. At this time, the insertion operation changes the load capacitance and the committed arrival time, and if an inverter is inserted, the signal polarity is changed; wherein the candidate solution of the current node is from the result of the propagation of its child nodes. The new candidate solution after inserting all possible combinations of buffers or inverters is generated and added to the candidate solution list of the current node.

[0081] Pruning rules are applied to remove candidate solutions that are inferior to other solutions in terms of delay and load capacitance, so as to control the size of the solution space.

[0082] Finally, a set of candidate solutions is obtained at the root node, and the solution that meets the constraints and has the optimal delay is selected as the final scheme.

[0083] Although the van Ginneken algorithm is very effective in optimizing pure delay, it strictly depends on the design of the fixed input Steiner tree topology, which leads to a significant defect in practical application: unable to perceive the polarity requirement of the fan-out end.

[0084] Please refer to Figure 2 Since the van Ginneken algorithm does not participate in the construction of the initial Steiner tree, and the generation process of the tree is usually independent of the subsequent buffer insertion, and the specific requirements of each fan-out end for the signal polarity are not considered, it is a "non-polarity-aware" tree. In the case of complex polarity requirements of the fan-out end, such as the existence of fan-out ends requiring positive and negative signals under a driving source, in order to meet the polarity requirements of all fan-out ends, the algorithm is often forced to insert multiple or even redundant inverters on different branches of the tree to passively correct the polarity.

[0085] This passive compensation mechanism can cause excessive insertion of inverters, which can directly degrade the timing margin of the critical path due to the inherent delay of the inverters and the additional wiring load, and the redundant inverters significantly increase the cell area overhead, exacerbating wiring congestion and power consumption.

[0086] To solve the problem that the existing buffer insertion technology is based on a fixed topology and cannot adapt to the polarity requirements of fan-out ends, and is prone to forced insertion of excessive inverters to maintain the correctness of signal polarity, the present application provides a buffer insertion method, system, device, medium and product.

[0087] Please refer to Figure 3 The buffer insertion method provided by the present application can consider the signal polarity requirements during the buffer insertion process, delay the polarity decision to the upstream node, avoid premature insertion of redundant inverters, and reduce the area used for physical design.

[0088] The buffer insertion method, system, device, medium and product provided by the present application will be described below.

[0089] Please refer to Figure 4 The buffer insertion method provided by the present application comprises the following steps:

[0090] S1: input the initial Steiner tree, the polarity requirement list of the leaf node and the design constraint file; perform post-order traversal on the Steiner tree.

[0091] S2: when traversing to the leaf node, obtain the polarity requirement of the leaf node, and obtain the committed arrival time and load capacitance of the leaf node from the design constraint file to generate an initial candidate solution.

[0092] S3: when traversing to the branch node, generate all possible candidate solutions of inserting buffers or inverters according to the candidate solution types of the downstream nodes, and update the committed arrival time and load capacitance corresponding to each candidate solution to generate intermediate candidate solutions and add them to the candidate solution list of the branch node.

[0093] S4: when traversing to the root node, generate all possible candidate solutions of inserting buffers or inverters according to the candidate solution types of the downstream branch nodes, and update the committed arrival time and load capacitance corresponding to each candidate solution.

[0094] S5: convert all non-positive polarity solutions in the newly generated candidate solutions into positive polarity solutions, and generate the final candidate solutions from the original positive polarity solutions and the converted positive polarity solutions, and add the final candidate solutions to the candidate solution list of the root node.

[0095] S6: selecting the positive polarity solution with the maximum arrival time from the candidate solution list of the root node, backtracking along the generation path of the positive polarity solution, extracting the insertion positions of the buffers and inverters recorded in the path, and outputting the buffer insertion scheme.

[0096] Specifically, in the above steps, the generated candidate solution includes a parallel state identifier for representing the polarity state of the candidate solution, and positive polarity solution information and negative polarity solution information. The candidate solution can contain the positive polarity solution information and the negative polarity solution information simultaneously or individually, and the state of the candidate solution is defined as the positive polarity solution, the negative polarity solution, or the parallel solution through the parallel state identifier.

[0097] Understandably, the buffer insertion method provided by the embodiment of the present application overcomes the problem that the existing buffer insertion technology is limited by fixed topology, and when the initial tree topology fails to adapt to the polarity requirement of the fan-out end, the algorithm is forced to insert excessive inverters to maintain the correctness of the signal polarity. Specifically, the Steiner tree is postorder traversed, and candidate solutions are generated in the process of traversing each node. The positive polarity solution information and the negative polarity solution information of the candidate solution coexist, and the state of the candidate solution is defined by a parallel state identifier. The present application allows the candidate solutions with different polarities to be retained and passed at each branch node, and through the parallel candidate solutions, a virtual branch is constructed on the basis of the original polarity solution of the node by storing another polarity solution. The virtual branch realizes that a single physical wire carries multiple logical polarity paths, and the space of the candidate solution is expanded without changing the actual wiring.

[0098] Further, all possible intermediate candidate solutions of buffer or inverter insertion are generated at the branch node. At this time, the candidate solution can be a parallel solution or a non-parallel solution, which ensures the delay of the polarity decision and reduces the insertion of redundant inverters.

[0099] Based on the intermediate candidate solution, the final candidate solution with the positive polarity is generated at the root node, and the positive polarity solution with the maximum arrival time is selected. The non-positive polarity solution is all converted into a positive polarity solution, so as to ensure that the buffer / inverter insertion scheme meets the polarity of the root node. Finally, the solution with the maximum arrival time is selected, the timing margin is maximized under the condition of meeting the timing constraint, and the output buffer insertion scheme is ensured to be consistent with the polarity of the root node.

[0100] The buffer insertion method breaks the limitation of fixed topology and realizes the consideration of the signal polarity requirement and the active optimization of the interconnection tree structure in the buffer insertion process.

[0101] The specific steps S1 to S6 of the buffer insertion method will be described below.

[0102] First, in step S1, the initial Steiner tree, the polarity requirement list of the leaf node, and the design constraint file are input, and the Steiner tree is postorder traversed.

[0103] A Steiner tree is a kind of minimum network, similar to a minimum spanning tree. A minimum spanning tree is to find the shortest network among given points and edges to make all points connected. A minimum Steiner tree allows additional points to be added outside the given points to make the cost of the generated shortest network minimum.

[0104] In the physical design stage of integrated circuits, a Steiner tree is used to solve the global routing problem of signal lines. It can significantly reduce the total length of routing, reduce signal delay and power consumption, and optimize the utilization of chip area by introducing additional "Steiner points" to build the shortest connected network among multiple pins that need to be connected, and is a key tool to balance routing efficiency and performance.

[0105] Further, the polarity requirement list of the input leaf nodes is inputted to obtain the polarity requirement of each leaf node in each Steiner tree, and to prepare for creating an initial candidate solution for the leaf nodes in the subsequent step. Similarly, the design constraint file is inputted to obtain the scheduled arrival time and load capacitance of each leaf node in the subsequent step.

[0106] It should be noted that the design constraint file includes but is not limited to a timing constraint file, a standard parasitic parameter extraction file, and a process library file. Among them, the timing constraint file is used to describe the timing constraint conditions of each signal, including clock constraints, input and output delay constraints, and timing requirements between signals. The standard parasitic parameter extraction file contains parasitic information of the design, such as resistance value, capacitance value, etc. The process library provides LEF files of standard cells, IO, and macro cells, which contain corresponding physical information such as shape, PIN position, direction performance, etc., for cell layout and routing.

[0107] And post-order traversal is performed on the input initial Steiner tree, that is, leaf nodes to root nodes are traversed. It should be noted that the Steiner tree includes leaf nodes and non-leaf nodes, wherein the non-leaf nodes include branch nodes and root nodes.

[0108] Secondly, in step S2, when the leaf node is traversed, the polarity requirement of the leaf node is obtained from the polarity requirement list of the leaf node, and the scheduled arrival time and load capacitance of the leaf node are obtained from the design constraint file to generate an initial candidate solution.

[0109] It should be noted that the signal starts to transmit from the starting point of the timing path and is required to arrive at the end point before a certain time point, which is the scheduled arrival time. If the actual delay makes the signal arrival time greater than the scheduled arrival time, the timing is violated.

[0110] In the embodiments of the present application, the latest time at which the signal must leave the node on the timing path to all downstream fan-out receiving ends of the node is the agreed arrival time. In this way, it can be ensured that the signal can finally meet the timing requirements of all downstream fan-out receiving ends after passing through the interconnect lines and logic units downstream. Specifically, the agreed arrival time of the leaf node is determined by the timing constraint.

[0111] The load capacitance refers to the total capacitance of all downstream circuits driven by the node. Specifically, the load capacitance of the leaf node is the input capacitance of itself.

[0112] Based on the acquired polarity requirement, agreed arrival time and load capacitance of the leaf node, an initial candidate solution is generated.

[0113] The candidate solution represents a possible buffer insertion configuration from the node to all receiving points in its sub-tree, wherein the initial candidate solution of the leaf node does not insert any buffer or inverter.

[0114] The candidate solution includes parallel state identifier, positive polarity solution information and negative polarity solution information. The parallel state identifier is used to indicate whether the candidate solution is a positive polarity solution, a negative polarity solution or a parallel solution. The positive polarity solution information and the negative polarity solution information respectively contain the agreed arrival time and the load capacitance of the node when the candidate solution is a positive polarity solution or a negative polarity solution.

[0115] When the parallel state identifier of the candidate solution is true, the positive polarity solution information and the negative polarity solution information both contain the corresponding agreed arrival time and load capacitance, and the candidate solution at this time is a parallel solution pair. At this time, the agreed arrival time of the entire candidate solution is the minimum value of the agreed arrival times of the positive polarity solution and the negative polarity solution, and the load capacitance of the entire candidate solution is the sum of the load capacitances of the positive polarity solution and the negative polarity solution.

[0116] When the parallel state identifier of the candidate solution is false, the positive polarity solution information and the negative polarity solution information are non-empty and only one of them contains the corresponding agreed arrival time and load capacitance. When the positive polarity solution information is non-empty, the candidate solution is a positive polarity solution; when the negative polarity solution information is non-empty, the candidate solution is a negative polarity solution. At this time, the agreed arrival time and the load capacitance of the entire candidate solution are the agreed arrival time and the load capacitance of the corresponding polarity solution.

[0117] It can be understood that the initial candidate solution of the leaf node is created as a positive polarity solution or a negative polarity solution based on its own polarity requirement.

[0118] By including the parallel state identifier, the positive polarity solution information and the negative polarity solution information in the candidate solution, and including the agreed arrival time and the load capacitance in the positive polarity solution information and the negative polarity solution information respectively, a candidate solution can store the solutions of both positive and negative polarity requirements at the same time, and the signal polarity selection is not restricted by the physical wiring path.

[0119] In step S3, the leaf node continues to traverse upwards to the branch node, when traversing to the branch node, all possible candidate solutions of the buffer or inverter are generated according to the candidate solution type of the downstream node of the branch node, and the committed arrival time and load capacitance corresponding to each candidate solution are updated, and the intermediate candidate solution is generated and added to the candidate solution list of the branch node.

[0120] Please refer to Figure 5 When the branch node has and only has one downstream node, at least one of the following operations on the candidate solution of the downstream node can be selected to generate a new candidate solution:

[0121] No buffer or inverter is inserted, and the original candidate solution is maintained and transmitted to the branch node as its new candidate solution. At this time, the committed arrival time and load capacitance of the new candidate solution are maintained unchanged.

[0122] A buffer is inserted in the candidate solution, the original candidate solution is maintained, and a new candidate solution is generated. At this time, the committed arrival time of the new candidate solution is updated as the difference between the committed arrival time of the original candidate solution and the inherent delay of the buffer, and the load capacitance of the new candidate solution is updated as the input capacitance of the buffer.

[0123] The update formula of the committed arrival time is:

[0124]

[0125] The update formula of the load capacitance is:

[0126]

[0127] Wherein, node u is the downstream node of node v, Q(v) is the committed arrival time of node v, Q(u) is the committed arrival time of node u, Q_Delay(buf) is the inherent delay of the buffer or inverter, which is a function related to the output load capacitance and input signal conversion time, and is usually obtained by querying the nonlinear delay model in the standard cell library. In order to simplify the calculation, a typical input conversion time can be used for query.

[0128] C(v) is the load capacitance of node v, and C(buf) is the input capacitance of the buffer or inverter.

[0129] An inverter is inserted in the candidate solution, the original candidate solution is inverted, and a new candidate solution is generated. At this time, the committed arrival time of the new candidate solution is updated as the difference between the committed arrival time of the original candidate solution and the inherent delay of the inverter, and the load capacitance of the new candidate solution is updated as the input capacitance of the inverter.

[0130] Further, when the candidate solution is a parallel solution, no buffer or inverter is inserted, and the original candidate solution is maintained and transmitted to the branch node as its new candidate solution.

[0131] Or, the parallel solution is degenerated into a single polarity solution by a degeneration operation, and a new candidate solution is generated.

[0132] Or, when the parallel solution is degenerated into a single polarity solution by a degeneration operation, an inverter is inserted to invert the single polarity solution from the original polarity to another polarity, and a new candidate solution is generated.

[0133] It should be noted that the degeneration operation includes the following steps T1-T3:

[0134] Step T1: Extracting the positive polarity solution or the negative polarity solution of the parallel solution pair.

[0135] Step T2: Inserting an inverter to generate a negative polarity solution for a positive polarity solution, or inserting an inverter to generate a positive polarity solution for a negative polarity solution.

[0136] Step T3: Merging the same polarity solutions.

[0137] The degeneration operation can degenerate the original parallel solution pair into a single polarity solution.

[0138] Further, in step T3, when the same polarity solutions are merged to generate a new candidate solution, the overall agreed arrival time of the new candidate solution is the minimum of the agreed arrival times of the two same polarity solutions, and the overall load capacitance is the sum of the load capacitances of the two same polarity solutions.

[0139] Through the above operation, a plurality of new candidate solutions are generated as intermediate candidate solutions and added to the candidate solution list of the branch node. At this time, each intermediate candidate solution in the selection solution list represents a possible buffer and / or inverter insertion configuration from the branch node to all receiving nodes in its sub-tree.

[0140] When the branch node has two downstream nodes, the candidate solutions of the double downstream nodes are merged by a branch solution merging algorithm, wherein the branch solution merging algorithm includes at least one of the following operations:

[0141] Merging the same polarity solutions in the candidate solutions of the two downstream nodes to generate a new candidate solution. At this time, the agreed arrival time and the load capacitance corresponding to the merged same polarity solutions are also updated based on the updating method of step T3 of the above degeneration operation.

[0142] After degenerating the candidate solution of the first downstream node into a single polarity solution by a degeneration operation, it is merged with the candidate solution of the second downstream node.

[0143] After degenerating the candidate solutions of the two downstream nodes into single polarity solutions by a degeneration operation, they are merged.

[0144] After degenerating the first downstream node into a single polarity solution by a degeneration operation, an inverter is inserted and merged with the candidate solution of the second downstream node.

[0145] For the convenience of understanding, the following basic operators are defined in advance for the branch solution merging algorithm:

[0146] Operator A: for a single polarity solution, place a buffer or inverter to generate a new solution;

[0147] Operator B: for a certain parallel solution pair, take out the positive polarity solution;

[0148] Operator C: for a certain parallel solution pair, take out the negative polarity solution;

[0149] Operator D: combine a positive polarity solution and a negative polarity solution to form a parallel solution pair;

[0150] Operator E: merge two solutions with the same polarity;

[0151] Based on the above basic operators, the operator B+C+A+E is defined as the Deparallel operator, i.e. the degeneration operation.

[0152] Operator Deparallel: for a certain parallel solution pair, place an inverter to make it merge into a single polarity solution.

[0153] Define the first downstream node as Left and the second downstream node as Right, take the positive polarity solution pair B(Left) = Left+ and the negative polarity solution pair C(Left) = Left- of the first downstream node, and take the positive polarity solution pair B(Right) = Right+ and the negative polarity solution pair C(Right) = Right- of the second downstream node;

[0154] According to the operators of the branch solution merging algorithm, the candidate solutions of the first downstream node and the second downstream node can be merged into the following 15 new solution pairs:

[0155] Solution pair 1: merge the positive and negative polarity solutions of the candidate solutions of the two branch nodes respectively to generate a new solution D(E(Left+, Right+), E(Left-, Right-));

[0156] Solution pair 2: degenerate the candidate solution of the first downstream node to the negative polarity, and merge it with the candidate solution of the second downstream node to generate a new solution D(Right+, E(Right-, Deparallel(Left)));

[0157] Solution pair 3: degenerate the candidate solution of the first downstream node to the positive polarity, and merge it with the candidate solution of the second downstream node to generate a new solution D(Right-, E(Right+, Deparallel(Left)));

[0158] Solution pair 4: Degenerate the candidate solution of the second downstream node to the negative polarity, combine with the candidate solution of the first downstream node, resulting in a new solution D(Left+, E(Left-, Deparallel(Right)));

[0159] Solution pair 5: Degenerate the candidate solution of the second downstream node to the positive polarity, combine with the candidate solution of the first downstream node, resulting in a new solution D(Left-, E(Left+, Deparallel(Right)));

[0160] Solution pair 6: Degenerate the candidate solution of the first downstream node to the negative polarity, degenerate the candidate solution of the second downstream node to the positive polarity, combine, resulting in a new solution D(Deparallel(Left), Deparallel(Right));

[0161] Solution pair 7: Degenerate the candidate solution of the first downstream node to the positive polarity, degenerate the candidate solution of the second downstream node to the negative polarity, combine, resulting in a new solution D(Deparallel(Left), Deparallel(Right));

[0162] Solution pair 8: Degenerate the candidate solution of the first downstream node to the negative polarity, insert an inverter, combine with the candidate solution of the second downstream node, resulting in a new solution D(Right-, E(Right+, A(Deparallel(Left))));

[0163] Solution pair 9: Degenerate the candidate solution of the first downstream node to the positive polarity, insert an inverter, combine with the candidate solution of the second downstream node, resulting in a new solution D(Right+, E(Right-, A(Deparallel(Left))));

[0164] Solution pair 10: Degenerate the candidate solution of the second downstream node to the negative polarity, insert an inverter, combine with the candidate solution of the first downstream node, resulting in a new solution D(Left-, E(A(Deparallel(Right)), Left+));

[0165] Solution pair 11: Degenerate the candidate solution of the second downstream node to the positive polarity, insert an inverter, combine with the candidate solution of the first downstream node, resulting in a new solution D(Left+, E(A(Deparallel(Right)), Left-));

[0166] Solution pair 12: Degenerate the candidate solution of the first downstream node to the negative polarity, insert an inverter, degenerate the candidate solution of the second downstream node to the negative polarity, combine, resulting in a new solution D(A(Deparallel(Left)), Deparallel(Right));

[0167] Solution pair 13: deparallelize the candidate solution of the first downstream node to positive polarity, insert an inverter, deparallelize the candidate solution of the second downstream node to positive polarity, combine both to produce a new solution D(A(Deparallel(Left)), Deparallel(Right));

[0168] Solution pair 14: deparallelize the candidate solution of the second downstream node to negative polarity, insert an inverter, deparallelize the candidate solution of the first downstream node to negative polarity, combine both to produce a new solution D(A(Deparallel(Right)), Deparallel(Left));

[0169] Solution pair 15: deparallelize the candidate solution of the second downstream node to positive polarity, insert an inverter, deparallelize the candidate solution of the first downstream node to positive polarity, combine both to produce a new solution D(A(Deparallel(Right)), Deparallel(Left)).

[0170] Insert a buffer to all combined positive polarity solutions and / or negative polarity solutions and / or parallel solutions, to obtain all possible candidate solutions of the insertion of buffers and inverters, and add them as intermediate candidate solutions to the candidate solution list of the branch node.

[0171] It should be noted that the corresponding part of 1-15 is selected to generate a new candidate solution according to the following cases.

[0172] Case 1: If the candidate solution of the first downstream node does not contain negative polarity solution, stop generating candidate solutions 3, 7, 9, 13, 15.

[0173] Case 2: If the candidate solution of the first downstream node does not contain positive polarity solution, stop generating candidate solutions 2, 6, 8, 12, 14.

[0174] Case 3: If the candidate solution of the second downstream node does not contain negative polarity solution, stop generating candidate solutions 5, 6, 11, 13, 15.

[0175] Case 4: If the candidate solution of the second downstream node does not contain positive polarity solution, stop generating candidate solutions 4, 7, 10, 12, 14.

[0176] Merge the double downstream nodes by the branch solution merging algorithm, and insert a buffer to the merged positive polarity solution and / or negative polarity solution and / or parallel solution to obtain all possible candidate solutions of the insertion of buffers and inverters.

[0177] The branch decomposition and combination algorithm is used to combine the candidate solutions of the two downstream nodes in a permutation and combination manner, so that all candidate solutions of the two downstream nodes and the insertion scheme of the possible inverters are combined. And based on the combined solutions, buffers are inserted to provide more comprehensive candidate solutions and avoid missing buffer or inverter insertion schemes.

[0178] In some embodiments, when a node is traversed, the committed arrival time and load capacitance of the candidate solution of the downstream node are updated according to the type of the candidate solution of the downstream node connected by the edge, and the updated candidate solution is passed to the upstream node connected by the edge.

[0179] The update formula of the committed arrival time is:

[0180]

[0181] The update formula of the load capacitance is:

[0182]

[0183] The edge is connected by node u and node v, node u is the downstream node of node v, Q(v) is the committed arrival time of node v, Q(u) is the committed arrival time of node u, C(v) is the load capacitance of node v, C(u) is the load capacitance of node u, unit_r is the resistance of the unit length conductor, unit_c is the capacitance of the unit length conductor, and l is the edge length of the edge.

[0184] When the candidate solution of node u is a single polarity solution, the committed arrival time and load capacitance of the corresponding polarity solution of node u are updated by the update formula to generate a new candidate solution and pass it to node v.

[0185] When the candidate solution of node u is a parallel solution, the update formula is applied to the positive and negative polarity solutions of node u respectively to obtain the committed arrival time and load capacitance corresponding to the positive and negative polarity solutions respectively, and a new candidate solution is generated and passed to node v.

[0186] By introducing the resistance and capacitance of the edge to update the committed arrival time and load capacitance, the interconnection line delay and load effect are accurately quantified, a real load environment is provided for the driving capability evaluation of the upstream node, and the distortion of the downstream physical effect is avoided.

[0187] When the candidate solution inserts a buffer or an inverter, the committed arrival time and load capacitance of the candidate solution can also be updated based on the following formula:

[0188] The update formula of the committed arrival time is:

[0189]

[0190] The update formula of the load capacitance is:

[0191]

[0192] wherein, node u is a downstream node of node v, Q(v) is the committed arrival time of node v, Q(u) is the committed arrival time of node u, Q_Delay(buf) is the inherent delay of the buffer or inverter, which is a function related to the output load capacitance and input signal conversion time, and is usually obtained by querying the nonlinear delay model in the standard cell library. For simplicity of calculation, a typical input conversion time can be defaulted for querying.

[0193] C(v) is the load capacitance of node v, and C(buf) is the input capacitance of the buffer or inverter.

[0194] In step S4, when the root node is traversed, all possible candidate solutions of inserting buffers or inverters are generated according to the candidate solution types of the downstream branch nodes. The steps of generating all possible candidate solutions of the root node are consistent with those of the branch nodes, and thus will not be described herein.

[0195] In step S5, all non-positive polarity solutions in the candidate solutions newly generated in step S4 are converted into positive polarity solutions, and the original positive polarity solutions and the converted positive polarity solutions are collectively generated into final candidate solutions, which are added to the candidate solution list of the root node.

[0196] wherein, when the candidate solution is a negative polarity solution, an inverter is inserted to invert the polarity to generate a positive polarity solution. Or, when the candidate solution is a parallel solution, the parallel solution is degenerated into a positive polarity solution through degeneration operation.

[0197] By uniformly converting the non-positive polarity solutions into positive polarity solutions, it is ensured that the signal polarity output by the root node meets the requirements of the global driving circuit, thereby avoiding logic function errors or timing problems caused by polarity mismatch.

[0198] In step S6, the positive polarity solution with the maximum committed arrival time is selected from the candidate solution list of the root node, the insertion positions of the buffers and inverters recorded in the generation path of the positive polarity solution are extracted in the direction of backtracking, and the insertion scheme of the buffer is output.

[0199] It should be noted that the positive polarity solution with the maximum committed arrival time maximizes the timing margin under the premise of meeting the timing constraints, provides additional timing fault tolerance, and improves the reliability of the circuit.

[0200] It can be understood that after selecting the positive polarity solution with the largest convention arrival time in the candidate solution list of the root node, the process of backtracking the buffer and inverter insertion position is as follows: during the process of Steiner tree traversal and candidate solution generation, whenever a new candidate solution is generated, its source and the type of operation performed are recorded, and the entire solution space essentially constitutes a decision tree. When backtracking, starting from the selected root node optimal solution, the parent node pointer is traversed in reverse to the leaf node. According to the operation information recorded at each node, that is, whether a buffer or inverter is inserted at the node, all insertion actions and specific positions taken to achieve the optimal solution can be restored, and the complete buffer insertion scheme is finally output.

[0201] The buffer insertion scheme generated according to the above steps is traversed through a bottom-up dynamic programming process, and parallel candidate solutions are introduced, allowing candidate solutions with different polarities to be retained and passed at branch nodes, expanding the connection resources of the traditional fixed Steiner tree through virtual branch expansion, and eliminating the parallel state of parallel solutions at subsequent nodes through a branch solution merging algorithm. This method can globally optimize the polarity allocation and timing path, significantly improving the optimization capability for fan-out end polarity inconsistency scenarios.

[0202] The steps of the buffer insertion method provided by the embodiments of the present application solve the technical problem that the existing buffer insertion technology is based on fixed topology and cannot adapt to the polarity requirements of fan-out ends, and is prone to forcibly inserting excessive inverters to maintain signal polarity correctness.

[0203] Further, please refer to Figure 6 In some embodiments, after steps S3 and S5 are performed, the following steps are also performed:

[0204] After generating the intermediate candidate solution in step S3, step S31 is performed: in the candidate solution list, delete the inferior candidate solution whose convention arrival time is less than or equal to that of other candidate solutions and whose load capacitance is greater than or equal to that of other candidate solutions.

[0205] After generating the final candidate solution in step S5, step S51 is performed: in the candidate solution list, delete the inferior candidate solution whose convention arrival time is less than or equal to that of other candidate solutions.

[0206] Steps S31 and S51 are actually processes of pruning the generated candidate solutions. Before traversing to the upstream node, the inferior candidate solutions are deleted in advance to control the size of the candidate solution space, significantly reducing the computational complexity of the candidate solutions in the transmission and merging process, thereby greatly improving the overall execution efficiency of the buffer insertion method.

[0207] Please refer to Figure 7The buffer insertion method is used for traversing the Steiner tree from bottom to top, and a parallel candidate solution mechanism is introduced. Further, a branch solution merging algorithm is performed according to the candidate solutions of the downstream branch nodes of each node to generate a new candidate solution. Finally, the candidate solution with the maximum arrival time is selected as the optimal solution at the root node, and the optimal solution is backtracked to obtain the insertion positions of the buffers and inverters, so as to output the buffer insertion scheme.

[0208] The buffer insertion method introduces the parallel candidate solution mechanism, effectively solves the excessive inverter insertion problem caused by the fixed topology and polarity mismatch in the traditional algorithm. The branch solution merging algorithm is used at the non-leaf nodes to significantly expand the range of the candidate solution space, so that the best balance between timing and area can be achieved under the premise of meeting the polarity requirements of each receiving end. Finally, the positive polarity solution with the maximum timing margin is selected at the root node, and the insertion scheme is output through the backtracking mechanism, which significantly reduces the area overhead and power consumption.

[0209] Referring to Figure 8 The buffer insertion system 1 provided by the embodiment of the present application comprises a user end 11 and a micro-service end 12 which are communicatively connected. The micro-service end 12 receives a to-be-processed command input by the user end 11, and executes the steps of the buffer insertion method according to the to-be-processed command.

[0210] It can be understood that the micro-service end 12 is responsible for executing the steps of the buffer insertion method. After executing the related steps, the micro-service end 12 outputs a preset command which is uniquely matched with the to-be-processed command to the user end 11. After receiving the preset command, the user end 11 submits the preset command to an interpreter for verification and analysis, and finally the buffer insertion system 1 is executed by the integrated circuit design software.

[0211] It should be noted that the buffer insertion method provided by the foregoing embodiment is implemented by using the buffer insertion system 1 based on micro-service. The micro-service is to separate the single-function module unit from the original, comprehensive monolithic application, so that the original software architecture is clearer and simpler, and the function of the single module unit can be updated, maintained and further improved.

[0212] Specifically, the buffer insertion system 1 of the embodiment of the present application separates the buffer insertion function in the integrated circuit design software to form the micro-service end 12. Through this design, a person skilled in the art or a user skilled in the integrated circuit design software only needs to deploy a set of micro-service for buffer insertion in advance, and then can request the micro-service on different versions of the integrated circuit design software within the local area network, so as to realize the buffer insertion through the micro-service end 12 and reduce the occupation of the memory resources.

[0213] Referring to Figure 9The embodiment of the present application further provides a computer device 2, which comprises a storage 21, a processor 22 and a computer program 100 stored in the storage 21, and the processor 22 executes the computer program 100 to realize the steps of the buffer insertion method.

[0214] It can be understood that the computer device 2 provided by the embodiment of the present application can realize the buffer insertion method described in the above embodiment when the processor 22 executes the computer program 100, and the computer device 2 provided by the embodiment of the present application has the same beneficial effects as the buffer insertion method provided by the above embodiment.

[0215] In some embodiments, the computer device 2 is a computer device applied to the field of integrated circuit design software application technology, which comprises but is not limited to obtaining an initial steiner tree and a leaf node polarity demand list and a design constraint file, traversing the steiner tree from bottom to top, generating a candidate solution, merging candidate solutions, etc., which will not be described here. In theory, the method steps involved in the technical solution of the present application can be realized by participating in the control of the computer device 2, and the related parameters involved can also be adjusted by the computer device 2. The related parameters include but are not limited to preset command set and preset option set and the like.

[0216] In some embodiments, the processor 22 provided by the embodiment of the present application is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, which can realize or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0217] In some embodiments, the method steps disclosed in the embodiments of the present application can be embodied by hardware processor execution or by combination of hardware and software modules in the processor 22.

[0218] Please refer to Figure 10 The embodiment of the present application further provides a computer readable storage medium 3, which stores a computer program 100, and the computer program 100 realizes the steps of the buffer insertion method when executed by a processor.

[0219] It can be understood that the computer readable storage medium 3 provided by the embodiment of the present application stores the computer program 100, and the computer program 100 can be called by the processor to execute the buffer insertion method described in the above embodiment.

[0220] It should be noted that the computer readable storage medium 3 provided by the embodiment of the present application has the same beneficial effects as the buffer insertion method provided by the above-mentioned embodiment, which will not be repeated here.

[0221] Specifically, the computer readable storage medium 3 can include at least one type of storage medium, for example, can include flash memory, hard disk, multimedia card, card memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc.

[0222] In some embodiments, the computer readable storage medium 3 includes a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules.

[0223] Specifically, the computer readable storage medium 3 has a storage space for the computer program 100 to execute any method steps of the above-mentioned buffer insertion method, and these programs can be read from one or more computer program products or written into one or more computer program products.

[0224] In some embodiments, the computer program 100 can be compressed in a suitable form.

[0225] Please refer to Figure 11 The embodiment of the present application also provides a computer program product 4, which includes a computer program 100, and the computer program 100 realizes the steps of the above-mentioned buffer insertion when executed by a processor.

[0226] It can be understood that the computer program product 4 provided by the embodiment of the present application includes the computer program 100, and the computer program 100 can be called by the processor to execute the buffer insertion method described in the above-mentioned embodiment, which will not be repeated here.

[0227] The above-mentioned buffer insertion method, buffer insertion system, device, medium and product disclosed by the embodiment of the present application are introduced in detail, and the principle and implementation mode of the present application are described by applying specific examples in this paper. The above-mentioned embodiment is only used to help understand the method of the present application and its core idea.

[0228] At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in specific implementation mode and application range, and the above-mentioned description should not be understood as the limitation of the present application. Any modification, equivalent replacement and improvement within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A buffer insertion method characterized by, The method comprises the following steps: inputting an initial Steiner tree, a polarity requirement list of leaf nodes, and a design constraint file; performing a post-order traversal on the Steiner tree; when a leaf node is reached, obtaining the polarity requirement of the leaf node, and obtaining the scheduled arrival time and load capacitance of the leaf node from the design constraint file to generate an initial candidate solution; wherein the candidate solution comprises a parallel state identifier, positive polarity solution information, and negative polarity solution information; the parallel state identifier is used to indicate whether the candidate solution is a positive polarity solution, a negative polarity solution, or a positive-negative parallel solution; the positive polarity solution information and the negative polarity solution information respectively contain the scheduled arrival time and the load capacitance of the node when the candidate solution is a positive polarity solution or a negative polarity solution; when a non-leaf node is reached, candidate solutions of all possible buffer or inverter insertions are generated according to the candidate solution types of downstream nodes, and the scheduled arrival time and the load capacitance corresponding to each candidate solution are updated; when the non-leaf node is a branch node, intermediate candidate solutions are generated, and all the intermediate candidate solutions are added to the candidate solution list of the branch node; when the non-leaf node is a root node, all non-positive polarity solutions in the newly generated candidate solutions are converted into positive polarity solutions, and the original positive polarity solutions and the converted positive polarity solutions jointly generate a final candidate solution, which is added to the candidate solution list of the root node; a positive polarity solution with the maximum scheduled arrival time is selected from the candidate solution list of the root node, a path is backtracked along the generation path of the positive polarity solution, buffer insertion positions recorded in the path are extracted, and a buffer insertion scheme is output.

2. The buffer insertion method of claim 1, wherein: when the parallel state identifier of the candidate solution is true, the positive polarity solution information and the negative polarity solution information both contain corresponding scheduled arrival times and load capacitances, and the candidate solution at this time is a parallel solution pair; wherein the scheduled arrival time of the entire candidate solution is the minimum value of the scheduled arrival times of the positive polarity solution and the negative polarity solution, and the load capacitance of the entire candidate solution is the sum of the load capacitances of the positive polarity solution and the negative polarity solution; when the parallel state identifier of the candidate solution is false, the positive polarity solution information and the negative polarity solution information are non-empty only one of them, that is, only one contains corresponding scheduled arrival times and load capacitances; when the positive polarity solution information is non-empty, the candidate solution is a positive polarity solution; when the negative polarity solution information is non-empty, the candidate solution is a negative polarity solution; wherein the scheduled arrival time and the load capacitance of the entire candidate solution are the scheduled arrival time and the load capacitance of the corresponding polarity solution.

3. The buffer insertion method of claim 1, wherein: when an edge is reached, the scheduled arrival time and the load capacitance of the candidate solution of a downstream node connected by the edge are updated according to the candidate solution type of the downstream node, and the updated candidate solution is transmitted to an upstream node connected by the edge; wherein the scheduled arrival time update formula is: the load capacitance update formula is: nodes u and v are connected to form an edge, node u is a downstream node of node v, Q(v) is the scheduled arrival time of node v, Q(u) is the scheduled arrival time of node u, C(v) is the load capacitance of node v, C(u) is the load capacitance of node u, unit_r is the resistance of a unit length of conductor, unit_c is the capacitance of a unit length of conductor, and l is the edge length of the edge. When the candidate solution of node u is a single polarity solution, the committed arrival time and load capacitance of the polarity solution of node u are updated by the update formula to generate a new candidate solution which is transmitted to node v; When the candidate solution of node u is a parallel solution, the committed arrival time and load capacitance of the positive polarity solution and the negative polarity solution are respectively obtained by applying the update formula to the positive polarity solution and the negative polarity solution of node u respectively to generate a new candidate solution which is transmitted to node v.

4. The buffer insertion method of claim 1, wherein: when the non-leaf node has only one downstream node, a new candidate solution is generated by at least one of the following operations on the candidate solution of the downstream node: no buffer or inverter is inserted, and the original candidate solution is maintained to be transmitted to the non-leaf node; a buffer is inserted to generate a new candidate solution; an inverter is inserted to generate a new candidate solution; when the candidate solution is a parallel solution, a new candidate solution is generated by a degeneration operation; or, after the degeneration operation, an inverter is inserted to generate a new candidate solution; wherein, when the candidate solution is inserted with a buffer and / or an inverter, the update formula of the committed arrival time is: the update formula of the load capacitance is: wherein, node u is a downstream node of node v, Q(v) is the committed arrival time of node v, Q(u) is the committed arrival time of node u, Q_Delay(buf) is the inherent delay of the buffer or inverter, C(v) is the load capacitance of node v, and C(buf) is the input capacitance of the buffer or inverter.

5. The buffer insertion method of claim 4, wherein: when the non-leaf node is a root node, at least one of the following operations is performed on the non-positive polarity solution in the generated new candidate solution to generate a final candidate solution: when the candidate solution is a negative polarity solution, an inverter is inserted to invert the polarity; when the candidate solution is a parallel solution, a degeneration operation is performed to degenerate the parallel solution into a positive polarity solution.

6. The buffer insertion method of claim 1, wherein: when the non-leaf node has two downstream nodes, the candidate solutions of the two downstream nodes are merged by a branch solution merging algorithm, wherein the branch solution merging algorithm includes at least one of the following operations: the same polarity solutions in the candidate solutions of the two downstream nodes are merged; the candidate solution of a first downstream node is degenerated into a single polarity solution by a degeneration operation, and then merged with the candidate solution of a second downstream node; the candidate solutions of the two downstream nodes are both degenerated into single polarity solutions by degeneration operations, and then merged; the candidate solution of the first downstream node is degenerated into a single polarity solution by a degeneration operation, and then an inverter is inserted, and the degenerated solution is merged with the candidate solution of the second downstream node; all the merged positive polarity solutions and / or negative polarity solutions and / or parallel solutions are inserted with buffers to obtain all the possible candidate solutions of the inserted buffers and inverters.

7. The buffer insertion method of any one of claims 4-6, wherein: the degeneration operation includes the following steps: a positive polarity solution or a negative polarity solution of a parallel solution pair is extracted; an inverter is inserted to generate a negative polarity solution from the positive polarity solution, or an inverter is inserted to generate a positive polarity solution from the negative polarity solution; the same polarity solutions are merged.

8. The buffer insertion method of claim 1, wherein: When the non-leaf node is traversed, after generating all possible candidate solutions and adding them to the candidate solution list, the following steps are further included: In the candidate solution list, delete the inferior candidate solution whose scheduled arrival time is less than or equal to that of other candidate solutions and whose load capacity is greater than or equal to that of other candidate solutions. Or, only delete the inferior candidate solution whose scheduled arrival time is less than or equal to that of other candidate solutions.

9. A buffer insertion system, characterized in that: The buffer insertion system comprises a user terminal and a micro-service terminal connected in communication; The micro-service terminal receives the inputted to-be-processed command of the user terminal, and executes the steps of the buffer insertion method according to any one of claims 1-8.

10. A computer device comprising a storage, a processor and a computer program stored on the storage, characterized in that, The processor executes the computer program to implement the steps of the buffer insertion method according to any one of claims 1-8.

11. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the buffer insertion method according to any one of claims 1-8.

12. A computer program product comprising a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the buffer insertion method according to any one of claims 1-8. The computer program, when executed by the processor, implements the steps of the buffer insertion method according to any one of claims 1-8.

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