Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof. In a semiconductor device having a semiconductor substrate, an insulating layer on the semiconductor substrate, and a wiring layer on the insulating layer, a first main element is provided on the semiconductor substrate and has a first gate electrode insulated from the semiconductor substrate; a first gate contact plug contacts the first gate electrode from the wiring layer; a first diode is provided on each of a plurality of sites surrounding a site directly below the first gate contact plug in the semiconductor substrate; and a plurality of first diode contact plugs contact each of the first diodes from the wiring layer.

Description

TECHNICAL FIELD

[0001] The present technology relates to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In the manufacturing of semiconductor devices, processes such as film formation on a semiconductor substrate, processing of a thin film on a semiconductor substrate, and the like are used. In these processes, plasma processing is used. Plasma etching, plasma CVD, and the like. In plasma processing, the processing target site is sometimes charged and deterioration based thereon occurs. Therefore, if plasma processing is used in a process of forming a hole reaching an element in a semiconductor substrate, or a process performed in a state where such a hole has been formed, it is possible that the element is affected.

[0003] To reduce such a case, a shield wiring that surrounds a high withstand voltage element and is connected to a substrate can be provided. A protection diode is connected to a gate electrode by an upper layer wiring that crosses the shield wiring. Thereby, plasma damage in a subsequent process is suppressed. SUMMARY

[0004] PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] The dummy pattern and the dummy via used in the above-described prior art do not have a particular relationship with the original circuit structure. Therefore, they do not particularly function in the use stage of the semiconductor device. The presence of a large number of such components can unnecessarily increase the overall size of the semiconductor device.

[0006] The present technology provides a semiconductor device and a manufacturing method thereof that can effectively suppress deterioration at the time of plasma processing with a configuration that does not waste.

[0007] MEANS FOR SOLVING THE PROBLEMS

[0008] To achieve the above object, in a first aspect, some embodiments of the present technology provide a semiconductor device including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a wiring layer on the insulating layer, the semiconductor device including: a first main element provided on the semiconductor substrate and having a first gate electrode insulated from the semiconductor substrate; a first gate contact plug in contact with the first gate electrode from the wiring layer; a first diode provided on a plurality of sites that surround sites directly below the first gate contact plug in the semiconductor substrate, respectively; and a plurality of first diode contact plugs in contact with each first diode from the wiring layer.

[0009] In some embodiments of the present disclosure, the semiconductor device can further include: an upper insulating layer on the wiring layer; an upper wiring layer on the upper insulating layer; a gate via plug contacting the upper wiring layer and the wiring layer on the first gate contact plug; and a diode via plug contacting the upper wiring layer and the wiring layer on the first diode contact plug.

[0010] In some embodiments of the present disclosure, at least one of the first diode contact plug and the first gate contact plug is connected by a pattern of the wiring layer.

[0011] In some embodiments of the present disclosure, the semiconductor device can further include: a second main element disposed on the semiconductor substrate and having a second gate electrode insulated from the semiconductor substrate and having a conductive type opposite to that of the first main element; a second gate contact plug contacting the wiring layer and the second gate electrode; a second diode disposed on a plurality of sites surrounding sites directly below the second gate contact plug in the semiconductor substrate and having a conductive type opposite to that of the first diode; and a plurality of second diode contact plugs contacting the wiring layer and each of the second diodes, the semiconductor substrate including: a first conductive type well including a range of a position of the first main element and a position of the first diode; a second conductive type main well including a range of a position of the second main element; a second conductive type sub well including a range of the second diode; and a first conductive type deep well including a lower portion of the first conductive type well and the second conductive type main well and excluding at least a portion of a lower portion of the second conductive type sub well. Preferably, a gap between the first gate contact plug and the first diode contact plug is 5 times or less the thickness of the first gate contact plug.

[0012] In some embodiments of the present disclosure, the semiconductor substrate includes: a second conductive type region disposed on a plurality of sites of a portion of a surface of the semiconductor substrate; a first conductive type well including a range of a position of the first main element and a position of the second conductive type region; a lower portion of the second conductive type region contacting the first conductive type well, and a contact site between the second conductive type region and the first conductive type well being the first diode.

[0013] In some embodiments of the present disclosure, a gate oxide film is disposed between the semiconductor substrate and the first gate.

[0014] In some embodiments of the present disclosure, the first main element includes a metal oxide semiconductor transistor.

[0015] In a second aspect, some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, the semiconductor device to be manufactured including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a wiring layer on the insulating layer, a main element and a diode being formed in the semiconductor substrate, the main element having a gate electrode insulated from the semiconductor substrate, in the method, a hole processing is performed on the insulating layer before the wiring layer is formed, a gate contact hole exposing the gate electrode on the side of the wiring layer and a diode contact hole exposing the diode on the side of the wiring layer are formed, after the hole processing, a build-up forming the wiring layer, a gate contact plug filling the gate contact hole, and a diode contact plug filling the diode contact hole is performed, at least one of the hole processing and the build-up includes a plasma treatment, the diodes are respectively provided on a plurality of sites surrounding sites directly below the gate contact plug in the semiconductor substrate, and in the hole processing, the diode contact hole is formed for the diodes on the plurality of sites.

[0016] In some embodiments of the present disclosure, after the build-up, an upper insulating layer on the wiring layer and an upper wiring layer on the upper insulating layer can also be formed, and before the upper wiring layer is formed, an upper hole processing is performed on the upper insulating layer, in the upper hole processing, a gate via exposing the wiring layer on the gate contact plug on the side of the upper wiring layer and a diode via exposing the wiring layer on the diode contact plug on the side of the upper wiring layer are formed, after the upper hole processing, an upper build-up forming the upper wiring layer, a gate via plug filling the gate via, and a diode via plug filling the diode via is performed, at least one of the upper hole processing and the upper build-up includes a plasma treatment, at least one of the diode contact plugs is connected to the first gate contact plug through a pattern of the wiring layer after the build-up.

[0017] The present disclosure can produce the unexpected effects that:

[0018] According to the present disclosure, a semiconductor device and a method of manufacturing the same can be provided, which can effectively suppress deterioration during plasma processing without waste. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0020] Figure 1 is a sectional view of a semiconductor device according to an embodiment.

[0021] Figure 2 is a plan view of a semiconductor device according to an embodiment.

[0022] Figure 3 It is a cross-sectional view (one) of the manufacturing process of the semiconductor device involved in the embodiment.

[0023] Figure 4 It is a graph representing the reduction in defect rate during contact processing.

[0024] Figure 5 This is a cross-sectional view (second one) of the manufacturing process of the semiconductor device involved in the implementation method.

[0025] Figure 6 It is a graph showing the reduction in defect rate during through-hole machining.

[0026] Figure 7 This is a schematic diagram illustrating the configuration relationship between the gate contact plug and the surrounding diode contact plugs.

[0027] Figure 8 It is a cross-sectional view of the semiconductor device involved in the application of CMOS.

[0028] Explanation of reference numerals in the attached figures

[0029] 1. Semiconductor device

[0030] 2 Semiconductor substrate

[0031] 3 Insulation layer

[0032] 4. Wiring layer

[0033] 5 First gate electrode

[0034] 6 N-well

[0035] 7 P+ area

[0036] 8 Gate contact plugs

[0037] 8a First gate contact plug

[0038] 9. Diode contact plug

[0039] 9a First diode contact plug

[0040] 10 Gate Via Plugs

[0041] 11 Diode via plug

[0042] 12 First main component

[0043] 13 First Diode

[0044] 14. Upper insulation layer

[0045] 15 Upper wiring layer

[0046] 16 Gate contact holes

[0047] 17 Diode contact hole

[0048] 18 Gate Vias

[0049] 19 Diode vias

[0050] 20 N deep well

[0051] 25 Second gate electrode

[0052] 26 P main well

[0053] 27 N+ regions

[0054] 28 Second gate contact plug

[0055] 29 Second Diode Contact Plug

[0056] 32 Second main component

[0057] 36 P-sub-well Detailed Implementation

[0058] The embodiments that embody the technology of this disclosure will be described. The configuration of the semiconductor device involved in this method is as follows: Figure 1 As shown. Figure 1 The semiconductor device 1 includes a semiconductor substrate 2, an insulating layer 3 on the semiconductor substrate 2, and a wiring layer 4 on the insulating layer 3. The semiconductor device 1 also includes an upper insulating layer 14 on the wiring layer 4 and an upper wiring layer 15 on the upper insulating layer 14.

[0059] Figure 1 The semiconductor in the semiconductor includes a first conductive well and a second conductive region. The first conductive well includes the location of a first main element and the range of the location of the second conductive region. The second conductive region is disposed at multiple locations on a portion of the surface of the semiconductor substrate. The lower part of the second conductive region is in contact with the first conductive well. The contact portion between the second conductive region and the first conductive well constitutes a diode. Figure 1 The semiconductor substrate 2 is P-type. An N-well 6 is formed on the semiconductor substrate 2. P+ regions 7 are formed at multiple locations on a portion of the surface of the semiconductor substrate 2. The lower part of each P+ region 7 is in contact with the N-well 6. The contact area between the P+ region 7 and the N-well 6 functions as a first diode 13.

[0060] A first gate electrode 5 is provided in the semiconductor device 1. The first gate electrode 5 constitutes part of a MOS transistor, which will be described later. The first gate electrode 5 is... Figure 1The first gate electrode 5 is depicted directly above the semiconductor substrate 2, but is actually insulated from the semiconductor substrate 2. A very thin gate oxide film exists between the semiconductor substrate 2 and the first gate electrode 5.

[0061] In the semiconductor device 1, a gate contact plug 8 and a diode contact plug 9 are provided in a manner that penetrates the insulating layer 3. The gate contact plug 8 is an electrically conductive body that contacts the wiring layer 4 and the first gate electrode 5. The gate contact plug 8 does not contact the first diode 13. The diode contact plug 9 is an electrically conductive body that contacts the wiring layer 4 and the first diode 13. The diode contact plug 9 does not contact the first gate electrode 5. In addition, the gate contact plug 8 and the diode contact plug 9 are Figure 1 the lowermost contact hole in the structure. This is because the gate contact plug 8 is directly connected to the first gate electrode 5, and the diode contact plug 9 is directly connected to the P+ region 7, which is an active region of the semiconductor substrate 2.

[0062] The semiconductor device 1 is further described using a plan view of Figure 2 . Figure 2 A plan view schematically showing the positional relationship of the first gate electrode 5, the wiring layer 4, and the contact plugs (including the gate contact plug 8 and the diode contact plug 9) formed in the semiconductor device 1 before the upper insulating layer 14 and the upper wiring layer 15 are formed is depicted in Figure 2 . In Figure 2 , the first gate electrode 5 is depicted as a long strip in the left-right direction in the figure. Both of the gate contact plugs 8 are within the range of the first gate electrode 5 in Figure 2 . That is, Figure 2 both of the gate contact plugs 8 in contact the first gate electrode 5.

[0063] Figure 2 The first gate electrode 5 in extends further (for example, to the left in the figure) than the above-mentioned two portions of the gate contact plug 8 to form a MOS transistor, which is the first main element 12 in the semiconductor device 1. The MOS transistor is constituted by the well structure in the semiconductor substrate 2 and the first gate electrode 5.

[0064] In Figure 2 , a plurality of diode contact plugs 9 are depicted. Specifically, six diode contact plugs 9 are disposed so as to surround the left gate contact plug 8 in Figure 2 , and seven diode contact plugs 9 are disposed so as to surround the right gate contact plug 8. That is, in the semiconductor device 1, the first diode 13 is provided at a plurality of portions that surround portions directly below the gate contact plug 8 in the semiconductor substrate 2.

[0065] exist Figure 2 The pattern of wiring layer 4 is also depicted. One of the plurality of diode contact plugs 9 surrounding the gate contact plug 8 is connected to the gate contact plug 8 through the pattern of wiring layer 4. The remaining diode contact plugs 9 are not connected to the gate contact plug 8 at the level of wiring layer 4.

[0066] Further explanation Figure 1 . Figure 1 The cross section shown is Figure 2 The cross-section at position A-A' in the diagram. Figure 1 The image shows one gate contact plug 8 and three diode contact plugs 9. A wiring layer 4 pattern is formed on the upper side of both the gate contact plug 8 and each diode contact plug 9. Figure 1 In this configuration, the diode contact plug 9 adjacent to the left side of the gate contact plug 8 is connected to the gate contact plug 8 via the pattern of the wiring layer 4. The patterns of the wiring layer 4 of the other diode contact plugs 9 are not connected to the patterns of the wiring layer 4 of the gate contact plug 8.

[0067] like Figure 1 As shown, in semiconductor device 1, a gate via plug 10 and a diode via plug 11 are disposed through the upper insulating layer 14. The gate via plug 10 is a conductor that contacts the wiring layer 4 on the gate contact plug 8 from the upper wiring layer 15. The diode via plug 11 is a conductor that contacts the wiring layer 4 on the diode contact plug 9 from the upper wiring layer 15.

[0068] The advantage of the semiconductor device 1 having the above-described structure lies in its manufacturing process, particularly the steps for forming the gate contact plug 8 and the diode contact plug 9. Through Figure 3 Please provide an explanation of this content. Figure 3 A cross-section is shown in the process of fabricating the gate contact plug 8 and the diode contact plug 9 in the semiconductor device 1. Figure 3 In this state, wiring layer 4, upper insulating layer 14, and upper wiring layer 15 have not yet been formed. N-well 6, P+ region 7, and first gate electrode 5 have been formed. Figure 3 The position shown is the same as Figure 1 The positions shown are the same.

[0069] exist Figure 3 The insulating layer 3 has a gate contact hole 16 and a diode contact hole 17 formed therein. The gate contact hole 16 is a hole that exposes the first gate electrode 5 on the wiring layer 4 side. The gate contact hole 16 is shaped to form a gate contact plug 8. The diode contact hole 17 is a hole that exposes the first diode 13 on the wiring layer 4 side. The diode contact hole 17 is shaped to form a diode contact plug 9. Therefore, multiple locations surrounding the gate contact hole 16 are provided.

[0070] The processes for forming the gate contact plug 8 and the diode contact plug 9 include hole fabrication and deposition. Hole fabrication is the process of forming the gate contact hole 16 and the diode contact hole 17 in the insulating layer 3. Deposition is the process of forming the wiring layer 4, the gate contact plug 8, and the diode contact plug 9 after the hole fabrication. Plasma processing can be used in these processes. For example, plasma etching can be used to process the insulating layer 3 through hole fabrication; as a process of deposition, the patterning of the wiring layer 4 can be done using plasma resist processing; and plasma CVD can be used to form the wiring layer 4, the gate contact plug 8, and the diode contact plug 9.

[0071] In plasma processing, there is a tendency for the area near the bottom of the gate contact hole 16 and the diode contact hole 17 to become positively charged. However, in this embodiment, the bottom of the diode contact hole 17 is the first diode 13. Therefore, in the diode contact hole 17, charge leaks through the first diode 13 to the semiconductor substrate 2, and hardly accumulates.

[0072] This reduces the degradation of the gate oxide film caused by so-called antenna damage. This is because, although a certain amount of charge accumulates in the gate contact hole 16, the charge generated by the plasma treatment preferentially flows into the diode contact hole 17. Furthermore, since the charge generated by the plasma treatment is a constant current, more charge flows into the diode contact hole 17, and correspondingly less charge flows into the gate contact hole 16.

[0073] The effect is as follows Figure 4 The graph is shown below. Figure 4 The vertical axis represents the defect rate (in arbitrary units) in the gate oxide film. The horizontal axis represents the antenna ratio (the ratio of the area of ​​the gate oxide film to the area of ​​the portion connected to the first gate electrode 5 and exposed to plasma). Figure 4 The graph with the solid line rising to the right is a comparative example, representing the defect rate when plasma processing is performed using only the gate contact hole 16 without the diode contact hole 17. In the comparative example, the case where a higher antenna ratio results in a higher defect rate is shown. This is because a higher antenna ratio means that the generated charge is concentrated over a larger area at the first gate electrode 5.

[0074] In contrast, the results under the same plasma processing conditions in this method are... Figure 4 The dashed line in the graph indicates that, roughly along the horizontal axis itself, the formation of defects is almost imperceptible. This is because the concentration of charge towards the first gate electrode 5 is mitigated by the diode contact hole 17. Figure 3In this state, the diode contact hole 17 is not in conduction with the first gate electrode 5. Therefore, the first diode 13 is not a protection diode in the usual sense. However, as described above, it actually functions to protect the first gate electrode 5. In this specification, it is referred to as a "dummy protection diode". Figure 3 All of the three first diodes 13 in the process of processing are dummy protection diodes.

[0075] In the case where plasma etching is used in the hole processing step, when the opening of the diode contact hole 17 in the insulating layer 3 reaches the surface of the semiconductor substrate 2, the first diode 13 functions to some extent to discharge the electric charge. When the opening of the gate contact hole 16 reaches the first gate electrode 5, the accumulation of the electric charge in the gate contact hole 16 causes the gate oxide film to rapidly deteriorate in a short time.

[0076] In Figure 3 After the state shown in FIG. 8, the wiring layer 4, the gate contact plug 8, and the diode contact plug 9 are formed. The conductive body that fills the gate contact hole 16 by the build-up is the gate contact plug 8, and the conductive body that fills the diode contact hole 17 is the diode contact plug 9. As described above, the build-up can also be plasma processing. In the wiring layer 4 with a pattern, as shown in FIG. 9, a plurality of diode contact plugs 9 are formed in a shape in which a part of each of the diode contact plugs 9 is connected to the gate contact plug 8. Figure 1

[0077] The deterioration prevention effect of the gate oxide film by the first diode 13 can also be obtained at the time of the upper layer processing. This will be described with reference to FIGS. 10 to 12. Figure 5 Figure 5 A cross section in the semiconductor device 1 in the process of processing the gate via plug 10 and the diode via plug 11 is shown in FIG. 10. In this state, the wiring layer 4 and the upper layer insulating layer 14 have been formed, but the upper layer wiring layer 15 has not been formed. Figure 5 Figure 5 The position shown in FIG. 11 is the same as the position shown in FIG. 8. Figure 1 Figure 3

[0078] In the upper layer insulating layer 14 of FIG. 11, the gate via 18 and the diode via 19 are formed. The gate via 18 is a hole that exposes the wiring layer 4 on the gate contact plug 8 to the upper layer wiring layer 15 side. The gate via 18 is in a shape for forming the gate via plug 10. The diode via 19 is a hole that exposes the wiring layer 4 on the diode contact plug 9 to the upper layer wiring layer 15 side. The diode via 19 is in a shape for forming the diode via plug 11. Figure 5

[0079] ​​​​​​The formation of the gate via plug 10 and the diode via plug 11 is also performed by the same hole processing and accumulation as described above. Hereinafter, these are referred to as upper layer hole processing and upper layer accumulation. The upper layer hole processing and upper layer accumulation also use plasma processing.

[0080] At the time of upper layer processing, the electric charges generated by plasma are also discharged through the first diode 13, and the same effect as described above is obtained. In more detail, as shown in FIG. 6, the electric charges generated by the diode via 19 reach the first diode 13 via the diode contact plug 9. Also, the electric charges generated by the gate via 18 reach the first diode 13 via the diode contact plug 9 as shown by the arrow S. This is because the gate contact plug 8 and a part of the diode contact plug 9 are connected by the pattern of the wiring layer 4. Therefore, at the time of upper layer processing, electric charges are hardly stored in the first gate electrode 5. Therefore, the deterioration prevention effect of the gate oxide film at the time of upper layer processing is higher than that at the time of lower layer processing described above. Figure 5 At the time of upper layer processing, it can be said that

[0081] of the three first diodes 13 does not function as a dummy protection diode but functions as a real protection diode. This is the first diode 13 below the diode contact plug 9 connected to the gate contact plug 8 by the wiring layer 4. That is, it is the first diode 13 below the diode contact plug 9 adjacent to the left of the gate contact plug 8 in Figure 5 Figure 5 At the time of upper layer processing, it can be said that Figure 5 of the three first diodes 13 does not function as a dummy protection diode but functions as a real protection diode. This is the first diode 13 below the diode contact plug 9 connected to the gate contact plug 8 by the wiring layer 4. That is, it is the first diode 13 below the diode contact plug 9 adjacent to the left of the gate contact plug 8 in

[0082] The effect at the time of upper layer processing will be described. Figure 6 The vertical axis of FIG. 8 is the same as that of FIG. 7. The horizontal axis is the antenna ratio, and this point is the same as that of FIG. 7, but is set to a logarithmic scale in FIG. 8. This is because the wiring layer 4 and the like have been formed at the time of upper layer processing, and sometimes the antenna ratio becomes very large. In Figure 6 In FIG. 8, the solid line rising to the right is also a comparative example, and shows the defect rate in the case where the plasma processing is performed using only the gate via 18 and the gate contact plug 8 without the diode via 19 and the diode contact plug 9. Figure 4 Figure 4 Figure 6 The dotted line below the solid line rising to the right in FIG. 8 is the result in the case of the present embodiment under the same plasma processing conditions. In Figure 6 In FIG. 8, the case where the antenna ratio is 100 or less (only dummy) and the case where the antenna ratio exceeds 100 (dummy + real) are shown separately.

[0083] Figure 6 The dotted line below the solid line rising to the right in FIG. 8 is the result in the case of the present embodiment under the same plasma processing conditions. In Figure 6

[0084] ​​​​As for the case where the antenna ratio is 100 or less, the results in the case where the pattern of the wiring layer 4 in which all the diode contact plugs 9 are not connected to the gate contact plugs 8 is used are shown. That is, the case where there is no real protection diode for all the first diodes 13 are dummy protection diodes. Even so, a case where almost no defects are generated is exhibited.

[0085] As for the case where the antenna ratio exceeds 100, the results in the case where a part of the diode contact plugs 9 are connected to the gate contact plugs 8 as shown in Figure 5 . That is, the case where not only dummy protection diodes but also real protection diodes are used. In this case, although a certain degree of defects occur in the case where the antenna ratio is extremely large, the degree of improvement in the defect rate with respect to the case of the comparative example above is very large. It is considered that this is due to the effect of the presence of the real protection diode. In the present mode, as shown in Figure 2 , the first diodes 13 can be used as the discharge path of the electric charge at the time of plasma processing. A plurality of first diodes 13 are provided in a manner of surrounding the position of one gate contact plug 8. Therefore, the discharge path of the electric charge at the time of plasma processing is large, and they are all located at a position not so far from the first gate electrode 5. Therefore, the protection effect of the first diodes 13 on the gate oxide film is very large. By connecting the gate contact plug 8 to at least a part of the first diodes 13 with the wiring layer 4, the effect becomes even better at the time of processing of the upper layer.

[0086] The configuration relationship of the gate contact plug 8 and the diode contact plug 9 is described. In Figure 7 , the gate contact plug 8 and the diode contact plug 9 around it in the cross section parallel to the plate surface of the semiconductor substrate 2 are shown. In Figure 7 , the cross-sectional shape of the gate contact plug 8 and the diode contact plug 9 are both square of the same size. Figure 7 In , the length T of one side of the gate contact plug 8, the interval G1 (the vertical direction in the drawing) between the gate contact plug 8 and the diode contact plug 9, and the interval G2 (the horizontal direction in the drawing) are also shown.

[0087] The intervals G1, G2 are preferably 5 times or less the length T of one side of the gate contact plug 8. This is for compactness of the overall structure of the element. The length T of one side of the gate contact plug 8 is one example of the thickness of the gate contact plug 8, and the diagonal length can also be used as the thickness. The cross-sectional shape of the gate contact plug 8 and the diode contact plug 9 is not limited to the square shape described above. It can be circular, or other shapes such as rectangular. In the case of a circular shape, the thickness can be the diameter. In the case of a rectangular shape, it can be the length of the short side, the length of the long side, or the diagonal length. In any case, the interval between the gate contact plug 8 and the diode contact plug 9 is preferably 5 times or less the thickness of the gate contact plug 8.

[0088] The interval between the gate contact plug 8 and the diode contact plug 9 is the shortest distance between the gate contact plug 8 and the diode contact plug 9 adjacent thereto. The intervals G1, G2 are one example. In Figure 7 the interval G1 is depicted as being different from the interval G2, but they can also be the same. The cross-sectional shape of the gate contact plug 8 and the cross-sectional shape of the diode contact plug 9 can also be different. The cross-sectional shape of the diode contact plug 9 can also not be the same throughout.

[0089] The disclosed technology can also be applied to the case of CMOS. By Figure 8 this example is described. In Figure 8 the upper layer insulating layer 14 and the upper layer wiring layer 15 are omitted for simplicity. In Figure 8 the right half, a structure substantially the same as that shown in Figure 1 is shown. In Figure 8 these structures are referred to as the first gate electrode 5, the first main element 12 (NMOS), the first gate contact plug 8a, the first diode contact plug 9a, and the first diode 13.

[0090] In the left half in Figure 8 a structure of a MOS transistor and its periphery of a conductive type opposite to that of the first main element 12 is shown. The MOS transistor is a second main element 32 (PMOS). Specifically, a second gate electrode 25, a second gate contact plug 28, a second diode contact plug 29, and an N+ region 27 are formed.

[0091] In the semiconductor substrate 2 in Figure 8 in addition to the N well 6 described above as a first conductive type well, a P main well 26 as a second conductive type main well, a P sub well 36 as a second conductive type sub well, and an N deep well 20 as a first conductive type deep well are formed.

[0092] Please refer to Figure 3 , Figure 8The N well 6 is formed in a first range (not shown) that includes the position of the MOS transistor and the position of the P+ region 7 (the first diode 13). The P main well 26 is formed in a second range (not shown) that includes the position of the second main element 32. The P sub well 36 is formed in a third range (not shown) that includes the position of the N+ region 27 (the second diode). The N deep well 20 is formed in a range that includes the lower portion of the N well 6 and the P main well 26 and does not include the lower portion of the P sub well 36.

[0093] With this well structure, the second diode is constituted by the N+ region 27 and the P sub well 36. The second diode is of opposite polarity to the first diode 13 described above. In addition, the P sub well 36 is directly connected to the original P-type portion of the semiconductor substrate 2 without passing through the N deep well 20. Thus, in the portion of the second main element in the left half of the semiconductor device 1, as in the portion of the first main element in the right half, a protective effect on the gate oxide film during plasma processing is obtained. In the portion of the second main element, the charge that flows into the second diode through the second diode contact plug 29 can flow out from the P sub well 36 to the P-type portion without being blocked by the N deep well 20. Figure 8

[0094] As described in detail above, according to the present embodiment, a plurality of diodes are arranged in a manner that surrounds the position where the gate contact plug exists in the semiconductor device 1. Thus, the charge during processing with plasma treatment is not concentrated on the gate electrode but is discharged via the diodes. In this way, a semiconductor device that can effectively suppress deterioration during plasma processing is realized with a configuration in which there is no waste, together with a method of manufacturing the same.

[0095] Furthermore, the present embodiment is merely an example and does not limit the present technology in any way. Thus, the present technology can of course be modified in various ways within the scope of the gist thereof. For example, the number of layers of the insulating layer and the wiring layer thereon can be greater. The first main element and the second main element can be elements that have an insulating gate electrode. The first diode and the second diode can function not only to protect the gate oxide film during plasma processing but also as a part of the circuit mounted on the semiconductor device 1. That is, the pattern of the wiring layer 4 can be changed as appropriate. The N deep well 20 can also locally reach the lower portion of the P sub well 36. The N-type and the P-type can be replaced.

[0096] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features in the above-described embodiments are described, but it should be understood that the scope of the present specification includes any combination of the technical features as long as the combination does not cause a contradiction.

[0097] ​The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope. It should be pointed out that, for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application.

Claims

1. A semiconductor device, characterized by comprising: A semiconductor device includes a semiconductor substrate, an insulating layer over the semiconductor substrate, and a wiring layer over the insulating layer, The semiconductor device includes: a first main element disposed on the semiconductor substrate and having a first gate electrode insulated from the semiconductor substrate; a first gate contact plug in contact with the first gate electrode from the wiring layer; a first diode disposed on each of a plurality of sites surrounding a site directly below the first gate contact plug in the semiconductor substrate; and a plurality of first diode contact plugs in contact with each of the first diodes from the wiring layer, at least one of the plurality of first diode contact plugs surrounding the first gate contact plug being connected to the first gate contact plug through a pattern of the wiring layer, and the remaining first diode contact plugs not being connected to the first gate contact plug in a horizontal plane of the wiring layer. a second main element disposed on the semiconductor substrate and having a second gate electrode insulated from the semiconductor substrate, the second gate electrode having a conductivity type opposite to that of the first main element; a second gate contact plug in contact with the second gate electrode from the wiring layer; a second diode disposed on each of a plurality of sites surrounding a site directly below the second gate contact plug in the semiconductor substrate, the second diode having a conductivity type opposite to that of the first diode; a plurality of second diode contact plugs in contact with each of the second diodes from the wiring layer, at least one of the plurality of second diode contact plugs surrounding the second gate contact plug being connected to the second gate contact plug through a pattern of the wiring layer, and the remaining second diode contact plugs not being connected to the second gate contact plug in a horizontal plane of the wiring layer, the second gate contact plug not being connected to the first gate contact plug in the horizontal plane of the wiring layer. The semiconductor device includes: a first conductivity type well including a range of a position of the first main element and a position of the first diode; a second conductivity type main well including a range of a position of the second main element; a second conductivity type sub well including a range of the second diode; and a first conductivity type deep well including a range of a lower portion of the first conductivity type well and the second conductivity type main well, and not including at least a portion of a lower portion of the second conductivity type sub well.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes: an upper layer insulating layer over the wiring layer; an upper layer wiring layer over the upper layer insulating layer; a gate via plug in contact with the wiring layer over the first gate contact plug from the upper layer wiring layer; and a diode via plug in contact with the wiring layer over the first diode contact plug from the upper layer wiring layer. A distance between the first gate contact plug and the first diode contact plug adjacent to the first gate contact plug is the shortest distance between the first gate contact plug and the first diode contact plug.

3. The semiconductor device according to claim 2, wherein In a portion of the second main element, a charge flowing into the second diode through the second diode contact plug can flow from the second conductivity type sub well to the semiconductor substrate portion without being blocked by the first conductivity type deep well.

4. The semiconductor device according to claim 1 or 2, wherein ​ 5. The semiconductor device according to claim 1 or 2, wherein a gap between the first gate contact plug and the first diode contact plug is 5 times or less the thickness of the first gate contact plug.

6. The semiconductor device according to claim 1, wherein the semiconductor substrate includes: a second conductivity type region provided at a plurality of sites of a portion of a surface of the semiconductor substrate; a first conductivity type well including a range of positions of the first main element and the second conductivity type region; a lower portion of the second conductivity type region contacts the first conductivity type well, and a contact site between the second conductivity type region and the first conductivity type well is the first diode.

7. The semiconductor device according to claim 1, wherein a gate oxide film is provided between the semiconductor substrate and the first gate.

8. The semiconductor device according to claim 1, wherein the first main element includes a metal oxide semiconductor transistor.

9. A method for manufacturing a semiconductor device, characterized by a semiconductor device manufactured by the manufacturing method of any one of claims 1 to 8, the manufactured semiconductor device including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a wiring layer on the insulating layer, a main element and a diode being formed in the semiconductor substrate, the main element having a gate electrode insulated from the semiconductor substrate, in the manufacturing method of the semiconductor device, before the wiring layer is formed, a hole processing is performed on the insulating layer to form a gate contact hole exposing the gate electrode on the wiring layer side and a diode contact hole exposing the diode on the wiring layer side, after the hole processing, a build-up is performed to form the wiring layer, a gate contact plug filling the gate contact hole, and a diode contact plug filling the diode contact hole, at least one of the hole processing and the build-up includes a plasma treatment, the diodes are respectively provided at a plurality of sites surrounding sites directly below the gate contact plugs in the semiconductor substrate, in the hole processing, the diode contact holes are respectively formed for the diodes at the plurality of sites.

10. The manufacturing method of the semiconductor device according to claim 9, wherein after the build-up, an upper insulating layer on the wiring layer and an upper wiring layer on the upper insulating layer are formed, and before the upper wiring layer is formed, an upper hole processing is performed on the upper insulating layer to form a gate via exposing the wiring layer on the gate contact plug on the upper wiring layer side and a diode via exposing the wiring layer on the diode contact plug on the upper wiring layer side, after the upper hole processing, an upper build-up is performed to form the upper wiring layer, a gate via plug filling the gate via, and a diode via plug filling the diode via, at least one of the upper hole processing and the upper build-up includes a plasma treatment, at least one of the diode contact plugs is connected to the gate contact plug through a pattern of the wiring layer after the build-up.

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