A multi-segment programmable soft-start circuit

Abstract

This invention discloses a multi-segment programmable soft-start circuit, comprising a frequency divider circuit, a digital-to-analog converter circuit, and a counter circuit. The frequency divider circuit generates a clock signal with an adjustable division ratio. The counter circuit receives the clock signal with an adjustable division ratio and generates a counting signal. The digital-to-analog converter circuit receives the counting signal and controls the output voltage to rise slowly in a step-like manner. This invention simultaneously solves the challenges of linearity, accuracy, noise, and integration with a simple architecture, providing key technical support for high-reliability power supply systems.

Description

Technical Field

[0001] This invention relates to a soft-start circuit, and more particularly to a multi-segment programmable soft-start circuit, belonging to the field of semiconductor integrated circuit technology. Background Technology

[0002] In electronic systems such as power management and power drives, the surge current at power-on can easily damage components and interfere with the system. To address this issue, soft-start technology is typically used to suppress surges by controlling the gradual rise of voltage / current.

[0003] Chinese Patent Publication No. CN117856601A discloses a surge suppression soft-start circuit with hysteresis characteristics to solve the problem of surge current and surge voltage generated during system power-up. It suppresses surge current and surge voltage by limiting current through a resistor. However, RC delay circuits utilize capacitor charging to generate a ramp, and the start-up time is greatly affected by component accuracy and temperature drift. Furthermore, long delays require large capacitors and resistors, leading to significant area costs.

[0004] Chinese patent publication CN116759886A discloses a soft-start constant power laser indicator control circuit and method, implemented based on a voltage-controlled constant current source module, which can avoid laser overshoot and overcurrent, protecting the laser and other devices. However, although constant current source charging improves linearity, it still relies on a high-precision current source, resulting in insufficient flexibility and anti-drift capability.

[0005] Chinese Patent Publication No. CN101741233A discloses a soft-start circuit for a DC-DC switching power supply with digital-to-analog conversion control. It uses a counter to achieve a stepped increase in the digital-to-analog conversion voltage, but the counter frequency is fixed and the voltage rise rate cannot be dynamically adjusted.

[0006] In summary, existing technologies struggle to simultaneously achieve high linearity ramp, precise timing control, flexible adjustability, and compact structure. Therefore, there is an urgent need for a soft-start solution that can generate stepless voltage regulation, precise timing, strong programmability, and eliminate the need for large capacitors, thus overcoming the limitations of traditional designs. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a multi-segment programmable soft-start circuit that simultaneously solves the problems of linearity, accuracy, noise and integration.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] A multi-segment programmable soft-start circuit includes a frequency divider circuit, a digital-to-analog converter circuit, and a counter circuit. The frequency divider circuit generates a clock signal with a flexibly adjustable division ratio. The counter circuit receives the clock signal with a flexibly adjustable division ratio and generates a counting signal. The digital-to-analog converter circuit receives the counting signal and controls the output voltage to rise slowly in a step-like manner.

[0010] Furthermore, the frequency divider circuit includes a counter module, a frequency divider core module, and a logic toggle module. The counter module generates N output signals QB0 to QB based on the clock signal CLK. N-1 The frequency division core module is based on N output signals QB0~QB N-1 and N control signals S0~S N-1 The logic flip module generates a frequency-divided clock signal CLK_DIV based on the flip control signal and the clock signal CLK.

[0011] Furthermore, the counter module includes N D flip-flops DFF0 to DFF0. N-1 For the (i+1)th D flip-flop (DFF) i i = 0, 1, 2, ..., N-2, D flip-flop (DFF) i The Q terminal and the D flip-flop DFF i+1 The CLK terminal is connected to the D flip-flop DFF. i of Terminal and D flip-flop DFF i The D terminal is connected and generates the output signal QB. i The CLK input of the D flip-flop DFF0 is connected to the clock signal CLK. The D flip-flop DFF... N-1 of Terminal and D flip-flop DFF N-1 The D terminal is connected and generates the output signal QB. N-1 .

[0012] Furthermore, the frequency division core module includes N XOR gates X0 to X1. N-1 N XOR gates X0 to X N-1 The first input terminal is sequentially and one-to-one connected to N control signals S0 to S1. N-1 Connect N XOR gates X0 to X N-1 The second input terminal is sequentially and one-to-one connected to N output signals QB0~QB N-1 Connection; when N is even, the frequency divider core module also contains N / 2 N / N OR gates Y0 to Y10. N / 2-1 A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. jThe two input terminals are connected, where j = 0, 1, ..., N / 2-1, and there are N / 2 N / N NOR gates Y0 to Y1. N / 2-1 The output terminal is connected one-to-one with the N / 2 input terminals of the multiplexer G0, and the output terminal of the multiplexer G0 generates a toggle control signal; when N is odd, the frequency divider core module also includes One or NOT gate Y0~ A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. j The two input terminals are connected, where j = 0, 1, ..., ... XOR gate N-1 The output of the AND-OR-NOT gate The first input is connected to the NOR gate. The second input terminal is grounded. One or NOT gate Y0~ The output terminal of the AND gate G0 Each input terminal is connected in a one-to-one correspondence, and the output terminal of the multiplexer G0 generates a toggle control signal.

[0013] Furthermore, the logic toggle module includes NOR gate SR0, NOR gate SR1, NOT gate G1, AND gate G2, and NAND gate G3. The input of NOT gate G1 and the first input of NOR gate SR0 are connected to the clock signal CLK. The output of NOT gate G1 is connected to the first input of AND gate G2. The second input of AND gate G2 is connected to the toggle control signal. The output of AND gate G2 is connected to the second input of NOR gate SR1 and the second input of NAND gate G3. The output of NOR gate SR0 is connected to the first input of NOR gate SR1 and the first input of NAND gate G3 to generate a frequency-divided clock signal CLK_DIV. The output of NOR gate SR1 is connected to the second input of NOR gate SR0. The output of NAND gate G3 is connected to N D flip-flops DFF0 to DFF1. N-1 of End connection.

[0014] Furthermore, the counter circuit includes M+1 D flip-flops dff0~dff M OR gate Z0, OR gate Z1, and multiplexed AND gate Z2, D flip-flops dff0~dff M The Q terminal generates a control signal SS k For the k-th D flip-flop dff k k=0, 1, 2, ..., M-2, D flip-flop dff k of Terminal and D flip-flop dff k The D terminal and the D flip-flop dff k+1The CLK terminal of the D flip-flop dff0 is connected to the output of the OR gate Z0. M-1 of Terminal and D flip-flop dff M-1 The D terminal is connected to the first input terminal of OR gate Z0 and the first input terminal of OR gate Z1, which are connected to the frequency divider clock signal CLK_DIV. The second input terminal of OR gate Z0 is connected to the output terminal of multiplexer Z2 and D flip-flop dff. M The D terminal is connected, and the D flip-flop is dff. M The Q terminal of the OR gate Z1 and the second input of the D flip-flop dff0~dff M-1 The RST terminal is connected to generate the control signal SS_OVER, and the inputs of the multiplexer Z2 are sequentially connected to control signals SS0 to SS0. M-1 .

[0015] Furthermore, the digital-to-analog converter circuit includes M+1 conversion branches, resistor RLP, and resistors R0 to R1. M-1 The k-th branch in the first M switching branches contains switch SS k-1 RH resistance k-1 , resistor RL k-1 and switch k=0, 1, 2, ..., M-1, switch SS k-1 One end is connected to the reference voltage V REF SS switch k-1 The other end is connected to resistor RH k-1 One end is connected to resistor RH k-1 The other end is connected to resistor RL k-1 One end is connected to resistor RL k-1 The other end is connected to the switch One end is connected to the switch. The other end is grounded, switch SS k-1 Control signal SS k-1 Control, switch Control signal Control, control signal SS k-1 and control signals For a pair of inverted signals, the (M+1)th conversion branch includes a switch SS_OVER, a resistor RHT, a resistor RLT, and a switch. One end of the switch SS_OVER is connected to the reference voltage V. REF The other end of switch SS_OVER is connected to one end of resistor RHT, the other end of resistor RHT is connected to one end of resistor RLT, and the other end of resistor RLT is connected to switch SS_OVER. One end is connected to the switch. The other end is grounded, and the switch SS_OVER is controlled by the control signal SS_OVER. Control signal Control, control signal SS_OVER and control signal This is a pair of inverted signals; one end of resistor RLP is connected to one end of resistor RL0, and the other end of resistor RLP is grounded. For the k-th resistor R... k-1 resistance R k-1 One end is connected to resistor RH k-1 The other end is connected to resistor R. k-1 The other end is connected to resistor RH k The other end is connected to resistor R. M-1 One end is connected to resistor RH M-1 The other end is connected to resistor R. M-1 The other end generates an output voltage V SS_REF .

[0016] Furthermore, the N control signals S0 to S N-1 It is provided sequentially by N multi-level multiplexing branches, each multi-level multiplexing branch containing multiplexers MUX1 to MUX2. P The 0 terminal of multiplexer MUX1 is connected to power supply VDD or ground, and the 1 terminal of multiplexer MUX1 is also connected to power supply VDD or ground. The ~MUX terminals of multiplexer MUX2... P One terminal is connected to the power supply VDD or ground, for the s-th multiplexer MUX s s=1, 2, ..., P-1, multiplexer MUX s The output terminal of the MUX multiplexer s+1 Terminal 0 connection, multiplexer MUX s The S-terminal is connected to the control signal CNT. s MUX (Multi-channel Selector) P The S-terminal is connected to the control signal CNT. P A MUX with N multi-level multi-path branches P The output terminals sequentially generate control signals S0 to S10. N-1 .

[0017] Furthermore, the control signals CNT1~CNT P Generated by a P-line control signal circuit, the control signal circuit includes a multiplexer K0, a NOR gate K1, and a NOR gate K2. The inputs of the multiplexer K0 are sequentially connected to the control signals SS0 / ~SS N-1 / The output of the AND gate K0 is connected to the first input of the NOR gate K1, the output of the NOR gate K1 is connected to the first input of the NOR gate K2, and the second input of the NOR gate K2 is connected to the control signal SS_OVER. The output of the NOR gate K2 of the P control signal circuit is connected to the second input of the NOR gate K1, and control signals CNT1 to CNT are generated sequentially. P And CNT1 <CNT2<……<CNT P .

[0018] Compared with the prior art, the present invention has the following advantages and effects:

[0019] 1. This invention solves the problems of linearity, accuracy, noise and integration simultaneously with a simple architecture, providing key technical support for high-reliability power supply systems;

[0020] 2. This invention features high linearity and ripple-free operation: the DAC directly outputs a continuously adjustable analog voltage, eliminating digital quantization steps and achieving a precise linear ramp.

[0021] 3. The timing of this invention is precise and controllable: by configuring the frequency division ratio N to adjust the number of clock cycles, the startup time can be precisely programmed, resisting temperature / process drift;

[0022] 4. This invention breaks through the area bottleneck: it completely removes large-capacity capacitors, allowing for full integration of the frequency divider and DAC module, thus reducing chip area costs;

[0023] 5. This invention is highly flexible and scalable: it supports dynamic adjustment of the startup curve slope and duration to adapt to various scenario requirements. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of a frequency divider circuit for a multi-segment programmable soft-start circuit according to the present invention.

[0025] Figure 2 This is a partially enlarged view of the frequency divider circuit of a multi-segment programmable soft-start circuit according to the present invention.

[0026] Figure 3 This is a schematic diagram of a counter circuit for a multi-segment programmable soft-start circuit according to the present invention.

[0027] Figure 4 This is a schematic diagram of a digital-to-analog converter circuit for a multi-segment programmable soft-start circuit according to the present invention.

[0028] Figure 5 This is a schematic diagram of a multi-stage multiplexer branch of a multi-segment programmable soft-start circuit according to the present invention.

[0029] Figure 6 This is a schematic diagram of the control signal circuit of a multi-segment programmable soft-start circuit according to the present invention.

[0030] Figure 7 This is a schematic diagram of a frequency divider circuit for a multi-segment programmable soft-start circuit according to an embodiment of the present invention.

[0031] Figure 8 This is a schematic diagram of a multi-stage multiplexing branch of a multi-segment programmable soft-start circuit according to an embodiment of the present invention.

[0032] Figure 9 This is a schematic diagram of a counter circuit of a multi-segment programmable soft-start circuit according to an embodiment of the present invention.

[0033] Figure 10 This is a schematic diagram of a digital-to-analog converter circuit for a multi-segment programmable soft-start circuit according to an embodiment of the present invention.

[0034] Figure 11 This is a schematic diagram of the control signal circuit of a multi-segment programmable soft-start circuit according to an embodiment of the present invention. Detailed Implementation

[0035] To illustrate in detail the technical solutions adopted by the present invention to achieve the intended technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Furthermore, the technical means or technical features in the embodiments of the present invention can be replaced without creative effort. The present invention will be described in detail below with reference to the accompanying drawings and embodiments.

[0036] This invention discloses a multi-segment programmable soft-start circuit, comprising a frequency divider circuit, a digital-to-analog converter circuit, and a counter circuit. The frequency divider circuit generates a clock signal with an adjustable division ratio. The counter circuit receives the clock signal with an adjustable division ratio and generates a counting signal. The digital-to-analog converter circuit receives the counting signal and controls the output voltage to rise slowly in a step-like manner. Simultaneously, by dynamically adjusting the division ratio of the frequency divider circuit in multiple segments, the rise rate of the output voltage is controlled, thereby achieving soft start and effectively suppressing surges.

[0037] like Figure 1 and Figure 2 As shown, the frequency divider circuit includes a counter module, a frequency divider core module, and a logic toggle module. The counter module generates N output signals QB0 to QB based on the clock signal CLK. N-1 The frequency division core module is based on N output signals QB0~QB N-1 and N control signals S0~S N-1 The logic flip module generates a frequency-divided clock signal CLK_DIV based on the flip control signal and the clock signal CLK.

[0038] The counter module contains N D flip-flops DFF0 to DFF0. N-1 For the (i+1)th D flip-flop (DFF) i i = 0, 1, 2, ..., N-2, D flip-flop (DFF) i The Q terminal and the D flip-flop DFF i+1 The CLK terminal is connected to the D flip-flop DFF. i of Terminal and D flip-flop DFF i The D terminal is connected and generates the output signal QB. i The CLK input of the D flip-flop DFF0 is connected to the clock signal CLK. The D flip-flop DFF... N-1 of Terminal and D flip-flop DFF N-1 The D terminal is connected and generates the output signal QB. N-1 .

[0039] The choice depends on the adjustment range of the target frequency division ratio R, and the specific relationship is as follows:

[0040] .

[0041] N D flip-flops, all triggered by the same rising edge of the clock, form a subtraction counter.

[0042] The frequency division core module contains N XOR gates X0 to X1. N-1 N XOR gates X0 to X N-1 The first input terminal is sequentially and one-to-one connected to N control signals S0 to S1. N-1 Connect N XOR gates X0 to X N-1 The second input terminal is sequentially and one-to-one connected to N output signals QB0~QB N-1 Connection; when N is even, the frequency divider core module also contains N / 2 N / N OR gates Y0 to Y10. N / 2-1 A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. j The two input terminals are connected, where j = 0, 1, ..., N / 2-1, and there are N / 2 N / N NOR gates Y0 to Y1. N / 2-1 The output terminal is connected one-to-one with the N / 2 input terminals of the multiplexer G0, and the output terminal of the multiplexer G0 generates a toggle control signal; when N is odd, the frequency divider core module also includes One or NOT gate Y0~ A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. jThe two input terminals are connected, where j = 0, 1, ..., ... XOR gate N-1 The output of the AND-OR-NOT gate The first input is connected to the NOR gate. The second input terminal is grounded. One or NOT gate Y0~ The output terminal of the AND gate G0 Each input terminal is connected in a one-to-one correspondence, and the output terminal of the multiplexer G0 generates a toggle control signal.

[0043] N control signals S0~S N-1 Used for dynamically adjusting the frequency division ratio.

[0044] The logic toggle module includes NOR gate SR0, NOR gate SR1, NOT gate G1, AND gate G2, and NAND gate G3. The input of NOT gate G1 and the first input of NOR gate SR0 are connected to the clock signal CLK. The output of NOT gate G1 is connected to the first input of AND gate G2. The second input of AND gate G2 is connected to the toggle control signal. The output of AND gate G2 is connected to the second inputs of NOR gate SR1 and NAND gate G3. The output of NOR gate SR0 is connected to the first inputs of NOR gate SR1 and NAND gate G3 to generate a frequency-divided clock signal CLK_DIV. The output of NOR gate SR1 is connected to the second input of NOR gate SR0. The output of NAND gate G3 is connected to N D flip-flops DFF0 to DFF1. N-1 of End connection.

[0045] To achieve a clock signal with a division ratio of R, at the initial moment, the output of the counter module ( Set to 1, Multiple AND gate The output is 0.

[0046] The frequency divider circuit uses control signals... ( )satisfy:

[0047] ；

[0048] And the frequency division ratio R only needs to satisfy:

[0049] 。

[0050] From the 1st to the 2nd Within -1 clock cycle, the counter's output ( An N-bit binary number consisting of the least significant bit and the most significant bit. Gradually reduce by 1 to When the first clock cycle arrives, It is at a high level because of the multiplexed AND gate. The output of the AND gate is 0, making the AND gate... The output of the RS flip-flop is also 0, and the RS flip-flop output is... The output is low. For the next R-1 clock cycles (including the first clock cycle), because the output of the multiplexed AND gate does not satisfy the condition that the output of the preceding NOR gate is always high, its output remains 0. Similarly, the output of AND gate G2 remains 0. Thus, the frequency-divided clock signal... It remains low until the Rth clock cycle arrives, at which point the counter output is... Multiple doors The output is 1 for the first time, which sets the toggle control signal high, thus releasing the AND gate. During this cycle, when CLK changes from high to low, the RS flip-flop outputs... The level is high, thus enabling the NAND gate to... Output, i.e., set signal The value is 0, so the D flip-flop outputs 0. Set the bit to 1 again, clear the subtractor, and then use the AND gate. The output of G1 becomes 0 again, and the output of G2 also becomes 0. Thus, when the first... When +1 clock cycle arrives When the signal is high, the RS flip-flop outputs the frequency-divided signal. By flipping to a low level and repeating this cycle, the R-division of the original signal CLK is achieved.

[0051] like Figure 3 As shown, the counter circuit contains M+1 D flip-flops dff0~dff M OR gate Z0, OR gate Z1, and multiplexed AND gate Z2, D flip-flops dff0~dff M The Q terminal generates a control signal SS k For the k-th D flip-flop dff k k=0, 1, 2, ..., M-2, D flip-flop dff k of Terminal and D flip-flop dff k The D terminal and the D flip-flop dff k+1 The CLK terminal of the D flip-flop dff0 is connected to the output of the OR gate Z0. M-1 of Terminal and D flip-flop dff M-1 The D terminal is connected to the first input terminal of OR gate Z0 and the first input terminal of OR gate Z1, which are connected to the frequency divider clock signal CLK_DIV. The second input terminal of OR gate Z0 is connected to the output terminal of multiplexer Z2 and D flip-flop dff. MThe D terminal is connected, and the D flip-flop is dff. M The Q terminal of the OR gate Z1 and the second input of the D flip-flop dff0~dff M-1 The RST terminal is connected to generate the control signal SS_OVER, and the inputs of the multiplexer Z2 are sequentially connected to control signals SS0 to SS0. M-1 .

[0052] Initial time as well as All are 0. After... After one clock cycle Depend on Become , It's still 0. At this point, the multi-way AND gate... The output is connected to the D flip-flop. Input Changing to 1 also makes the OR gate... The output is 1, at which point the counter blocks the clock signal, and the counter outputs... Keep When the rising edge of the next clock cycle arrives, the D flip-flop... Output It changes to 1, serving as the reset signal for the counter. A high value will cause the counter to reset to zero, returning it to its initial state. Become ,and A value of 1 will also enable the OR gate. The output is 1, which makes the D flip-flop... Shield clock signal, output When locked at 1, the counter stops changing, marking the end of the soft start, until the chip is completely powered down.

[0053] like Figure 4 As shown, the digital-to-analog converter circuit includes M+1 conversion branches, resistor RLP, and resistors R0 to R1. M-1 The k-th branch in the first M switching branches contains switch SS k-1 RH resistance k-1 , resistor RL k-1 and switch k=0, 1, 2, ..., M-1, switch SS k-1 One end is connected to the reference voltage V REF SS switch k-1 The other end is connected to resistor RH k-1 One end is connected to resistor RH k-1 The other end is connected to resistor RL k-1 One end is connected to resistor RL k-1 The other end is connected to the switch One end is connected to the switch. The other end is grounded, switch SS k-1 Control signal SS k-1 Control, switch Control signal Control, control signal SS k-1 and control signals For a pair of inverted signals, the (M+1)th conversion branch includes a switch SS_OVER, a resistor RHT, a resistor RLT, and a switch. One end of the switch SS_OVER is connected to the reference voltage V. REF The other end of switch SS_OVER is connected to one end of resistor RHT, the other end of resistor RHT is connected to one end of resistor RLT, and the other end of resistor RLT is connected to switch SS_OVER. One end is connected to the switch. The other end is grounded, and the switch SS_OVER is controlled by the control signal SS_OVER. Control signal Control, control signal SS_OVER and control signal This is a pair of inverted signals; one end of resistor RLP is connected to one end of resistor RL0, and the other end of resistor RLP is grounded. For the k-th resistor R... k-1 resistance R k-1 One end is connected to resistor RH k-1 The other end is connected to resistor R. k-1 The other end is connected to resistor RH k The other end is connected to resistor R M-1 One end is connected to resistor RH M-1 The other end is connected to resistor R. M-1 The other end generates an output voltage V SS_REF .

[0054] Resistors R0~R M-1 The resistance value is R, resistor RLP, resistor RH k-1 , resistor RL k-1 The resistance values ​​of resistors RHT and RLT are 2R. A trapezoidal network resistor structure is used to achieve digital-to-analog conversion. This structure consists of several resistors with a resistance ratio of... The precision resistor units form a binary weighted structure, with each branch cascaded to a common output node via resistor R, forming a ladder-like topology. When the control signal... or When the value is 0, the branch is grounded; when the control signal... or When the value is 1, the branch is connected to the reference voltage. . The output voltage is located at the end of the branch. .

[0055] Output voltage and and The M+1 bit binary value T is formed from the least significant bit to the most significant bit, and the specific formula is as follows:

[0056] .

[0057] when Depend on Accumulated by counting through clock cycles At that time, the output voltage It also gradually rose from 0 to Simply make By setting the output voltage to twice the target voltage, a step-by-step soft-start can be achieved, ultimately yielding the desired soft-start voltage. Clearly, the rate of increase in output voltage is related to the frequency division clock signal. The voltage rises more slowly because the period is longer. The longer the period, the longer it takes for the counter value to increase by 1, and the slower the voltage rises.

[0058] In addition to providing fixed control signals, phased configuration is also possible. This allows for a soft-start circuit that increases voltage in multiple stages with different slopes. For example... Figure 5 As shown, N control signals S0 to S1 N-1 It is provided sequentially by N multi-level multiplexing branches, each multi-level multiplexing branch containing multiplexers MUX1 to MUX2. P The 0 terminal of multiplexer MUX1 is connected to power supply VDD or ground, and the 1 terminal of multiplexer MUX1 is also connected to power supply VDD or ground. The ~MUX terminals of multiplexer MUX2... P One terminal is connected to the power supply VDD or ground, for the s-th multiplexer MUX s s=1, 2, ..., P-1, multiplexer MUX s The output terminal of the MUX multiplexer s+1 Terminal 0 connection, multiplexer MUX s The S-terminal is connected to the control signal CNT. s MUX (Multi-channel Selector) P The S-terminal is connected to the control signal CNT. P A MUX with N multi-level multi-path branches P The output terminals sequentially generate control signals S0 to S10. N-1 .

[0059] When the segmented control signals CNT1~CNT P When all three are 0, the control signals S0 to S2 are... N-1The control signals S0 to S1 are determined by the 0th input of the multiplexer MUX1. When the control signal CNT1 is 1, the control signals S0 to S1 are... N-1 The control signals S0 to S1 are determined by input 1 of the multiplexer MUX1 until CNT2 is 1. N-1 The control signal CNT1 is determined by input 1 of the multiplexer MUX2, meaning that control signal CNT1 is overridden by control signal CNT2, and the control signal CNT1 ~ CNT2... P Gradually set to 1, control signals S0~S N-1 The path is determined by input 0 of multiplexer MUX1, input 1 of multiplexer MUX1, input 1 of multiplexer MUX2, and so on, until MUX... P One end determines the P control signals CNT. P This allows for a P+1 stage soft-start process by setting the stage control signal CNT. P The number of stages required for a multi-stage soft boot can be changed.

[0060] like Figure 6 As shown, control signals CNT1~CNT P Generated by a P-line control signal circuit, the control signal circuit includes a multiplexer K0, a NOR gate K1, and a NOR gate K2. The inputs of the multiplexer K0 are sequentially connected to the control signals SS0 / ~SS N-1 / The output of the AND gate K0 is connected to the first input of the NOR gate K1, the output of the NOR gate K1 is connected to the first input of the NOR gate K2, and the second input of the NOR gate K2 is connected to the control signal SS_OVER. The output of the NOR gate K2 of the P control signal circuit is connected to the second input of the NOR gate K1, and control signals CNT1 to CNT are generated sequentially. P And CNT1 <CNT2<……<CNT P .

[0061] Because the inputs of the multiplexer K0 are all the outputs of the counter circuit and their inverted signals, these segmented control signals actually represent the count value. That is, we can design the combination of the multiplexer K0 inputs according to the segmentation time required during the system's soft-start process, thus ensuring that the count value represented by the segmented control signals matches the required segmentation time. The circuit principle is as follows: When the count value reaches the preset value, all inputs to the multiplexer K0 are 1, therefore, the output of the multiplexer K0 is also 1. Since the soft-start process is still ongoing, the counter is still in the counting state, and the control signal SS_OVER connected to the second input of the NOR gate K2 is 0, causing the RS flip-flop to be set to 1, i.e., the segmentation control signal CNT. sThe value is 1, and due to the characteristics of the RS flip-flop, the reset terminal SS_OVER remains 0 until the soft start is complete. Once the segmentation control signal is set to 1, it remains 1 until the soft start is complete. At this time, the control signals S0~S of the frequency divider clock circuit are... N-1 By segmented control signal CNT s The corresponding multiplexer MUX s The 1st end determines the segmented signal until it covers a higher count value.

[0062] Furthermore, by configuring the connection method of each multiplexer port and coordinating with segmented control signals CNT1~CNT... P This allows for the generation of N control signals S0 to S1 at different time periods during the soft-start process. N-1 Different combinations of these elements achieve different division ratios R for different time periods. The changes in the clock of the timer circuit are reflected in the digital-to-analog converter circuit as changes in the slope of the soft-start voltage rise, thus realizing a soft-start circuit that increases voltage in multiple stages with different slopes.

[0063] like Figures 7 to 11 The diagram shown is a schematic representation of a specific embodiment of the present invention.

[0064] Let N=8, control signal ( )satisfy:

[0065] ；

[0066] This allows for the adjustment of the division ratio to any integer multiple, and the division ratio R only needs to satisfy:

[0067] .

[0068] Let M=10, output voltage and and The eleven-bit binary value T is formed from the least significant bit to the most significant bit, and the specific formula is as follows:

[0069] .

[0070] Setting P=2, the entire soft-start process is divided into three stages, in which control signals are specially configured for each stage. This achieves a slow-fast-slow adjustment mode.

[0071] Initially, the counter circuit outputs 0, therefore, the segmentation indication signal... and All values ​​are 0, at which point the output of the eight-channel two-stage multiplexer is... The 8-bit binary number formed from the least significant bit to the most significant bit is 15, achieving a frequency division ratio of 15. This generates a frequency-divided clock signal with a longer period. The control voltage rises slowly. When the counter counts to... When all values ​​are set to 1, that is, when the counter reaches 126, the multiplexer gate... The output becomes 1. and When the RS flip-flop is in the set state, the first segment control signal... Become 1 and The value is still 0; the output of the two-stage multiplexer is... The 8-bit binary number formed from the least significant bit to the most significant bit is 240, achieving a frequency division ratio of... That is, 16. A shorter clock signal period causes the voltage rise rate to increase. When the counter counts to... When all values ​​are set to 1, that is, when the counter reaches 574, the multiplexer gate... The output becomes 1. and When the RS flip-flop is in the set state, the second segment control signal... When it changes to 1, its control logic combination covers the first segment control signal. The logical combination causes the output of the eight-way two-stage multiplexer to revert back to its original state. The voltage rise rate slows down again. When the soft-start completion signal SS_OVER goes high, the RS flip-flop will be in a reset state, and the segmented indicator signal will be... and The counter is reset to 0 and fully locked until the chip is completely powered down. This achieves a three-stage slow-fast-slow soft-start adjustment mode. To adapt to more application scenarios, the number of stages and voltage rise rate of the soft-start scheme can be customized by changing the division ratio of the frequency divider circuit and the number of stages of the multiplexer.

[0072] This invention addresses the challenges of linearity, accuracy, noise, and integration simultaneously with a simple architecture, providing key technical support for highly reliable power supply systems. Its high linearity and ripple-free performance are achieved by directly outputting a continuously adjustable analog voltage from the DAC, eliminating digital quantization steps and realizing a precise linear ramp. Precise timing control is ensured by adjusting the clock cycle number through the division ratio N, enabling accurate startup time programming and resistance to temperature / process drift. Overcoming area limitations, this invention completely eliminates large-capacity capacitors, allowing for full integration of the divider and DAC module, reducing chip area costs. Finally, this invention offers strong flexibility and scalability, supporting dynamic adjustment of the startup curve slope and duration to adapt to various scenarios.

[0073] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent substitutions, and improvements made to the above embodiments without departing from the scope of the present invention, based on the technical essence of the present invention and within the spirit and principles of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A multi-segment programmable soft-start circuit, characterized in that: It includes a frequency divider circuit, a digital-to-analog converter circuit, and a counter circuit. The frequency divider circuit generates a clock signal with a flexibly adjustable division ratio. The counter circuit receives the clock signal with a flexibly adjustable division ratio and generates a counting signal. The digital-to-analog converter circuit receives the counting signal and controls the output voltage to rise slowly in a step-like manner. The frequency divider circuit includes a counter module, a frequency divider core module, and a logic toggle module. The counter module generates N output signals QB0 to QB based on the clock signal CLK. N-1 The frequency division core module is based on N output signals QB0~QB N-1 and N control signals S0~S N-1 A toggle control signal is generated, and the logic toggle module generates a frequency-divided clock signal CLK_DIV based on the toggle control signal and the clock signal CLK. The N control signals S0~S N-1 It is provided sequentially by N multi-level multiplexing branches, each multi-level multiplexing branch containing multiplexers MUX1 to MUX2. P The 0 terminal of multiplexer MUX1 is connected to power supply VDD or ground, and the 1 terminal of multiplexer MUX1 is also connected to power supply VDD or ground. The ~MUX terminals of multiplexer MUX2... P One terminal is connected to the power supply VDD or ground, for the s-th multiplexer MUX s s=1, 2, ..., P-1, multiplexer MUX s The output terminal of the MUX multiplexer s+1 Terminal 0 connection, multiplexer MUX s The S-terminal is connected to the control signal CNT. s MUX (Multi-channel Selector) P The S-terminal is connected to the control signal CNT. P A MUX with N multi-level multi-path branches P The output terminals sequentially generate control signals S0 to S10. N-1 ; The control signals CNT1~CNT P Generated by a P-line control signal circuit, the control signal circuit includes a multiplexer K0, a NOR gate K1, and a NOR gate K2. The inputs of the multiplexer K0 are sequentially connected to the control signals SS0 / ~SS N-1 / The output of the AND gate K0 is connected to the first input of the NOR gate K1, the output of the NOR gate K1 is connected to the first input of the NOR gate K2, and the second input of the NOR gate K2 is connected to the control signal SS_OVER. The output of the NOR gate K2 of the P control signal circuit is connected to the second input of the NOR gate K1, and control signals CNT1 to CNT are generated sequentially. P And CNT1 < CNT2 < ... <CNT P .

2. The multi-segment programmable soft-start circuit according to claim 1, characterized in that: The counter module contains N D flip-flops DFF0 to DFF0. N-1 For the (i+1)th D flip-flop (DFF) i i = 0, 1, 2, ..., N-2, D flip-flop (DFF) i The Q terminal and the D flip-flop DFF i+1 The CLK terminal is connected to the D flip-flop DFF. i of Terminal and D flip-flop DFF i The D terminal is connected and generates the output signal QB. i The CLK input of the D flip-flop DFF0 is connected to the clock signal CLK. The D flip-flop DFF... N-1 of Terminal and D flip-flop DFF N-1 The D terminal is connected and generates the output signal QB. N-1 .

3. The multi-segment programmable soft-start circuit according to claim 1, characterized in that: The frequency division core module contains N XOR gates X0 to X1. N-1 N XOR gates X0 to X N-1 The first input terminal is sequentially and one-to-one connected to N control signals S0 to S1. N-1 Connect N XOR gates X0 to X N-1 The second input terminal is sequentially and one-to-one connected to N output signals QB0~QB N-1 Connection; when N is even, the frequency divider core module also contains N / 2 N / N OR gates Y0 to Y10. N / 2-1 A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. j The two input terminals are connected, where j = 0, 1, ..., N / 2-1, and there are N / 2 N / N NOR gates Y0 to Y1. N / 2-1 The output terminal is connected one-to-one with the N / 2 input terminals of the multiplexer G0, and the output terminal of the multiplexer G0 generates a toggle control signal; when N is odd, the frequency divider core module also includes One or NOT gate Y0~ A multi-AND gate G0, an XOR gate X 2j The output terminal and the XOR gate X 2j+1 The outputs of the gates are respectively connected to the OR gate Y. j The two input terminals are connected, where j = 0, 1, ..., ... XOR gate N-1 The output of the AND-OR-NOT gate The first input is connected to the NOR gate. The second input terminal is grounded. One or NOT gate Y0~ The output terminal of the AND gate G0 Each input terminal is connected in a one-to-one correspondence, and the output terminal of the multiplexer G0 generates a toggle control signal.

4. The multi-segment programmable soft-start circuit according to claim 1, characterized in that: The logic toggle module includes NOR gate SR0, NOR gate SR1, NOT gate G1, AND gate G2, and NAND gate G3. The input of NOT gate G1 and the first input of NOR gate SR0 are connected to the clock signal CLK. The output of NOT gate G1 is connected to the first input of AND gate G2. The second input of AND gate G2 is connected to the toggle control signal. The output of AND gate G2 is connected to the second inputs of NOR gate SR1 and NAND gate G3. The output of NOR gate SR0 is connected to the first inputs of NOR gate SR1 and NAND gate G3 to generate a frequency-divided clock signal CLK_DIV. The output of NOR gate SR1 is connected to the second input of NOR gate SR0. The output of NAND gate G3 is connected to N D flip-flops DFF0 to DFF1. N-1 of End connection.

5. The multi-segment programmable soft-start circuit according to claim 1, characterized in that: The counter circuit contains M+1 D flip-flops dff0~dff M OR gate Z0, OR gate Z1, and multiplexed AND gate Z2, D flip-flops dff0~dff M The Q terminal generates a control signal SS k For the k-th D flip-flop dff k k=0, 1, 2, ..., M-2, D flip-flop dff k of Terminal and D flip-flop dff k The D terminal and the D flip-flop dff k+1 The CLK terminal of the D flip-flop dff0 is connected to the output of the OR gate Z0. M-1 of Terminal and D flip-flop dff M-1 The D terminal is connected to the first input terminal of OR gate Z0 and the first input terminal of OR gate Z1, which are connected to the frequency divider clock signal CLK_DIV. The second input terminal of OR gate Z0 is connected to the output terminal of multiplexer Z2 and D flip-flop dff. M The D terminal is connected, and the D flip-flop is dff. M The Q terminal of the OR gate Z1 and the second input of the D flip-flop dff0~dff M-1 The RST terminal is connected to generate the control signal SS_OVER, and the inputs of the multiplexer Z2 are sequentially connected to control signals SS0 to SS0. M-1 .

6. A multi-segment programmable soft-start circuit according to claim 5, characterized in that: The digital-to-analog converter circuit includes M+1 conversion branches, resistor RLP, and resistors R0 to R1. M-1 The k-th branch in the first M switching branches contains switch SS k-1 RH resistance k-1 , resistor RL k-1 and switch k=0, 1, 2, ..., M-1, switch SS k-1 One end is connected to the reference voltage V REF SS switch k-1 The other end is connected to resistor RH k-1 One end is connected to resistor RH k-1 The other end is connected to resistor RL k-1 One end is connected to resistor RL k-1 The other end is connected to the switch One end is connected to the switch. The other end is grounded, switch SS k-1 Control signal SS k-1 Control, switch Control signal Control, control signal SS k-1 and control signals For a pair of inverted signals, the (M+1)th conversion branch includes a switch SS_OVER, a resistor RHT, a resistor RLT, and a switch. One end of the switch SS_OVER is connected to the reference voltage V. REF The other end of switch SS_OVER is connected to one end of resistor RHT, the other end of resistor RHT is connected to one end of resistor RLT, and the other end of resistor RLT is connected to switch SS_OVER. One end is connected to the switch. The other end is grounded, and the switch SS_OVER is controlled by the control signal SS_OVER. Control signal Control, control signal SS_OVER and control signal This is a pair of inverted signals; one end of resistor RLP is connected to one end of resistor RL0, and the other end of resistor RLP is grounded. For the k-th resistor R... k-1 resistance R k-1 One end is connected to resistor RH k-1 The other end is connected to resistor R k-1 The other end is connected to resistor RH k The other end is connected to resistor R M-1 One end is connected to resistor RH M-1 The other end is connected to resistor R. M-1 The other end generates an output voltage V SS_REF .

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