A clock synchronization system

Abstract

This application relates to a clock synchronization system, comprising: a clock detection circuit configured to receive an external clock signal and generate a delay control signal; the delay control signal is valid when the external clock signal stops being provided and continues for a preset duration; a phase-locked loop (PLL) electrically connected to the clock detection circuit; including a frequency and phase detector, whose first input terminal is configured to receive an external clock signal or a reference clock signal, and whose second input terminal is configured to receive the output of the PLL, and is configured to compare the frequency or phase difference of the signals received at the two input terminals; and a pulse width limiting module electrically connected to the frequency and phase detector, configured to adjust the pulse width of its output control signal based on the relationship between the pulse width of the signal output by the frequency and phase detector and a preset time limit; a charge pump electrically connected to the pulse width limiting module; and a voltage-controlled oscillator electrically connected to the charge pump and the clock detection circuit.

Description

Technical Field

[0001] This invention relates to the field of clock control, and more particularly to a clock synchronization system. Background Technology

[0002] Power control integrated circuits are widely used in consumer electronics, automobiles, industrial control systems, and other fields. They are the core components of switching power supplies and often contain multiple power management chips working together to handle the core tasks of power conversion, distribution, and system regulation. The implementation of these control functions typically requires the integration of a phase-locked loop (PLL) within the power management chip to synchronize clock signals. The PLL is responsible for synchronizing external clock signals or using an internal reference clock signal to generate the PWM signal that drives the DC / DC converter to achieve power conversion. DC / DC converters are extremely sensitive to clock signal jitter; even a small fluctuation in the clock signal can lead to a sharp increase in output voltage ripple.

[0003] Figure 1 This is a schematic diagram of a traditional clock synchronization system. During clock signal switching, the frequency of the PLL output signal needs to be dynamically adjusted to follow the input clock signal CLK. The clock detection circuit outputs a control signal clk_det to indicate whether an external clock signal is connected to the clock synchronization system. For example, when the external clock signal CLK is connected, the control signal clk_det is valid. When the external clock signal CLK stops connecting, the control signal clk_det is invalid.

[0004] When the control signal clk_det is valid, the voltage-controlled current unit inside the voltage-controlled oscillator (VCO) flows in or out based on the difference between the voltage V_lpf and the reference voltage Vref, causing the current-mode relaxation oscillator to adjust its output frequency to synchronize with the external clock signal frequency. When the control signal clk_det is invalid, the PLL stops synchronization locking, and the electrical connection between the voltage-controlled current unit and the current-mode relaxation oscillator is quickly disconnected. The current-mode relaxation oscillator then generates its internal reference clock signal based on the current provided by its internal current source. Because the internal reference clock signal of the PLL and the external clock signal may differ significantly in frequency, switching between the two clocks can cause the current-mode relaxation oscillator to fluctuate dramatically due to rapid current changes. This results in drastic changes in the frequency of the clock signal output by the PLL, causing overshoot in the DC / DC converter output voltage and potentially damaging the load.

[0005] In some improved solutions, when the external clock signal stops being connected to the clock synchronization system, the control signal clk_det output by the clock detection circuit is used to start the auxiliary circuit outside the PLL. The auxiliary circuit then slowly adjusts the voltage V_lpf to achieve a smooth transition of the clock signal output by the clock synchronization system. However, when the external clock signal CLK is connected to the clock synchronization system, the transition time when the clock synchronization system switches from the internal reference clock signal to the external clock signal is related to the PLL loop lock-in time and cannot be arbitrarily set. Therefore, these improved solutions cannot achieve a smooth transition of the clock frequency when the external clock signal is loaded. Summary of the Invention

[0006] To address the technical problems existing in the prior art, this application proposes a clock synchronization system, characterized by comprising: a clock detection circuit configured to receive an external clock signal and generate a delay control signal; the delay control signal is valid when the external clock signal stops being provided and continues for a preset duration; a phase-locked loop (PLL) electrically connected to the clock detection circuit, configured to receive and lock the external clock signal when the PLL is in a synchronization-locked state; configured to receive and lock the reference clock signal when the external clock signal stops being provided, and the delay control signal remains valid; at the end of the valid pulse of the delay control signal, the PLL enters a stop-synchronization-locked state and is configured to output an internal reference clock signal; wherein the reference clock signal is the same as the internal reference clock signal of the PLL; wherein the PLL includes a detection... A frequency-phase detector, with its first input configured to receive the external clock signal or reference clock signal and its second input configured to receive the output of the phase-locked loop, is configured to compare the frequency or phase difference of the signals received at the two inputs; a pulse width limiting module, electrically connected to the frequency-phase detector, is configured to adjust the pulse width of its output control signal based on the relationship between the pulse width of the signal output by the frequency-phase detector and a preset time limit; a charge pump, electrically connected to the pulse width limiting module, is configured to output a current signal based on the control signal output by the pulse width limiting module; and a voltage-controlled oscillator, electrically connected to the charge pump and the clock detection circuit, with its output electrically connected to the second input of the frequency-phase detector, is configured to generate the output of the phase-locked loop based at least on the current signal or a variation thereof.

[0007] Specifically, the clock synchronization system is characterized in that, when the pulse width of the signal output by the frequency and phase detector is greater than or equal to a predetermined time, the pulse width of the control signal output by the pulse width limiting module is equal to a preset predetermined time length; when the pulse width of the signal output by the frequency and phase detector is less than the predetermined time, the pulse width of the control signal output by the pulse width limiting module is equal to the pulse width of the signal output by the frequency and phase detector.

[0008] In particular, the clock synchronization system is characterized in that the duration of the delay control signal being in an active state is greater than or equal to the transition time when the phase-locked loop output clock signal is synchronized from the external clock signal to the reference clock signal.

[0009] Specifically, the clock synchronization system is characterized in that the value of the time limit is greater than or equal to the minimum pulse width of the signal output by the frequency and phase detector, and less than the clock period of the reference clock signal.

[0010] Specifically, the clock synchronization system is characterized in that the signal output by the frequency and phase detector includes a first control signal and a second control signal; the signal adjustment unit of the pulse width limiting module limits the pulse width of the first control signal and generates a third control signal; or, the signal adjustment unit limits the pulse width of the second control signal and generates a fourth control signal; wherein, the signal adjustment unit includes: an adjustment unit NOT gate, whose input signal includes the first control signal or the second control signal output by the frequency and phase detector; an adjustment unit first transistor, whose control electrode is configured to receive a bias voltage, whose second electrode is configured to receive a power supply voltage, and whose first transistor is configured to provide current; an adjustment unit second transistor, whose control electrode is electrically connected to the output terminal of the adjustment unit NOT gate, and whose second electrode is electrically connected to the first electrode of the adjustment unit first transistor; and an adjustment unit third transistor, whose control electrode is electrically connected to the adjustment unit NOT gate. The output terminal of the adjustment unit is connected to the control electrode of the second transistor of the adjustment unit, and its first electrode is electrically connected to the first electrode of the second transistor of the adjustment unit, and its second electrode is grounded; the adjustment unit capacitor is electrically connected between the first electrode and the second electrode of the third transistor of the adjustment unit; its first plate is electrically connected between the first electrode of the third transistor of the adjustment unit and the first electrode of the second transistor of the adjustment unit; the adjustment unit flip-flop has its input terminal electrically connected to the first plate of the adjustment unit capacitor, configured to switch the potential of the first plate of the adjustment unit capacitor; the adjustment unit NOR gate has its first input terminal electrically connected to the output terminal of the adjustment unit flip-flop, and its second input terminal electrically connected to the output terminal of the adjustment unit NOT gate; wherein, the first transistor and the second transistor of the adjustment unit are of the same type, and the type of the third transistor of the adjustment unit is opposite to that of the first transistor and the second transistor of the adjustment unit.

[0011] Specifically, the clock synchronization system is characterized by further including a clock switching circuit electrically connected to the clock detection circuit, configured to select the external clock or reference clock signal for output based on the delay control signal output by the clock detection circuit.

[0012] Specifically, the clock synchronization system is characterized in that the clock detection circuit includes: a first detection branch configured to detect an external clock signal and generate a first detection signal; including a first branch current source configured to receive a power supply voltage and provide current; a first branch transistor whose control electrode receives the external clock signal, whose first electrode is electrically connected to the output terminal of the first branch current source, and whose second electrode is grounded; a first branch capacitor whose first plate is electrically connected between the first electrode of the first branch transistor and the output terminal of the first branch current source, and whose second plate is electrically connected to the second electrode of the first branch transistor; a first branch trigger electrically connected between the first plate of the first branch capacitor and the output terminal of the first branch current source, configured to generate the first detection signal based on the voltage of the first plate of the first branch capacitor; and a second detection branch configured to detect an external clock signal and generate a second detection signal; including a second branch current source configured to receive a power supply voltage and provide current; a second branch transistor whose control electrode receives the external clock signal, and whose first electrode is electrically connected to the output terminal of the second branch current source. The first branch capacitor has a first terminal, with its second terminal grounded; the second branch capacitor has its first plate electrically connected between the first terminal of the second branch transistor and the output terminal of the second branch current source, and its second plate electrically connected to the second terminal of the second branch transistor; the second branch flip-flop has its first terminal electrically connected between the output terminal of the second branch current source and the first plate of the second branch capacitor, configured to generate a second detection signal based on the voltage of the first plate of the second branch capacitor; the detection circuit NOT gate has its first input terminal electrically connected to the output terminal of the detection circuit NOT gate, and its second input terminal electrically connected to the output terminal of the second branch flip-flop, the detection circuit AND gate is configured to receive the first detection signal and the second detection signal and perform an AND operation on them; wherein, the capacitance values ​​of the first branch capacitor and the second branch capacitor are different; when the external clock signal stops loading, there is a time difference between the moment when the second detection signal and the first detection signal become valid, and the delay control signal is valid within the time difference.

[0013] Specifically, the clock synchronization system is characterized in that the capacitance value of the first branch capacitor is greater than the capacitance value of the second branch capacitor.

[0014] Specifically, the clock synchronization system is characterized in that the clock switching circuit includes: a first NOR gate configured to receive an external clock signal and a delay control signal from the clock detection circuit, and perform a logical NOR operation on the two; a NOT gate configured to receive a reference clock signal and perform a logical NOT operation on it; an AND gate configured to receive the output of the NOT gate and the delay control signal, and perform a logical AND operation on the two; and a second NOR gate configured to receive the outputs of the first NOR gate and the AND gate, and perform a logical NOR operation on the two.

[0015] Specifically, the clock synchronization system is characterized in that the phase-locked loop further includes a current-to-voltage conversion module electrically connected to the output terminal of the charge pump, configured to convert the current signal output by the charge pump into a voltage signal; a voltage-controlled oscillator also electrically connected to the current-to-voltage conversion module and the clock detection circuit; including a voltage-controlled current unit, whose first input terminal is electrically connected between the charge pump and the current-to-voltage conversion module, and whose second input terminal is configured to receive a reference voltage; a first switch electrically connected between the first input terminal and the second input terminal of the voltage-controlled current unit; and a second switch and an oscillator, the second switch being electrically connected between the output terminal of the voltage-controlled current unit and the input terminal of the oscillator; wherein the first switch and the second switch are configured to be switched on and off under the control of the first detection signal, and the two cooperate to change the operating state of the phase-locked loop.

[0016] Specifically, the clock synchronization system is characterized in that when the first detection signal generated by the clock detection circuit changes to invalid, the first switch is opened and the second switch is closed; or, when the first detection signal generated by the clock detection circuit changes to valid, the first switch is closed and the second switch is opened.

[0017] This application also relates to an electronic device characterized by including a clock synchronization system as described in any of the preceding applications.

[0018] The clock synchronization system proposed in this application solves the problem of reduced output stability of switching power supplies caused by sudden changes in clock signals during clock switching, making the clock switching transition time adjustable and improving the stability and reliability of power management chips. Attached Figure Description

[0019] The preferred embodiments of this application will now be described in further detail with reference to the accompanying drawings, wherein:

[0020] Figure 1 The diagram shown is a schematic of a traditional clock synchronization system.

[0021] Figure 2The diagram shown is a schematic diagram of a clock signal synchronization process according to an embodiment of this application;

[0022] Figure 3 The diagram shown is a schematic diagram of a clock synchronization system according to an embodiment of this application;

[0023] Figure 4 The diagram shows a clock detection circuit according to an embodiment of this application;

[0024] Figure 5 for Figure 4 The diagram shows the timing sequence of the clock detection circuit.

[0025] Figure 6 The diagram shown is a schematic diagram of a clock switching circuit structure according to an embodiment of this application.

[0026] Figure 7 The diagram shown is a schematic diagram of the signal adjustment unit structure in a pulse width limiting module according to an embodiment of this application;

[0027] Figure 8 for Figure 3 The diagram shows a timing sequence of a clock synchronization system.

[0028] Figure 9 for Figure 3 Another timing diagram of the clock synchronization system shown. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0031] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0032] The clock synchronization system proposed in this application can adjust the transition time when the clock signal is switched, which solves the problem of reduced output stability of the switching power supply caused by sudden changes in the clock signal during clock switching. It realizes soft switching of the clock signal, improves the stability, reliability and lifespan of the power supply chip, and makes the DC-DC constant voltage or constant current output change tend to be smooth.

[0033] In traditional schemes, the lock-on time of the phase-locked loop (PLL) to the clock signal is related to the characteristics of its internal frequency and phase detector. The control signals UP and DN output by the frequency and phase detector control the charge pump to achieve charging and discharging behavior. When the frequency and phase difference between the external clock signal and the internal reference clock signal of the PLL is large, the pulse widths of the control signals UP and DN are also large, which in turn affects the rate of change of the voltage V_lpf after integration by the low-pass filter, and causes large fluctuations in the output frequency of the voltage-controlled oscillator (VCO). Furthermore, the characteristics of the frequency and phase detector are related to the stability of the PLL loop and cannot be arbitrarily changed.

[0034] Figure 2 The diagram shown is a schematic diagram of a clock signal synchronization process according to an embodiment of this application.

[0035] According to one embodiment, the external clock signal is divided into an external high-frequency clock signal with a frequency higher than the internal reference clock signal of the phase-locked loop, and an external low-frequency clock signal with a frequency lower than the internal reference clock signal of the phase-locked loop.

[0036] According to one embodiment, the frequency and phase of the reference clock signal are approximately the same as or equal to the frequency and phase of the internal reference clock signal of the phase-locked loop.

[0037] When no external clock signal is input, the clock signal output by the clock synchronization system (hereinafter referred to as the system) in this application is an internal reference clock signal that is substantially the same as the reference clock signal. When an external clock signal is present, the external clock signal is loaded into the clock synchronization system, and the system begins to synchronize and lock onto the external clock signal. After a first transition time, the clock signal output by the system switches to the external clock signal. When the external clock signal stops loading, the system begins to synchronize and lock onto the reference clock signal. After a second transition time, the clock switching action is completed, and the system continuously provides an internal reference clock signal that is substantially the same as the reference clock signal.

[0038] The clock synchronization system proposed in this application includes a phase-locked loop (PLL), within which a pulse width limiting module is incorporated. During clock switching, the pulse width limiting module adjusts the control signal output by the frequency and phase detector, limiting its maximum pulse width. This controls the output current of the charge pump, slowing down the rate of change of the voltage-controlled oscillator (VCO) input voltage. This extends the first or second transition time of the PLL during synchronization locking, mitigating the impact on the controllable switch caused by a short transition time and excessively fast frequency switching.

[0039] During clock signal switching, the external clock detection circuit of the phase-locked loop (PLL) works in conjunction with the clock switching circuit to enable the clock synchronization system to lock onto the clock signal. The clock detection circuit controls the PLL to enable or disable synchronization locking. This change does not affect the PLL's response speed. Under the control of the clock detection circuit, the clock switching circuit outputs an external clock signal or a reference clock signal. After the external clock signal stops loading, the clock detection circuit controls the clock switching circuit to provide the reference clock signal to the PLL and generates a duration exceeding the second transition time, ensuring that the PLL completes synchronization locking with the reference clock signal before being shut down. Since the internal reference clock signal of the PLL is the same as the reference clock signal, after the PLL is shut down, the clock signal output by the PLL is its internal reference clock signal.

[0040] In the following detailed description, the effective level can be either high or low, depending on the circuit. High levels will be described as effective levels, and low levels as ineffective levels.

[0041] Figure 3 The diagram shown is a schematic diagram of a clock synchronization system according to an embodiment of this application.

[0042] According to one embodiment, the clock synchronization system may include a clock detection circuit 31, configured to receive an external clock signal CLK, determine whether the external clock signal CLK has started loading into the clock synchronization system, and generate a delay control signal CLK_SEL and a first detection signal CLK_detl that changes the operating state of the clock synchronization system. When the external clock signal CLK stops loading, the delay control signal CLK_SEL is active. The duration t_delay when the delay control signal CLK_SEL is active affects the duration of the clock synchronization system switching from a synchronization-locked state to a de-synchronization-locked state.

[0043] In one embodiment, the effective state duration t_delay of the delay control signal CLK_SEL is greater than the second transition time to ensure that the phase-locked loop can complete the synchronous locking of the reference clock signal CLK_REF.

[0044] In another embodiment, when the external clock signal CLK stops loading, the delay control signal CLK_SEL output by the clock detection circuit 31 jumps to an active state, marking the beginning of the second transition time for the clock synchronization system to synchronize and lock the reference clock signal CLK_REF.

[0045] According to one embodiment, when an external clock signal is loaded, the first detection signal CLK_detl jumps to a failure state, controlling the clock synchronization system to enter a synchronization lock state.

[0046] According to one embodiment, in a synchronization-locked state, the clock synchronization system synchronizes and locks the received clock signal, ensuring that its output clock signal maintains a frequency and phase approximately the same as or equal to that of the received clock signal. The clock signal received by the clock synchronization system may include an external clock signal CLK and a reference clock signal CLK_REF.

[0047] According to one embodiment, when the first detection signal CLK_detl transitions to an active state, the clock synchronization system stops its synchronization locking operation. The clock signal CLK_VCO provided externally by the clock synchronization system is an internal reference clock signal that is similar to or the same as the reference clock signal CLK_REF.

[0048] According to one embodiment, the clock synchronization system may further include a clock switching circuit 32 electrically connected to the clock detection circuit 31, configured to receive an external clock signal CLK, a reference clock signal CLK_REF, and a delay control signal CLK_SEL output by the clock detection circuit 31, and select either the reference clock signal CLK_REF or the external clock signal CLK as the clock signal CLK_OUT for output based on the state of the delay control signal CLK_SEL.

[0049] According to one embodiment, when the external clock signal CLK is loaded into the clock synchronization system, the delay control signal CLK_SEL output by the clock detection circuit 31 becomes invalid, and the clock signal CLK_OUT output by the clock switching circuit 32 becomes the external clock signal CLK.

[0050] According to one embodiment, when the external clock signal CLK stops loading, the delay control signal CLK_SEL jumps to active, and the clock signal CLK_OUT output by the clock switching circuit 32 is the reference clock signal CLK_REF.

[0051] According to one embodiment, the clock synchronization system may further include a reference clock signal generation circuit (not shown) electrically connected to the clock switching circuit 32, configured to generate a reference clock signal CLK_REF that is similar to or the same as the internal reference clock signal of the phase-locked loop.

[0052] According to one embodiment, the clock synchronization system further includes a phase-locked loop 33 electrically connected to the clock switching circuit 32, configured to receive a clock signal CLK_OUT from the clock switching circuit 32 and a clock signal CLK_VCO output by the phase-locked loop itself, and to keep the frequency (or phase) of the clock signal CLK_VCO output by the phase-locked loop synchronized with the frequency (or phase) of the clock signal CLK_OUT received by the phase-locked loop.

[0053] According to one embodiment, the phase-locked loop 33 may include a frequency and phase detector 331, whose first input is configured to receive a clock signal CLK_OUT from the clock switching circuit 32, and whose second input is configured to receive a clock signal CLK_VCO output by the phase-locked loop 33 itself. The frequency and phase detector 331 is configured to compare the frequency and phase of the signals received at the two inputs and generate a first control signal UP and a second control signal DN representing the frequency and phase difference between the two signals.

[0054] According to one embodiment, the phase-locked loop 33 may further include a pulse width limiting module 332 electrically connected to the frequency and phase detector 331, configured to receive a first control signal UP and / or a second control signal DN output by the frequency and phase detector 331, limit the pulse width of both, and generate corresponding third control signal P1 and fourth control signal P2. By limiting the maximum pulse width of the first control signal UP and the second control signal DN, the transition time during clock signal switching is extended. The transition time includes a first transition time when the reference clock signal switches to an external clock signal, and a second transition time when switching from an external clock signal to the reference clock signal.

[0055] According to one embodiment, the pulse widths of the third control signal P1 and the fourth control signal P2 are less than or equal to a specified time t_limit. The specified time t_limit is less than the clock period of the reference clock signal CLK_REF. The smaller the value of the specified time t_limit, the longer the transition time during clock switching. The specific value of the specified time t_limit can be set according to actual needs.

[0056] According to one embodiment, when the clock signal output by the phase-locked loop 33 is synchronously locked to the clock signal CLK_OUT, the pulse width of the first control signal UP or the second control signal DN output by the frequency and phase detector 331 is its minimum pulse width. The value of the time limit t_limit is greater than or equal to the minimum value of the minimum pulse width of the first control signal UP or the minimum pulse width of the second control signal DN to ensure the normal operation of the phase-locked loop.

[0057] According to one embodiment, the pulse width limiting module 332 includes a first adjustment unit 3321 and a second adjustment unit 3322. The first adjustment unit 3321 is configured to receive a first control signal UP, adjust its pulse width, and generate a third control signal P1. The second adjustment unit 3322 is configured to receive a second control signal DN, adjust its pulse width, and generate a fourth control signal P2.

[0058] In one embodiment, the first adjustment unit 3321 and the second adjustment unit 3322 may have the same or similar structures.

[0059] According to one embodiment, when the pulse width of the first control signal UP or the second control signal DN is greater than or equal to the value of the time limit t_limit, the first adjustment unit 3321 will clamp the pulse width of the output third control signal P1 to around the time limit t_limit, or the second adjustment unit 3322 will clamp the pulse width of the output fourth control signal P2 to around the time limit t_limit.

[0060] According to one embodiment, when the pulse width of the first control signal UP or the second control signal DN is less than the value of the time limit t_limit, the pulse width of the third control signal P1 output by the first adjustment unit 3321 is kept to be substantially similar to or equal to the pulse width of the first control signal UP. Alternatively, the second adjustment unit 3322 will keep the pulse width of the output fourth control signal P2 substantially similar to or equal to the pulse width of the second control signal DN.

[0061] According to one embodiment, the phase-locked loop 33 may further include a charge pump 333 electrically connected to the pulse width limiting module 332, configured to receive a third control signal P1 and a fourth control signal P2 from the pulse width limiting module 332, and output a current Icp under the control of the third control signal P1 and the fourth control signal P2, which contain frequency (or phase) difference information.

[0062] According to one embodiment, the charge pump 333 includes: a current source 3331 configured to receive a power supply voltage VDD; a first terminal of a switch S3332 electrically connected to the output terminal of the current source 3331, and a second terminal electrically connected to the first terminal of a switch S3334, i.e., node A; and a second terminal of a switch S3334 electrically connected to the input terminal of a current source 3335, the output terminal of the current source 3335 being grounded.

[0063] According to one embodiment, node A can serve as the output terminal of charge pump 333, and current Icp can flow into or out of node A.

[0064] According to one embodiment, switch S3332 is configured to be switched on and off under the control of a third control signal P1. When the third control signal P1 is valid, and switch S3332 is closed, current source 3331 outputs current Icp to node A, and current Icp is a positive value.

[0065] In another embodiment, switch S3334 is configured to be switched on and off under the control of a fourth control signal P2. When the fourth control signal P2 is active, switch S3334 is closed, and current Icp flows from node A into charge pump 333, with a negative current Icp. In this case, the phase-locked loop discharges charge through current source 3335.

[0066] According to one embodiment, the phase-locked loop 33 may also include a current-to-voltage conversion module 334 electrically connected to node A, which may be embodied as a low-pass filter configured to convert the current Icp output by the charge pump 333 into a voltage V_lpf.

[0067] According to one embodiment, the phase-locked loop 33 may further include a voltage-controlled oscillator 335 electrically connected to node A, configured to adjust its output clock signal CLK_VCO under the drive of voltage V_lpf, and feed it back as the output of the phase-locked loop 33 to the input of the frequency-phase discriminator 331. The voltage-controlled oscillator 335 is also electrically connected to a clock detection circuit 31 (not shown).

[0068] According to one embodiment, the voltage-controlled oscillator 335 may include a voltage-controlled current unit 3351 and a first switch S3352, as well as a second switch S3353 and an oscillator 3354. The oscillator 3354 may be a current-mode relaxation oscillator. A first input terminal of the voltage-controlled current unit 3351 is electrically connected to node A, and its second input terminal is configured to receive a reference voltage Vref. The first switch S3352 is electrically connected between the first and second input terminals of the voltage-controlled current unit 3351. The second switch S3353 is electrically connected between the output terminal of the voltage-controlled current unit 3351 and the input terminal of the oscillator 3354. The voltage-controlled current unit 3351 is configured to receive the reference voltage Vref and a voltage V_lpf provided by the current-to-voltage conversion module 334, compare the two, and output a current Igm based on the difference between them. The current Igm may flow into or out of the voltage-controlled current unit. The first switch S3352 and the second switch S3353 are configured to be switched on and off under the control of the first detection signal CLK_detl, and the two work together to change the operating state of the phase-locked loop 33. The oscillator 3354 is configured to adjust its output clock signal CLK_VCO based on the current Igm output by the voltage-controlled current unit 3351.

[0069] According to one embodiment of this application, when the external clock signal CLK is loaded, the first switch S3352 is open and the second switch S3353 is closed. In this case, the phase-locked loop is in a synchronous locking state, synchronously locking the clock signal CLK_OUT from the clock switching circuit 32.

[0070] In another embodiment, after the external clock signal CLK terminates loading and a duration t_delay has elapsed, the first switch S3352 closes and the second switch S3353 opens. In this case, the phase-locked loop is in a stopped synchronization locked state, and its output clock signal CLK_VCO is an internal reference clock signal that is substantially similar to or the same as the reference clock signal CLK_REF.

[0071] In some embodiments of this application, the structure of the reference clock signal generation circuit can be consistent with the structure of the oscillator 3354.

[0072] When the clock signal switches, the pulse width limiting module processes the control signal output by the frequency and phase detector. The output of the pulse width limiting module adjusts the switching time in the charge pump, slowing down the increase or decrease of the voltage V_lpf obtained after processing by the current-to-voltage conversion module 334. This, in turn, adjusts the frequency of the voltage-controlled oscillator's output clock signal CLK_VCO, achieving a smooth switching of the clock signal.

[0073] Figure 4The diagram shows a clock detection circuit according to one embodiment of this application. The clock detection circuit may also have other structures, which are not limited thereto.

[0074] According to one embodiment, the clock detection circuit may include a first detection branch electrically connected to its input, configured to receive an external clock signal CLK and generate a first detection signal CLK_detl when the external clock signal is applied.

[0075] According to one embodiment, when an external clock signal is applied, the first detection signal CLK_detl transitions to an inactive state. When the external clock signal stops applying and a duration t_delay has elapsed, the first detection signal CLK_detl transitions to an active state.

[0076] According to one embodiment, the first transition time and the second transition time are related to the phase-locked loop response time and the minimum pulse width of the first control signal UP and the second control signal DN output by the frequency and phase detector. After determining the first transition time and the second transition time, the duration t_delay of the effective state of the delay control signal CLK_SEL can be set according to actual needs.

[0077] According to one embodiment, the clock detection circuit may further include a second detection branch electrically connected to its input, configured to receive an external clock signal CLK and generate a second detection signal CLK_dets when the external clock signal is applied. The second detection signal CLK_dets indicates whether the external clock signal CLK is connected to the clock synchronization system.

[0078] According to one embodiment, the second detection signal CLK_dets is valid when the external clock signal CLK is no longer connected. The second detection signal CLK_dets is invalid when the external clock signal CLK is present.

[0079] According to one embodiment, the first detection branch includes: a first branch current source 401 configured to receive a power supply voltage VDD and provide a current Ib1; a first branch transistor T402, whose first electrode is electrically connected to the output terminal of the first branch current source 401, whose control electrode is configured to receive an external clock signal CLK, and whose second electrode is grounded; and a first branch capacitor C403, whose first plate is electrically connected between the first electrode of the first branch transistor T402 and the output terminal of the first branch current source 401, and whose second plate is electrically connected to the second electrode of the first branch transistor T402. The first detection branch may further include a first branch trigger 404, whose input terminal is electrically connected between the output terminal of the first branch current source 401 and the first plate of the first branch capacitor C403, configured to generate a first detection signal CLK_detl based on the voltage VCL of the first plate of the first branch capacitor C403.

[0080] According to one embodiment, when the voltage VCL of the first plate of the first branch capacitor C403 rises and exceeds the positive threshold voltage Vth1 of the first branch trigger 404, the output of the first branch trigger 404 jumps to a high level, thereby causing the first detection signal CLK_detl to become active. When the voltage VCL of the first plate of the first branch capacitor C403 falls and falls below the reverse threshold voltage Vth1' of the first branch trigger 404, the first detection signal CLK_detl becomes inactive.

[0081] According to one embodiment, the first detection branch may have a similar structure to the second detection branch.

[0082] According to one embodiment, the second detection branch may include: a second branch current source 405 configured to receive a power supply voltage VDD and provide a current Ib2; a second branch transistor T406, the first terminal of which is electrically connected to the output terminal of the second branch current source 405, the control terminal of which is configured to receive an external clock signal CLK, and the second terminal of which is grounded; and a second branch capacitor C407, the first plate of which is electrically connected between the first terminal of the second branch transistor T406 and the output terminal of the second branch current source 405, and the second plate of which is electrically connected to the second terminal of the second branch transistor T406. The second detection branch may further include a second branch trigger 408, the input terminal of which is electrically connected between the first plate of the second branch capacitor C407 and the output terminal of the second branch current source 405, configured to generate a second detection signal CLK_dets based on the voltage VCS of the first plate of the second branch capacitor C407.

[0083] According to one embodiment, the clock detection circuit may further include a detection circuit NOT gate 409, electrically connected to the output of the first detection branch, configured to receive the first detection signal CLK_detl and perform a logical NOT operation on it; and a detection circuit AND gate 410, whose first input is electrically connected to the output of the detection circuit NOT gate 409 and whose second input is electrically connected to the output of the second branch flip-flop 408, configured to receive the output of the detection circuit NOT gate 409 and the second detection signal CLK_dets from the second detection branch, and perform a logical AND operation on the two to generate a delay control signal CLK_SEL.

[0084] According to one embodiment, when the voltage VCS of the first plate of the second branch capacitor C407 increases and exceeds the positive threshold voltage Vth2 of the second branch trigger 408, the output of the second branch trigger 404 changes, thereby causing the second detection signal CLK_dets to become active. When the voltage VCS of the first plate of the second branch capacitor C407 decreases and falls below the reverse threshold voltage Vth2' of the second branch trigger 408, the second detection signal CLK_dets becomes inactive.

[0085] According to one embodiment, when the external clock signal CLK is loaded, both the first detection signal CLK_detl and the second detection signal CLK_dets are in a disabled state. In this case, the delay control signal CLK_SEL is also in a disabled state.

[0086] According to another embodiment, when the external clock signal CLK stops loading, the second detection signal CLK_dets becomes active before the first detection signal CLK_detl. In this case, the delay control signal CLK_SEL also becomes active and continues until the first detection signal CLK_detl becomes active.

[0087] According to one embodiment, the first branch trigger 404 and the second branch trigger 408 can be Schmitt triggers of the same type. The first branch trigger 404 and the second branch trigger 408 can have similar or equal positive threshold voltages and reverse threshold voltages.

[0088] According to one embodiment, the values ​​of the currents provided by the first branch current source 401 and the second branch current source 405 can be substantially similar or equal.

[0089] According to one embodiment, the capacitance values ​​of the first branch capacitor C403 and the second branch capacitor C407 can be different. Because of the difference in capacitance values ​​between the first branch capacitor C403 and the second branch capacitor C407, the rise rates of voltage VCL and voltage VCS are different. Therefore, there is a time difference between the moment when voltage VCL drives the output of the first branch trigger 404 to change and the moment when voltage VCS drives the output of the second branch trigger 408 to change. During this time difference, the delay control signal CLK_SEL is valid.

[0090] According to one embodiment, the duration t_delay when the delay control signal CLK_SEL is in an active state is related to the capacitance value C1 of the first branch capacitor C403, the positive threshold Vth1 of the first branch trigger 404, and the current Ib1 provided by the first branch current source 401. The duration t_delay can be expressed as... At this point, the currents provided by the first branch current source 401 and the second branch current source 405 are basically similar or equal. By changing the capacitance value of the first branch capacitor C403, the duration of the effective state of the delay control signal CLK_SEL can be adjusted, making it more convenient for the user to control the working state of the clock synchronization system. It is understandable that the duration t_delay can also be adjusted by changing the capacitance value of the second branch capacitor C407.

[0091] According to one embodiment, the capacitance value of the first branch capacitor C403 is greater than the capacitance value of the second branch capacitor C407.

[0092] In another embodiment, the capacitance value of the first branch capacitor C403 may also be less than the capacitance value of the second branch capacitor C407. In this case, the output of the first detection branch can be used as the second detection signal CLK_dets, and the output of the second detection branch can be used as the first detection signal CLK_detl.

[0093] Understandably, the currents provided by the first branch current source 401 and the second branch current source 405 may not be equal. Regardless of the currents provided by the first branch current source 401 and the second branch current source 405, the duration of the effective state of the delay control signal can be adjusted.

[0094] By utilizing the difference in capacitance values ​​between the first branch capacitor C403 and the second branch capacitor C407, and / or the difference in current values ​​provided by the first branch current source 401 and the second branch current source 405, the transition times of the first detection signal CLK_dets and the second detection signal CLK_detl when the external clock signal stops being connected are adjusted, thereby adjusting the duration of the effective delay control signal to ensure that the clock signal switching is completed before the phase-locked loop is closed.

[0095] Figure 5 for Figure 4 The diagram shows the timing sequence of the clock detection circuit. The following describes the operation of the clock detection circuit during clock switching.

[0096] (1) Time interval t1-t2:

[0097] An external clock signal CLK is loaded into the clock synchronization system, and the external clock signal CLK transitions between a valid state and a invalid state.

[0098] When the external clock signal CLK is valid, the first branch transistor T402 and the second branch transistor T406 are turned on. In the first detection branch, the voltage VCL of the first plate of the first branch capacitor C403 drops to zero, which is lower than the reverse threshold voltage Vth1' of the first branch flip-flop 404. The output of the first branch flip-flop 404 jumps low, and the first detection signal CLK_detl becomes inactive. In the second detection branch, the voltage VCS of the first plate of the second branch capacitor C407 drops to zero, which is lower than the reverse threshold voltage Vth2' of the second branch flip-flop 408. The output of the second branch flip-flop 408 goes low, and the second detection signal CLK_dets also becomes inactive.

[0099] When the external clock signal fails, both the first branch transistor T402 and the second branch transistor T406 are turned off. In the first detection branch, the voltage VCL of the first plate of the first branch capacitor C403 gradually increases. Before reaching the positive threshold voltage Vth1 of the first branch flip-flop 404, the external clock signal CLK becomes active, and the output of the first branch flip-flop 404 remains low. The first detection signal CLK_detl remains inactive. In the second detection branch, the voltage VCS of the first plate of the second branch capacitor C407 gradually increases. Before the external clock signal CLK becomes active, the value of voltage VCS has not reached the positive threshold voltage Vth2 of the second branch flip-flop 408, the output of the second branch flip-flop 408 remains low, and the second detection signal CLK_detl remains inactive.

[0100] In this case, the delay control signal CLK_SEL is always in an inactive state.

[0101] (2) Time interval t2-t3:

[0102] The loading process of the external clock signal CLK has terminated. The external clock signal CLK received by the clock detection circuit is in a failed state.

[0103] In the first detection branch, transistor T402 is turned off, and current source 401 charges the first plate of capacitor C403, causing voltage VCL to gradually rise. In the second detection branch, transistor T406 is turned off, and voltage VCS of the first plate of capacitor C407 rises.

[0104] Because the capacitance of the first branch capacitor C403 is greater than that of the second branch capacitor C407, the rise rate of voltage VCS is higher than that of voltage VCL. When the value of voltage VCS exceeds the positive threshold voltage Vth2 of the second branch trigger 408, the output of the second branch trigger 408 jumps high, and the second detection signal CLK_dets becomes valid. At this time, voltage VCL has not yet reached the positive threshold voltage Vth1 of the first branch trigger 404, and the first detection signal CLK_detl remains in an inactive state.

[0105] In this situation, the delay control signal CLK_SEL switches to an active state. In the first detection branch, the voltage VCL continues to rise.

[0106] (3) Time t3:

[0107] The second detection signal CLK_dets is still valid.

[0108] In the first detection branch, if the voltage VCL is higher than the positive threshold voltage Vth1 of the first branch trigger 404, the output of the first branch trigger 404 will switch to high, and the first detection signal CLK_detl will switch to valid.

[0109] In this situation, the delay control signal CLK_sel transitions to an inactive state.

[0110] Figure 6 The diagram shown is a schematic representation of a clock switching circuit according to one embodiment of this application. The clock switching circuit may also have other structures, which are not limited herein.

[0111] According to one embodiment, the clock switching circuit may include a switching circuit first NOR gate 601, configured to receive an external clock signal CLK and a delay control signal CLK_SEL from a clock detection circuit, and perform a logical NOR operation on the two.

[0112] According to one embodiment, the clock switching circuit may include a switching circuit NOT gate 602 configured to receive a reference clock signal CLK_REF and perform a logical NOT operation on it.

[0113] According to one embodiment, the clock switching circuit may include a switching circuit AND gate 603 configured to receive the output of the switching circuit NOT gate 602 and the delay control signal CLK_SEL, and perform a logical AND operation on the two.

[0114] According to one embodiment, the clock switching circuit may include a second NOR gate 604 of the switching circuit, configured to receive the outputs of the first NOR gate 601 of the switching circuit and the AND gate 603 of the switching circuit, and perform a logical OR operation on the two.

[0115] Figure 7 The diagram shown is a schematic diagram of the signal adjustment unit structure in a pulse width limiting module according to an embodiment of this application. Figure 7 The structure shown can be used as Figure 3 The first adjustment unit 3321, which adjusts the first control signal UP, can also be used as the second adjustment unit 3322, which adjusts the second control signal DN. The signal adjustment unit in the pulse width limiting module can also have other structures, which are not limited in this application.

[0116] According to one embodiment, the signal adjustment unit may include an adjustment unit NOT gate 701, configured to receive an input signal Sin and perform a logical NOT operation on it. The input signal Sin may be a first control signal UP from a frequency and phase detector, or a second control signal DN output by the frequency and phase detector.

[0117] According to one embodiment, the signal conditioning unit may include a first conditioning transistor T702, the control electrode of which is configured to receive a bias voltage Vbias, and the second electrode of which is configured to receive a power supply voltage VDD. The first conditioning transistor T702 is configured to provide a current Ibl associated with the bias voltage Vbias.

[0118] According to one embodiment, the signal adjustment unit may further include a second transistor T703 of the adjustment unit, whose control electrode is electrically connected to the output terminal of the NOT gate 701 of the adjustment unit, and whose second electrode is electrically connected to the first electrode of the first transistor T702 of the adjustment unit.

[0119] According to one embodiment, the signal adjustment unit may further include a third transistor T704 and an adjustment unit capacitor C705. The control electrode of the third transistor T704 is electrically connected between the output terminal of the NOT gate 701 and the control electrode of the second transistor T703, its first electrode is electrically connected to the first electrode of the second transistor T703, and its second electrode is grounded. The adjustment unit capacitor C705 is electrically connected between the first and second electrodes of the third transistor T704, and its first plate is electrically connected between the first electrode of the third transistor T704 and the first electrode of the second transistor T703 (node ​​B).

[0120] According to one embodiment, the signal conditioning unit may include a conditioning unit trigger 706, the input of which is electrically connected to node B and configured to generate a corresponding signal based on the voltage condition of node B. The conditioning unit trigger 706 may be a Schmitt trigger.

[0121] According to one embodiment, the signal adjustment unit further includes an adjustment unit NOR gate 707, whose first input is electrically connected to the output of the adjustment unit flip-flop 706, and whose second input is electrically connected to the output of the adjustment unit NOT gate 701. The adjustment unit NOR gate 707 is configured to receive the outputs of the adjustment unit flip-flop 706 and the adjustment unit NOT gate 701, perform a logical NOR operation on the two, and generate a signal Sout.

[0122] In one embodiment of this application, the adjustment unit trigger 706 has a positive threshold voltage and a reverse threshold voltage that are approximately equal to or the same as those of the first branch trigger 404 and the second branch trigger 408 in the clock detection circuit.

[0123] According to one embodiment, the second transistor T703 and the third transistor T704 of the adjustment unit are not turned on at the same time.

[0124] According to one embodiment, the first transistor T702 and the second transistor T703 of the adjustment unit can be of the same type, such as P-type transistors.

[0125] According to one embodiment, the third transistor T704 of the adjustment unit can be an N-type transistor, which is the opposite type to the first transistor T702 and the second transistor T703 of the adjustment unit.

[0126] According to one embodiment, when the input signal Sin becomes active, the signal output by the NOT gate 701 of the adjustment unit becomes inactive. The second transistor T703 of the adjustment unit is turned on, and the first plate of the capacitor C705 of the adjustment unit begins to charge under the action of the current Ibl, and the potential of node B begins to gradually rise. When the potential of node B has not reached the positive threshold voltage Vth3 of the adjustment unit flip-flop 706, the output signal of the adjustment unit flip-flop 706 is inactive, and the output signal Sout of the adjustment unit NOR gate 707 is active. Subsequently, when the potential of node B rises to a level higher than the positive threshold voltage Vth3 of the adjustment unit flip-flop 706, the output signal of the adjustment unit flip-flop 706 becomes active, and the output signal Sout of the adjustment unit NOR gate 707 becomes inactive. The pulse width of the output signal Sout is less than or equal to the limited time t_limit.

[0127] According to one embodiment, the time limit t_limit can be expressed as: C3 is the capacitance value of the adjustment unit capacitor C705.

[0128] According to one embodiment, when the input signal Sin transitions to an invalid state, the signal output by the NOT gate 701 of the adjustment unit transitions to an valid state. The output signal Sout of the NOR gate 707 of the adjustment unit is in an invalid state.

[0129] By adjusting the capacitance value of the adjustment unit capacitor C705, the magnitude of the current Ibl, and the positive threshold voltage of the adjustment unit trigger 706, the time limit t_limit when the output signal Sout is in an active state is controlled, thereby making the first and second transition times adjustable when switching between the external clock signal and the reference clock signal.

[0130] Figure 8 for Figure 3 The diagram shows a timing sequence of a clock synchronization system. The external clock signal CLK has a higher frequency than the reference clock signal CLK_REF. Figure 3 The intermediate clock detection circuit can be Figure 4 The structure shown indicates that the pulse width limiting module can be... Figure 7 The structure is shown below. The following describes the working process of the clock synchronization system during clock switching.

[0131] (1) From time t1 to t2:

[0132] Before time t1, the clock signal CLK_VCO output by the phase-locked loop is essentially the same internal reference clock signal as the reference clock signal CLK_REF. Starting at time t1, the external clock signal CLK is loaded into the clock synchronization system, and the first detection signal CLK_detl and the second detection signal CLK_dets generated by the clock detection circuit 31 simultaneously switch to an inactive state, and the delay control signal CLK_SEL is in an inactive state.

[0133] Based on the delay control signal CLK_SEL, the clock switching circuit 32 outputs the external clock signal CLK as the clock signal CLK_OUT to the phase-locked loop 33.

[0134] Under the control of the first detection signal CLK_detl, the first switch S3352 is opened and the second switch S3353 is closed, and the phase-locked loop 33 enters the synchronous locking state.

[0135] In phase-locked loop 33, frequency and phase detector 331 compares the external clock signal CLK with the clock signal CLK_VCO from the output of phase-locked loop 33, generates a first control signal UP and a second control signal DN, and outputs them to pulse width limiting module 332. Since the frequency of the external clock signal CLK is higher than the frequency of the reference clock signal CLK_REF, the pulse width of the first control signal UP generated by frequency and phase detector 331 in phase-locked loop 33 is greater than the pulse width of the second control signal DN, and the pulse width of the first control signal UP is greater than the time limit t_limit.

[0136] The pulse width limiting module 332 limits the pulse width of the first control signal UP from the frequency and phase detector 331, restricting the pulse width of the first control signal UP to within a limited time t_limit, and outputs a third control signal P1 with a pulse width equal to the limited time t_limit. The pulse width of the second control signal DN is also within the limited time t_limit. Therefore, the pulse width of the fourth control signal P2 is basically similar to the pulse width of the second control signal DN. Since the pulse width of the third control signal P1 is greater than the pulse width of the fourth control signal P2, a current Icp flows outward from node A in the charge pump 333, and the value of the current Icp is positive.

[0137] The current-to-voltage conversion module 334 processes the current Icp and converts it into a voltage V_lpf. The value of the voltage V_lpf gradually increases and exceeds the reference voltage Vref, causing the frequency of the clock signal CLK_VCO output by the voltage-controlled oscillator 335 to gradually increase.

[0138] When the output clock signal CLK_VCO of the voltage-controlled oscillator 335 is synchronized with the external clock signal CLK, the clock signal output by the clock synchronization system is switched from the internal reference clock signal to the external clock signal CLK.

[0139] (2) Time interval t2-t3:

[0140] The external clock signal CLK continues to be loaded into the clock synchronization system, and the clock synchronization system continues to maintain synchronization lock on the external clock signal CLK.

[0141] (3) Time interval t3-t4:

[0142] Starting from time t3, the external clock signal CLK stops loading.

[0143] In the clock detection circuit 31, both voltage VCL and voltage VCS begin to gradually rise. When voltage VCS is higher than the positive threshold Vth2 of the second branch flip-flop 408, the second detection signal CLK_dets becomes active. At this time, voltage VCL is less than the positive threshold Vth1 of the first branch flip-flop 404, and the first detection signal CLK_detl remains inactive. The delay control signal CLK_SEL also becomes active.

[0144] In this case, the clock signal CLK_OUT output by the clock switching circuit 32 to the phase-locked loop 33 is the reference clock signal CLK_REF.

[0145] Phase-locked loop 33 receives a reference clock signal CLK_REF from clock switching circuit 32 and its output clock signal CLK_VCO. It uses a frequency and phase detector 331 to compare the frequencies and phases of the two signals and generates a first control signal UP and a second control signal DN. Since the frequency of the reference clock signal CLK_REF is lower than the frequency of the external clock signal CLK, the pulse width of the first control signal UP is less than the pulse width of the second control signal DN. Pulse width limiting module 332 processes the received first control signal UP and second control signal DN and generates a third control signal P1 and a fourth control signal P2 to control the output current Icp of the charge pump. The pulse width of the fourth control signal P2 is equal to the time limit t_limit, and the pulse width of the third control signal P1 is approximately similar to or the same as the pulse width of the first control signal UP. The pulse width of the third control signal P1 is less than the pulse width of the fourth control signal P2. The closing time of switch S3332 in charge pump 333 is less than the closing time of switch S3334. Current Icp flows from current-to-voltage conversion module 334 into node A in charge pump 333, causing the potential level of voltage V_lpf obtained after processing by current-to-voltage conversion module 334 to gradually decrease and fall below the reference voltage Vref. The output frequency of voltage-controlled oscillator 335 gradually decreases.

[0146] When the clock signal CLK_VCO output by the voltage-controlled oscillator 335 is synchronized with the reference clock signal CLK_REF, the clock synchronization system completes the synchronization lock of the reference clock signal CLK_REF.

[0147] During this process, the delay control signal CLK_SEL clock is in an active state.

[0148] (4) Time t4:

[0149] In the clock detection circuit, the voltage VCL continues to rise until it exceeds the positive threshold voltage Vth1 of the first branch flip-flop 404. At this point, the first detection signal CLK_detl becomes active, and the delay control signal CLK_SEL becomes inactive, indicating the end of the duration t_delay during which the delay control signal CLK_SEL is active. In the phase-locked loop 33, the first switch S3352 closes, and the second switch S3353 opens, stopping the phase-locked loop 33 from synchronizing with the clock signal CLK_OUT output by the clock switching circuit. The clock signal CLK_VCO output by the voltage-controlled oscillator 335 is essentially the same internal reference clock signal as the reference clock signal CLK_REF.

[0150] Figure 9 for Figure 3The diagram shows another timing sequence of the clock synchronization system. In this system, the frequency of the external clock signal CLK is lower than the frequency of the reference clock signal CLK_REF.

[0151] (1) From time t1 to t2:

[0152] Before time t1, the internal reference clock signal CLK_VCO output by the phase-locked loop is basically the same as the reference clock signal. Starting at time t1, the external clock signal CLK is loaded into the clock synchronization system, and the first detection signal CLK_detl and the second detection signal CLK_dets generated by the clock detection circuit 31 simultaneously switch to failure, and the delay control signal CLK_SEL is in a failure state.

[0153] When the delay control signal CLK_SEL fails, the clock switching circuit 32 outputs the external clock signal CLK as the clock signal CLK_OUT to the phase-locked loop 33.

[0154] Under the control of the first detection signal CLK_detl, the first switch S3352 is opened and the second switch S3353 is closed, and the phase-locked loop 33 enters the synchronous locking state.

[0155] In phase-locked loop 33, frequency and phase detector 331 compares the external clock signal CLK with the clock signal CLK_VCO from the output of phase-locked loop 33, generates a first control signal UP and a second control signal DN, and outputs them to pulse width limiting module 332. Since the frequency of the external clock signal CLK is lower than the frequency of the reference clock signal CLK_REF, the pulse width of the second control signal DN generated by frequency and phase detector 331 in phase-locked loop 33 is greater than the time limit t_limit.

[0156] The pulse width limiting module 332 limits the pulse width of the second control signal DN from the frequency and phase detector 331, and outputs a fourth control signal P2 with a pulse width equal to the limited time t_limit. The pulse width limiting module 332 also outputs a third control signal P1 with a pulse width approximately equal to that of the first control signal UP. Because the pulse width of the third control signal P1 is less than the pulse width of the fourth control signal P2, the closing time of switch S3332 in the charge pump 333 is less than the closing time of switch S3334, and the current Icp flows from the current-to-voltage conversion module 334 to the charge pump 333.

[0157] The current-to-voltage conversion module 334 processes the current Icp and converts it into a voltage V_lpf. The value of the voltage V_lpf gradually decreases and falls below the reference voltage Vref, causing the frequency of the clock signal output by the voltage-controlled oscillator 335 to gradually decrease.

[0158] When the output clock signal CLK_VCO of the voltage-controlled oscillator is synchronized with the external clock signal CLK, the clock synchronization system completes the synchronization lock of the external clock signal CLK.

[0159] (2) Time interval t2-t3:

[0160] The external clock signal CLK continues to be loaded into the clock synchronization system, and the clock synchronization system continues to maintain synchronization lock on the external clock signal CLK. The frequency or phase of its output clock signal CLK_VCO is approximately the same as or equal to the frequency or phase of the external clock signal CLK.

[0161] (3) Time interval t3-t4:

[0162] Starting from time t3, the external clock signal CLK stops loading.

[0163] In the clock detection circuit 31, both voltage VCL and voltage VCS begin to rise. The time when voltage VCS exceeds the positive threshold voltage Vth2 of the second branch flip-flop 408 precedes the time when voltage VCL exceeds the positive threshold voltage Vth1 of the first branch flip-flop 404, causing the second detection signal CLK_dets generated by the clock detection circuit 31 to become active before the first detection signal CLK_detl, and also causing the delay control signal CLK_SEL to become active.

[0164] At this time, the clock signal CLK_OUT output by the clock switching circuit 32 to the phase-locked loop 33 is a reference clock signal CLK_REF that is basically similar to the internal reference clock signal of the phase-locked loop 33.

[0165] Phase-locked loop 33 receives the clock signal CLK_OUT from clock switching circuit 32 and its output clock signal CLK_VCO. It compares the two signals using a frequency and phase detector 331 and generates a first control signal UP and a second control signal DN. Pulse width limiting module 332 processes the received first and second control signals UP and DN, generating a third control signal P1 and a fourth control signal P2 to control the charge pump output current Icp. Since the frequency of the reference clock signal CLK_REF is higher than the frequency of the external clock signal CLK, the pulse width of the third control signal P1 is greater than the pulse width of the fourth control signal P2. The closing time of switch S3332 in charge pump 333 is greater than the closing time of switch S3334, resulting in a positive value for the charge pump output current Icp. After processing by current-to-voltage conversion module 334, the potential level of voltage V_lpf gradually rises and gradually exceeds the reference voltage Vref, causing the output frequency of voltage-controlled oscillator 335 to gradually increase.

[0166] When the clock signal CLK_VCO output by the voltage-controlled oscillator 335 is synchronized with the reference clock signal CLK_REF, it means that the clock synchronization system switches from the external clock signal CLK to the reference clock signal CLK_REF.

[0167] During this process, the delay control signal CLK_SEL clock is in an active state.

[0168] (4) Time t4:

[0169] Subsequently, in the clock detection circuit 31, the voltage VCL rises and exceeds the positive threshold voltage Vth1 of the first branch trigger 404. The first detection signal CLK_detl becomes active, and the delay control signal CLK_SEL becomes inactive, indicating that the duration of the active state of the delay control signal CLK_SEL has ended. In the phase-locked loop 33, the first switch S3352 closes, the second switch S3353 opens, and the phase-locked loop 33 stops synchronizing with the clock signal CLK_OUT output by the clock switching circuit 32. The clock signal CLK_VCO output by the voltage-controlled oscillator 335 is an internal reference clock signal that is approximately equal to or similar to the reference clock signal CLK_REF.

[0170] This application also includes an electronic device comprising a clock synchronization system as described in any of the preceding claims.

[0171] The clock synchronization system proposed in this application can control the transition time during clock switching, solve the problem of sudden changes in chip frequency during clock switching, and thereby reduce the output voltage ripple of the switching power supply at the moment of switching, so that the entire power supply system has high reliability and stability.

[0172] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A clock synchronization system, characterized in that, include: The clock detection circuit is configured to receive an external clock signal and generate a delay control signal. The delay control signal is valid when the external clock signal stops being provided and continues for a preset duration. A phase-locked loop (PLL) is electrically connected to the clock detection circuit. When the PLL is in a synchronous locked state, it is configured to receive the external clock signal and lock. When the external clock signal stops being provided, it is configured to receive a reference clock signal and lock. The delay control signal is valid. When the valid pulse of the delay control signal ends, the PLL enters a stopped synchronous locked state and is configured to output an internal reference clock signal. The reference clock signal is the same as the internal reference clock signal of the phase-locked loop; the phase-locked loop includes, A frequency and phase detector, wherein a first input terminal is configured to receive the external clock signal or a reference clock signal, and a second input terminal is configured to receive the output of the phase-locked loop, and is configured to compare the frequency or phase difference of the signals received at the two input terminals; and A pulse width limiting module is electrically connected to the frequency and phase detector and is configured to adjust the pulse width of its own output control signal based on the relationship between the pulse width of the signal output by the frequency and phase detector and a preset time limit. A charge pump, electrically connected to the pulse width limiting module, is configured to output a current signal based on a control signal output by the pulse width limiting module. A voltage-controlled oscillator, electrically connected to the charge pump and the clock detection circuit, with its output electrically connected to the second input of the frequency and phase detector, is configured to generate the output of the phase-locked loop based at least on the current signal or a variation thereof.

2. The clock synchronization system according to claim 1, characterized in that, When the pulse width of the signal output by the frequency and phase detector is greater than or equal to the limited time, the pulse width of the control signal output by the pulse width limiting module is equal to the preset limited time length. When the pulse width of the signal output by the frequency and phase detector is less than a predetermined time, the pulse width of the control signal output by the pulse width limiting module is equal to the pulse width of the signal output by the frequency and phase detector.

3. The clock synchronization system according to claim 2, characterized in that, The duration of the delay control signal being in an active state is greater than or equal to the transition time when the phase-locked loop output clock signal is synchronized from the external clock signal to the reference clock signal.

4. The clock synchronization system according to claim 3, characterized in that, The value of the time limit is greater than or equal to the minimum pulse width of the signal output by the frequency and phase detector, and less than the clock period of the reference clock signal.

5. The clock synchronization system according to claim 3, characterized in that, The signal output by the frequency and phase detector includes a first control signal and a second control signal; the signal adjustment unit of the pulse width limiting module limits the pulse width of the first control signal and generates a third control signal; or, the signal adjustment unit limits the pulse width of the second control signal and generates a fourth control signal; wherein, the signal adjustment unit includes: The adjustment unit NOT gate receives input signals including either the first control signal or the second control signal output by the frequency and phase detector. The first transistor of the adjustment unit is configured to receive a bias voltage at its control terminal and a power supply voltage at its second terminal, and the first transistor is configured to provide current. The control electrode of the second transistor of the adjustment unit is electrically connected to the output terminal of the NOT gate of the adjustment unit, and its second electrode is electrically connected to the first electrode of the first transistor of the adjustment unit. The third transistor of the adjustment unit has its control electrode electrically connected between the output terminal of the NOT gate of the adjustment unit and the control electrode of the second transistor of the adjustment unit, its first electrode electrically connected to the first electrode of the second transistor of the adjustment unit, and its second electrode grounded. The adjustment unit capacitor is electrically connected between the first and second terminals of the third transistor of the adjustment unit; its first plate is electrically connected between the first terminal of the third transistor of the adjustment unit and the first terminal of the second transistor of the adjustment unit. An adjustment unit trigger, the input of which is electrically connected to the first plate of the adjustment unit capacitor, is configured to switch the potential of the first plate of the adjustment unit capacitor; The adjustment unit NOR gate has its first input terminal electrically connected to the output terminal of the adjustment unit flip-flop, and its second input terminal electrically connected to the output terminal of the adjustment unit NOT gate. The first transistor and the second transistor of the adjustment unit are of the same type, and the third transistor of the adjustment unit is of the opposite type to the first transistor and the second transistor of the adjustment unit.

6. The clock synchronization system according to claim 1, characterized in that, It also includes a clock switching circuit, electrically connected to the clock detection circuit, configured to select the external clock or reference clock signal for output based on the delay control signal output by the clock detection circuit.

7. The clock synchronization system according to claim 3, characterized in that, The clock detection circuit includes: A first detection branch is configured to detect an external clock signal and generate a first detection signal. This includes: a first branch current source configured to receive a power supply voltage and provide current; a first branch transistor whose control electrode receives the external clock signal, whose first electrode is electrically connected to the output terminal of the first branch current source, and whose second electrode is grounded; a first branch capacitor whose first plate is electrically connected between the first electrode of the first branch transistor and the output terminal of the first branch current source, and whose second plate is electrically connected to the second electrode of the first branch transistor; and a first branch trigger electrically connected between the first plate of the first branch capacitor and the output terminal of the first branch current source, configured to generate the first detection signal based on the voltage of the first plate of the first branch capacitor. The second detection branch is configured to detect an external clock signal and generate a second detection signal. It includes: a second branch current source configured to receive a power supply voltage and provide current; a second branch transistor whose control electrode receives the external clock signal, whose first electrode is electrically connected to the output terminal of the second branch current source, and whose second electrode is grounded; a second branch capacitor whose first plate is electrically connected between the first electrode of the second branch transistor and the output terminal of the second branch current source, and whose second plate is electrically connected to the second electrode of the second branch transistor; and a second branch trigger electrically connected between the output terminal of the second branch current source and the first plate of the second branch capacitor, configured to generate the second detection signal based on the voltage of the first plate of the second branch capacitor. The detection circuit NOT gate is electrically connected to the output terminal of the first branch flip-flop and is configured to receive the first detection signal output by the first detection branch and perform a logical NOT operation. The detection circuit AND gate has its first input terminal electrically connected to the output terminal of the detection circuit NOT gate, and its second input terminal electrically connected to the output terminal of the second branch flip-flop. The detection circuit AND gate is configured to receive the first detection signal and the second detection signal and perform an AND logic operation on the two. The capacitance values ​​of the first branch capacitor and the second branch capacitor are different; when the external clock signal stops loading, there is a time difference between the moment when the second detection signal and the first detection signal become valid, and the delay control signal is valid within the time difference.

8. The clock synchronization system according to claim 7, characterized in that, The capacitance value of the first branch capacitor is greater than the capacitance value of the second branch capacitor.

9. The clock synchronization system according to claim 6, characterized in that, The clock switching circuit includes, The switching circuit first NOR gate is configured to receive an external clock signal and a delay control signal from the clock detection circuit, and perform a logical NOR operation on the two. The switching circuit NOT gate is configured to receive a reference clock signal and perform a logical NOT operation on it; The switching circuit AND gate is configured to receive the output of the switching circuit NOT gate and the delay control signal, and perform a logical AND operation on the two; The second NOR gate of the switching circuit is configured to receive the outputs of the first NOR gate of the switching circuit and the AND gate of the switching circuit, and perform a logical NOR operation on the two.

10. The clock synchronization system according to claim 7, characterized in that, The phase-locked loop also includes, A current-to-voltage conversion module is electrically connected to the output terminal of the charge pump and configured to convert the current signal output by the charge pump into a voltage signal; A voltage-controlled oscillator is also electrically connected to the current-to-voltage conversion module and the clock detection circuit; including a voltage-controlled current unit, the first input of which is electrically connected between the charge pump and the current-to-voltage conversion module, and the second input of which is configured to receive a reference voltage; a first switch, electrically connected between the first input and the second input of the voltage-controlled current unit; and a second switch and an oscillator, the second switch being electrically connected between the output of the voltage-controlled current unit and the input of the oscillator; wherein the first switch and the second switch are configured to be switched on and off under the control of the first detection signal, and the two cooperate to change the operating state of the phase-locked loop.

11. The clock synchronization system according to claim 10, characterized in that, When the first detection signal generated by the clock detection circuit changes to failure, the first switch opens and the second switch closes. or, When the first detection signal generated by the clock detection circuit becomes valid, the first switch closes and the second switch opens.

12. An electronic device, characterized in that, Includes the clock synchronization system described in any one of claims 1-11.

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