Substrate structure, method of manufacturing a substrate structure, and semiconductor structure

Abstract

The application provides a substrate structure, a preparation method of the substrate structure and a semiconductor structure. The substrate structure comprises: a substrate body; a plurality of periodically arranged groove structures, the plurality of groove structures being located in the substrate body, and any two adjacent groove structures being in contact; and a plurality of filling layers, each of the filling layers being located in a groove structure, and a surface of the filling layer being flush with a surface of the substrate body. The application solves the problem of high defect density in the growth of a silicon carbide epitaxial layer in the prior art.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a substrate structure, a method for preparing the substrate structure, and a semiconductor structure. Background Technology

[0002] Silicon carbide (SiC) materials, due to their wider bandgap, exhibit higher avalanche critical electric field, thermal conductivity, operating temperature, chemical stability, and radiation resistance, making them a highly sought-after material in recent years as one of the third-generation semiconductors. The efficient and stable operation of 4H-SiC power devices relies on high-quality silicon carbide epitaxial wafers. Currently, various types of defects exist during the 4H-SiC epitaxial growth process, including micropipes, basal plane dislocations (BPD), triangular defects, thread-like surface defects (TSD), and tilted epitaxial defects (TED), which can severely impact device performance. Therefore, current technologies primarily focus on reducing defects in the silicon carbide epitaxial layer. Based on the source of these defects, there are generally three solutions: one is to optimize the parameters of the epitaxial process to reduce potential defects during epitaxial growth. The second method involves preparing a barrier layer on the substrate before epitaxial growth. This involves pre-growing a dense, homogeneous buffer layer or other layer on the wafer surface to prevent defects in the substrate from entering the epitaxial layer. The third method involves pre-treating the substrate, including but not limited to cleaning and surface etching, to remove surface contaminants and defects. However, for substrates used in high-voltage power devices, controlling defects by adjusting process parameters has limited effectiveness. Generally, surface pre-treatment combined with the preparation of a thicker barrier layer is used to manage defects. Nevertheless, completely removing or significantly reducing defects in the substrate remains a challenge for the industry.

[0003] Various defects exist in current silicon carbide epitaxy, which can have a serious impact on devices, especially thick epitaxial layer devices used in high voltage applications. Summary of the Invention

[0004] The main objective of this application is to provide a substrate structure, a method for preparing the substrate structure, and a semiconductor structure to solve the problem of high defect density during the growth of silicon carbide epitaxial layers in the prior art.

[0005] To achieve the above objectives, according to one aspect of this application, a substrate structure is provided, comprising: a substrate body; a plurality of periodically arranged trench structures located in the substrate body, wherein any two adjacent trench structures are in contact; and a plurality of filling layers located one-to-one in the trench structures, wherein the surface of the filling layer is flush with the surface of the substrate body.

[0006] Optionally, the bottom surface of the trench structure may be a circle or an equilateral polygon with 2a sides, where a ≥ 3.

[0007] Optionally, the width of the trench structure gradually decreases along a predetermined direction, the predetermined direction being the direction from the bottom surface of the trench structure to the non-trench surface of the substrate body, the non-trench surface being the surface of the substrate body away from the trench structure, the predetermined direction being parallel to the thickness direction of the substrate body, and the direction of the width intersecting the thickness direction of the substrate body.

[0008] Optionally, the angle between the extension direction of the sidewall of the trench structure and the thickness direction of the substrate body is 4°-8°.

[0009] Optionally, the depth of the trench structure is 0.5 μm–1.5 μm, and the direction of the depth is parallel to the thickness direction of the substrate body.

[0010] Optionally, the plurality of periodically arranged trench structures stop at a distance of ≥5μm from the edge of the substrate body.

[0011] According to another aspect of this application, a method for fabricating any of the aforementioned substrate structures is provided, comprising: providing a pre-substrate; forming a mask layer on the surface of the pre-substrate; patterning the mask layer to remove a portion of the mask layer to obtain a plurality of periodically arranged pre-trench structures, wherein any two adjacent pre-trench structures are in contact; patterning the pre-substrate using the plurality of pre-trench structures; removing a portion of the pre-substrate and then removing the plurality of pre-trench structures, wherein the remaining pre-substrate forms a substrate body and a plurality of trench structures located on the substrate body; and forming a filling layer corresponding to each trench structure, wherein the surface of the filling layer is flush with the surface of the substrate body.

[0012] Optionally, patterning the pre-substrate includes: patterning the pre-substrate using plasma etching.

[0013] Optionally, forming a filling layer in a one-to-one correspondence within the trench structure includes: forming a first sub-filling layer in the trench structure using atomic layer deposition; and forming a second sub-filling layer on the surface of the first sub-filling layer using chemical vapor deposition, wherein the first sub-filling layer and the second sub-filling layer constitute the filling layer.

[0014] According to another aspect of this application, a semiconductor structure is provided, comprising: any of the substrate structures described herein, or a substrate structure prepared by any of the substrate structure preparation methods described herein; and an epitaxial layer located on the surface of the substrate structure having a filling layer.

[0015] Optionally, the semiconductor structure further includes a buffer layer located between the substrate structure and the epitaxial layer.

[0016] The substrate structure using the technical solution of this application includes a substrate body, a plurality of periodically arranged trench structures located within the substrate body, and a plurality of filling layers. Each filling layer is located in a corresponding trench structure, and the surface of the filling layer is flush with the surface of the substrate body. Compared with the high defect density during silicon carbide epitaxial layer growth in the prior art, this application, by introducing a periodically arranged trench structure network into the substrate, can artificially introduce stress quantization, change the stress distribution on the substrate surface, effectively release local stress concentration on the substrate surface, and help reduce dislocation nucleation and propagation during subsequent epitaxial growth. Furthermore, the introduction of the filling layers, especially their close cooperation with the trench structures, can optimize the interface quality between the substrate and the epitaxial layer, reduce defects caused by lattice mismatch, and ensure a low defect density in the epitaxial layer. Attached Figure Description

[0017] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 A top view schematic diagram of a substrate structure provided according to an embodiment of this application is shown;

[0019] Figure 2 A front view of a single trench structure provided according to an embodiment of this application is shown;

[0020] Figure 3 A schematic flowchart of a method for fabricating a substrate structure according to an embodiment of this application is shown;

[0021] Figure 4 A schematic diagram comparing the defect densities of epitaxial wafers grown using the substrate structure of this application and the substrate structure of the prior art is shown.

[0022] The above figures include the following reference numerals:

[0023] 10. Substrate body; 11. Trench structure. Detailed Implementation

[0024] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0025] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0028] For ease of description, the following explains some of the nouns or terms used in the embodiments of this application:

[0029] As described in the background section, the existing technology has a high defect density during the growth of silicon carbide epitaxial layers. To solve the above problem, the embodiments of this application provide a substrate structure, a method for preparing the substrate structure, and a semiconductor structure.

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] This application provides a substrate structure, such as... Figure 1 As shown, it includes:

[0032] Substrate body 10;

[0033] Optionally, the substrate body 10 may be made of 4H-SiC.

[0034] Multiple periodically arranged trench structures 11 are located in the substrate body 10, and any two adjacent trench structures 11 are in contact.

[0035] Specifically, multiple trench structures 11 are periodically arranged on a predetermined plane, which intersects with the thickness direction of the substrate body 10.

[0036] Specifically, periodic arrangements include, but are not limited to, honeycomb arrangements, matrix arrangements, and so on.

[0037] Multiple filler layers (not shown) are located in the trench structure 11 in a corresponding manner, and the surface of the filler layer is flush with the surface of the substrate body 10.

[0038] Optionally, the filling layer may be made of silicon carbide, which is lattice-matched with the substrate material to ensure lattice matching between the substrate structure and the epitaxial layer interface, thereby reducing the risk of defects.

[0039] In the above embodiments, the substrate structure includes a substrate body, a plurality of periodically arranged trench structures located within the substrate body, and a plurality of filling layers, wherein each filling layer is located in a corresponding trench structure, and the surface of the filling layer is flush with the surface of the substrate body. Compared with the problem of high defect density during silicon carbide epitaxial layer growth in the prior art, this application introduces a periodically arranged trench structure network in the substrate, which can artificially introduce stress quantization, change the stress distribution on the substrate surface, effectively release local stress concentration on the substrate surface, and help reduce dislocation nucleation and propagation during subsequent epitaxial growth. Furthermore, the introduction of the filling layer, especially its close cooperation with the trench structure, can optimize the interface quality between the substrate and the epitaxial layer, reduce defects caused by lattice mismatch, and ensure a low defect density in the epitaxial layer.

[0040] In one alternative embodiment, the bottom surface of the aforementioned trench structure includes a circle or an equilateral polygon with 2a sides, where a ≥ 3. In this embodiment, different trench bottom surface shapes can alter the stress distribution pattern. Due to their symmetry, equilateral polygons can more evenly disperse stress, further reducing the formation and propagation of dislocations. Furthermore, equilateral polygons with more sides provide more edges, giving dislocations a greater chance to be guided to the hole wall and annihilated during growth. A circular bottom surface can provide the same stress response in all directions, avoiding stress concentration caused by directional differences.

[0041] Specifically, polygons can be hexagons, octagons, decagons, 12-sided polygons, etc.

[0042] In practical applications, those skilled in the art can flexibly choose the appropriate shape of the bottom surface of the trench structure according to actual needs, and this application does not impose specific limitations in this regard. In the embodiments of this application, the bottom surface of the trench structure is hexagonal, and the shape of the upper opening of the trench structure is also hexagonal, with a side length of 0.5μm-2μm.

[0043] In one exemplary embodiment, the width of the trench structure gradually decreases along a predetermined direction, the predetermined direction being the direction from the bottom surface of the trench structure towards the non-trenching surface of the substrate body, the non-trenching surface being the surface of the substrate body away from the trench structure, the predetermined direction being parallel to the thickness direction of the substrate body, and the direction of the width intersecting the thickness direction of the substrate body. In this embodiment, by designing the width of the trench structure to gradually decrease along the direction from the bottom of the trench towards the substrate surface (non-trenching surface) (i.e., a funnel-shaped trench structure), dislocations can be effectively guided to the hole walls and annihilated during growth, further reducing the propagation of dislocations into the epitaxial layer. The trench structure with gradually decreasing width can guide dislocations to move along a specific direction until they reach the hole walls and disappear, thereby further reducing defect sources in the epitaxial layer.

[0044] According to some exemplary embodiments of this application, such as Figure 2 As shown, the angle between the extension direction of the sidewall of the trench structure 11 and the thickness direction of the substrate body (not shown) is 4°-8°. In this embodiment, by constructing a trench structure with a specific angle, a certain stress relief path can be formed on the substrate surface, further reducing stress concentration. When the angle is too small, it may not be sufficient to effectively disperse local stress, causing dislocations to extend more easily along the original path during epitaxy. When the angle is too large, it may introduce additional stress, which is not conducive to defect control. The range of 4° to 8° is the best trade-off between avoiding excessive stress concentration and preventing the introduction of additional stress, which helps to control the stress distribution of the substrate, thereby further reducing dislocations and defects in the epitaxial layer.

[0045] Specifically, by controlling the tilt angle of the trench sidewalls, the movement path of dislocations can be effectively guided, preventing the dislocations from expanding laterally during growth and reducing defects in the epitaxial layer. Sidewalls at specific angles can generate appropriate stress gradients, causing dislocations to move along the hole wall and eventually disappear, rather than spreading into the epitaxial layer.

[0046] According to some other exemplary embodiments of this application, the depth of the trench structure is 0.5 μm–1.5 μm, and the direction of the depth is parallel to the thickness direction of the substrate body. In this embodiment, by controlling the depth of the trench structure, a more effective stress relief region can be formed on the substrate surface, further reducing the possibility of dislocation nucleation during the growth process. Trenches of appropriate depth can provide sufficient space to accommodate and dissipate dislocations, preventing them from entering the epitaxial layer. At the same time, controlling the depth is also to maintain the mechanical strength of the substrate and prevent excessive etching from causing substrate warping or breakage.

[0047] According to some other exemplary embodiments of this application, such as Figure 1 As shown, the aforementioned multiple periodically arranged trench structures 11 stop at a distance of ≥5μm from the edge of the substrate body 10. This ensures the integrity of the wafer edge and reduces the risk of edge breakage due to gaps during processing, thus minimizing the potential for wafer cracking. Being too close to the wafer edge is ineffective, while being too far away may result in wasted substrate resources.

[0048] In summary, this application constructs a hollow funnel-shaped structure (i.e., a trench structure) in a silicon carbide substrate. The hollow structure can release local stress concentration and reduce the probability of dislocation nucleation. The funnel-shaped angle guides dislocations to extend along a specific direction to the hole wall for annihilation, effectively reducing the original sites for defects in the substrate to extend to the epitaxial layer. Subsequently, the hollow funnel-shaped structure is filled with ALD (Atomic Layer Deposition) and CVD (Chemical Vapor Deposition) techniques, and an epitaxial layer is grown, ultimately achieving the goal of effectively reducing the defect density in the substrate.

[0049] Figure 3 This is a flowchart of a method for fabricating a substrate structure according to an embodiment of this application. Figure 3 As shown, the method includes the following steps:

[0050] Step S101: Provide a pre-prepared substrate;

[0051] Step S102: A mask layer is formed on the surface of the prepared substrate.

[0052] Step S103: Pattern the above-mentioned mask layer to remove part of the above-mentioned mask layer, and obtain a plurality of periodically arranged pre-groove structures, with any two adjacent pre-groove structures in contact.

[0053] Step S104: Using multiple pre-trench structures, the pre-substrate is patterned, a portion of the pre-substrate is removed, and multiple pre-trench structures are removed. The remaining pre-substrate forms a substrate body and multiple trench structures located on the substrate body.

[0054] Step S105: A filling layer is formed in the trench structure in a one-to-one correspondence, and the surface of the filling layer is flush with the surface of the substrate body.

[0055] In this embodiment, a pre-substrate is first provided, then a mask layer is formed on the surface of the pre-substrate, and the mask layer is patterned to obtain multiple periodically arranged pre-trench structures. The pre-substrate is then patterned using these pre-trench structures to obtain a substrate body and multiple trench structures located within the substrate body. Finally, a filling layer is formed in each trench structure. Compared to the high defect density problem in the growth of silicon carbide epitaxial layers in the prior art, this application introduces a periodically arranged trench structure network into the substrate, which artificially introduces stress quantization, changes the stress distribution on the substrate surface, effectively releases local stress concentration on the substrate surface, and helps reduce dislocation nucleation and propagation during subsequent epitaxial growth. Furthermore, the introduction of the filling layer, especially its close cooperation with the trench structure, can optimize the interface quality between the substrate and the epitaxial layer, reduce defects caused by lattice mismatch, and ensure a low defect density in the epitaxial layer.

[0056] In one alternative approach, patterning the aforementioned pre-substrate includes: patterning the pre-substrate using plasma etching. In this embodiment, plasma etching can precisely transfer the pattern on the mask layer onto the pre-substrate to form the desired structure, improving the quality of the substrate structure and the reliability of epitaxial layer growth.

[0057] Specifically, in addition to plasma dry etching, wet etching can also be used, and this application does not impose any specific restrictions on this.

[0058] In other embodiments, filling layers are formed one-to-one in the trench structure, including: forming a first sub-filling layer in the trench structure using atomic layer deposition (ALD); and forming a second sub-filling layer on the surface of the first sub-filling layer using chemical vapor deposition (CVD). The first and second sub-filling layers constitute the filling layer. In this embodiment, by performing a dual deposition process of ALD followed by CVD, a high-quality filling layer can be formed in the trench structure, optimizing the interface matching between the substrate and the epitaxial layer. ALD deposition provides a uniform and dense first sub-filling layer, while CVD deposition quickly fills the remaining space to form the second sub-filling layer. The combination of the two processes ensures both interface quality and filling efficiency.

[0059] Specifically, the thickness of the first sub-filling layer is 5nm-20nm.

[0060] Specifically, in addition to the dual deposition process of ALD followed by CVD to form the filling layer, the filling layer can also be formed by using ALD technology alone or by using CVD technology alone. This application does not impose any specific restrictions on this.

[0061] Specifically, the specific steps of the substrate structure fabrication method are as follows:

[0062] 1) Preparation and cleaning of the pre-substrate (i.e., providing the pre-substrate): Select a 6, 8, or 12-inch N-type 4H-SiC pre-substrate (preferably 6 inches). First, perform RCA standard cleaning to remove surface organic matter, particulate contaminants, and residual metal ions. Finally, clean with deionized water and blow the pre-substrate with high-purity nitrogen gas.

[0063] 2) Photoresist coating, hardening, exposure, and development on the substrate surface (i.e., forming a mask layer on the surface of the prepared substrate and patterning the mask layer): Positive photoresist is used for coating, with a thickness of 1.0-2.0 μm (preferably 1.3 μm). If the photoresist is too thin, the light propagation path within the layer will be shortened during exposure due to insufficient thickness, potentially leading to uneven distribution of exposure energy within the layer, thus affecting lithography resolution. During development, insufficient thickness may prevent the photoresist from effectively blocking the etchant, resulting in over-etching or over-development, inaccurate pattern transfer, and problems such as undersized patterns or shape distortion. Excessively thick photoresist requires a longer exposure time to reach the required exposure dose at the bottom of the layer, increasing the lithography machine's operating time and cost. During development, an excessively thick layer will prolong the development time, and incomplete development may occur within the layer, resulting in residual photoresist or unclear patterns. Subsequently, pre-baking is performed on a hot plate at 80-120℃ (preferably 100℃) for 40-80 seconds (preferably 60 seconds). The main purpose is to evaporate the solvent through heating, thereby improving the adhesion between the photoresist and the silicon wafer, reducing internal stress in the photoresist film, and making it more flat, thus preparing it for subsequent exposure and development steps. The aforementioned temperature and time ranges ensure good solvent evaporation while avoiding over-drying or insufficient drying. Too low a temperature or too short a time will result in insufficient solvent evaporation in the photoresist, leading to excessive residual solvent. This will reduce the adhesion between the photoresist film and the prepared substrate, making it prone to detachment or erosion in subsequent wet chemical processes, resulting in process failure. A decrease in yield can lead to an increase in unexposed photoresist film areas (dark etching) during development, affecting the photoresist contour shape, dimensional accuracy, and sidewall steepness, thus reducing development yield. Excessive temperature or time can cause the photoresist to over-dry, even cracking, reducing its flexibility and increasing brittleness, making it prone to breakage and detachment in subsequent processes. For positive photoresist, it may cause photoinitiator decomposition, leading to intensified dark etching and affecting the performance and development effect of the photoresist film. Subsequently, an ultraviolet lithography machine is used, with the exposure dose set to 50-200 mJ / cm². 2(Preferred 135 mJ / cm²), the patterned etching area is defined. The exposure dose determines the degree of decomposition of the photoinitiator in the photoresist, thus affecting the chemical changes of the photoresist. An appropriate exposure dose ensures that the photoresist can accurately form the required pattern during development. Insufficient exposure will lead to incomplete reaction of the photoresist, and the photoresist in the unexposed areas may be partially removed after development, resulting in an incomplete pattern or an oversized pattern. Overexposure will cause the photoresist to react excessively, resulting in excessive removal of the photoresist in the exposed areas during development, resulting in an undersized pattern or overdevelopment. Development with a positive photoresist developer for 40-70 seconds (preferred 50 seconds) determines the reaction time between the developer and the photoresist, thus affecting the formation of the photoresist pattern. An appropriate development time ensures that the photoresist in the exposed areas is completely removed, while the photoresist in the unexposed areas remains intact. Insufficient development time will lead to incomplete reaction of the photoresist in the exposed areas. If the photoresist is not completely removed, the pattern will be incomplete or too large. Excessive development time can also cause partial removal of photoresist in unexposed areas, resulting in a smaller pattern size or overdevelopment. The post-baking conditions are 80-130℃ (preferably 110℃) and 60-100 seconds (preferably 90 seconds). The purpose of post-baking is to further solidify the photoresist through heating, improving its adhesion to the substrate, reducing internal stress, and enhancing its etching resistance, thus preparing it for subsequent etching processes. Too low a temperature or too short a time will result in insufficient photoresist solidification and weak adhesion to the prepared substrate, making it prone to detachment or erosion during subsequent etching. Too high a temperature or too long a time will cause the photoresist to over-solidify, becoming too brittle and prone to cracking or peeling in subsequent processes. After this step, a patterned photoresist mask can be formed on the surface of the prepared substrate, facilitating subsequent patterning of the prepared substrate.

[0064] 3) ICP etching of the pre-substrate (i.e., removal of the pre-substrate portion): Using the developed photoresist as a mask, plasma etching is performed on the pre-substrate to etch the designed pattern. Etching gases include: fluorine-based gases (SF6, CF4, NF3, BF3, CHF3), chlorine-based gases (Cl2, SiCl4, BCl3), and bromine-based gases (Br2, IBr). Other gases include oxygen, helium, argon, nitrogen, and hydrogen. SF6 is selected here, used in conjunction with O2. The main purpose of oxygen and argon is to enhance carbon atom removal or increase the concentration of reactive substances. The ratio of SF6 to O2 is between 5:1 and 20:1. Increasing the O2 flow rate promotes oxygen removal during the etching process. The chemical reaction helps form a protective film on the sidewalls, making the etched pattern steeper, but may reduce the etch rate. Reducing the O2 flow rate increases the activity of SF6 and improves the etch rate, but may lead to insufficient sidewall protection, resulting in tilted patterns or over-etching. Here, the preferred etchant is an SF6 main gas flow rate of 30 sccm and an O2 auxiliary gas flow rate of 2 sccm (ratio 15:1). The ICP power is between 500W and 2000W. Higher ICP power results in greater plasma density and a faster etch rate, but may lead to over-etching, pattern edge damage, and equipment wear. If the power is too low, the plasma density is insufficient, resulting in a slow etch rate that cannot meet the requirements for high-efficiency etching. Here, 900W is preferred. RF bias... The power is selected between 50W and 300W. The RF bias power controls the ion energy and direction in the plasma, thus affecting the anisotropy and pattern fidelity of the etching. Higher power results in greater ion energy and better anisotropy, but may lead to substrate damage and pattern edge loss. If the power is too low, the ion energy is insufficient, and the etched pattern is prone to lateral etching, resulting in decreased pattern fidelity. Here, 180W is preferred. The chamber pressure is selected between 5mTorr and 30mTorr. The chamber pressure affects the behavior of the plasma and the progress of the etching reaction. At higher pressure, the gas molecule density is high, the plasma collision frequency is high, and the etching rate may decrease, but the removal of reaction byproducts may be slower, leading to pattern contamination. Lower pressure... At this stage, the gas molecules have a long free path, resulting in fewer plasma collisions and a high etching rate. However, uniformity and stability may deteriorate. Here, 12 mTorr is preferred. The etching time varies from a few minutes to tens of minutes depending on the etching depth and rate. If the etching time is too long, it may lead to over-etching, exceeding the design requirements for pattern size, or even damaging the substrate. If the time is too short, the predetermined etching depth cannot be achieved, resulting in an incomplete pattern. The etching depth affects the defect density and wafer state after epitaxial layer growth. Insufficient etching depth leads to poor defect reduction, while excessive etching depth can cause wafer warping. The etching depth achieved in this step is 0.5 micrometers to 2 micrometers, and the etching time here is 5 minutes with an etching depth of 1.5 micrometers; After ICP etching, an array structure pattern is formed on the bottom. The etched pattern unit cell is a hollow boss structure (i.e., trench structure) with hexagonal top and bottom. Its front and side views are funnel-shaped, meaning the side length of the upper hexagon is longer than that of the lower hexagon, and their centers are aligned. The angle between the line connecting the vertices of the upper and lower hexagons and the surface normal is 4-8°. If it is less than 4°, edge defects are prone to occur in the epitaxial layer. If it is greater than 8°, stress concentration will occur, leading to structural incompleteness and the risk of substrate breakage. Here, 6° is preferred, balancing dislocation blocking efficiency and structural stability. The hexagonal unit expands periodically, and the edge region gradually becomes a truncated hexagon. The side length of the upper hexagon is 0.5-2 micrometers. The central unit cell is aligned with the wafer center, and subsequent unit cells are arranged closely in sequence. While a small side length can improve dislocation blocking rate, it increases the cost of photolithography in the initial steps and makes precise pattern transfer difficult, leading to defects in the final pattern structure. Conversely, a large side length makes the sidewalls of holes prone to collapse during etching or epitaxy. Furthermore, a small side length can cause abnormal nucleation due to the high curvature of the surface, forming polycrystalline SiC inclusions and creating new defect sites. An excessively large side length reduces the dislocation blocking rate and also leads to stress concentration, increasing substrate warpage. The optimal side length here is 1.2 μm, achieving maximum defect suppression and alleviating stress concentration in the edge region. Multiple periodically arranged trench structures stop 5 μm from the substrate edge to ensure wafer edge integrity and reduce edge breakage due to notches during processing, thus reducing the risk of further wafer cracking. Too close to the wafer edge is ineffective, while too far may result in wasted substrate resources.

[0065] 4) Removal of photoresist (i.e., removal of multiple pre-trench structures): Immerse the etched pre-substrate in acetone solution and ultrasonically clean for 5-20 minutes. If the time is too short, the acetone may not be able to fully dissolve the photoresist, resulting in incomplete stripping. Photoresist residue will affect subsequent processes. If the time is too long, it will not significantly improve the effect of photoresist removal and will increase the process time and reduce production efficiency. Here, 10 minutes is preferred to ensure the stripping of photoresist. Then rinse with ethanol and deionized water in sequence, and blow dry with nitrogen to ensure that there is no residual photoresist (in addition to wet methods, ICP plasma cleaning can also be used to remove photoresist. This application does not make specific restrictions on this).

[0066] 5) ALD deposition (i.e., formation of the first sub-fill layer): Silane and H2O are selected as precursors. The ALD process is used to pre-deposit patterned voids to ensure lattice fit at the interface, reducing the risk of defect formation. The resulting ALD layer thickness is 5-20 nm, and the cycle count is 50-200 times. Insufficient cycle counts or insufficient thickness may not effectively achieve lattice fit at the interface, failing to fully realize the defect reduction effect and significantly impacting subsequent processes and device performance. While excessive cycle counts or excessive thickness can help reduce defects to some extent, they increase process time and cost, and may also lead to defects in the thin film. Excessive thickness leads to stress problems; a thickness of 15 nm and 100 cycles are preferred here. The temperature range for ALD deposition of silicon carbide is 150℃-300℃. The deposition temperature can ensure the reactivity of the precursor, resulting in a high-quality final film. If the temperature is too low, the reaction rate will be slow, the film deposition speed will be slow, and the reaction may not be sufficient, resulting in poor film quality, such as the presence of many unreacted precursors or pores. If the temperature is too high, the precursor will decompose, destroying the self-limiting reaction mechanism, making it difficult to control the film thickness and causing poor uniformity. It may also cause deformation or damage to the substrate material. 220℃ is preferred here.

[0067] 6) CVD Deposition for Hole Filling (i.e., Formation of a Second Sub-filling Layer): After ALD deposition, CVD technology is used to continue filling until completion. The CVD deposition gas options include SiH4, CH4, C3H8, and C2H4, with hydrogen (H2) chosen as the carrier gas. Specifically, SiH4 and C2H4 are preferred as the reactant gases, with a flow ratio between 1:1 and 1:5. A flow ratio that is too low (e.g., less than 1:1) may lead to excessively high silicon content, affecting the uniformity and quality of the film. A flow ratio that is too high (e.g., greater than 1:3) may lead to… Excessive carbon content can lead to non-stoichiometric ratio and internal stress issues in the thin film; the optimal ratio is 1:3. The hydrogen flow rate to silane ratio should be 1:50-1:200. Excessive hydrogen flow will reduce the relative concentration of reactant gases, causing a decrease in the reaction rate and a slower film deposition rate. This increases the deposition time required to achieve the desired film thickness, reducing production efficiency. Furthermore, excessive hydrogen flow may lead to uneven distribution of reactant gases within the reaction chamber and a decrease in chamber temperature, resulting in uneven film thickness and quality. Insufficient hydrogen flow will... Excessively high relative concentrations of reactant gases can lead to overly vigorous reactions, causing localized overreactions or carbon buildup. This can affect the uniformity and quality of the film, and even cause cracking or peeling. Furthermore, excessively high reactant gas concentrations may increase side reactions, generating unnecessary byproducts and affecting the purity and performance of the film. A ratio of 1:100 is preferred here. The deposition temperature is 800℃-1200℃. Too low a temperature may result in a slow reaction rate and poor film quality, while too high a temperature may cause excessively rapid precursor decomposition, triggering side reactions and affecting film quality. A temperature of 980℃ is preferred here. The deposition pressure is 100 Torr-500 Torr. Too low a pressure may result in insufficient reactant gas molecular density, affecting the reaction rate, while too high a pressure may cause uneven gas flow, affecting film uniformity. A pressure of 250 Torr is preferred here. The deposition time is 10-150 min. Too short a deposition time may result in incomplete filling of voids, leaving unfilled areas and affecting device performance. Too long a deposition time may lead to resource waste, increased production costs, and excessively thick films may cause stress problems, affecting device reliability. A deposition time of 45 min is preferred here.

[0068] 7) Surface polishing, cleaning and drying: The substrate surface after the above steps is first chemically and mechanically polished, then ultrasonically cleaned with deionized water, dried with nitrogen, and dried in a vacuum oven.

[0069] 8) Epitaxial layer growth: The cleaned and dried silicon carbide substrate is placed in an epitaxial furnace for CVD epitaxial growth.

[0070] This application also provides a semiconductor structure, including: any of the above-described substrate structures, or a substrate structure prepared by any of the above-described substrate structure preparation methods; and an epitaxial layer located on the surface of the substrate structure having a filling layer.

[0071] In the above embodiments, the semiconductor structure includes a substrate structure and a surface with a filling layer located on the substrate structure. Compared with the problem of high defect density during silicon carbide epitaxial layer growth in the prior art, this application introduces a periodically arranged trench structure network in the substrate, which can artificially introduce stress quantization, change the stress distribution on the substrate surface, effectively release local stress concentration on the substrate surface, and help reduce dislocation nucleation and propagation during subsequent epitaxial growth. Furthermore, the introduction of the filling layer, especially its close cooperation with the trench structure, can optimize the interface quality between the substrate and the epitaxial layer, reduce defects caused by lattice mismatch, and ensure a low defect density in the epitaxial layer.

[0072] In one exemplary embodiment, the semiconductor structure further includes a buffer layer located between the substrate structure and the epitaxial layer. In this embodiment, the presence of the buffer layer can further alleviate the lattice difference between the substrate and the epitaxial layer, further reduce the generation of dislocations, and further improve the quality of the epitaxial layer.

[0073] Specifically, defect testing was performed on the epitaxial wafer grown using the substrate structure of this application. Taking a 1-micrometer-thick buffer layer and a 10-micrometer-thick epitaxial layer as an example, defect detection was performed on the epitaxial layer, and the results are as follows: Figure 4 As shown, the control group consists of samples directly grown epitaxially in the prior art. Figure 4 It is known that the defect density of the epitaxial layer (i.e., the pretreatment group) grown using the substrate structure of this application is 0.03 ± 0.01 cm⁻¹. -2 The defect density of the epitaxial layer (i.e., the untreated group) in the prior art is 0.18 ± 0.07 cm⁻¹. -2 By adopting the substrate structure of this application, the defect density of the epitaxial layer is greatly reduced.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0076] The substrate structure of this application includes a substrate body, multiple periodically arranged trench structures within the substrate body, and multiple filling layers. Each filling layer is located in a corresponding trench structure, and the surface of the filling layer is flush with the surface of the substrate body. Compared to the high defect density during silicon carbide epitaxial layer growth in existing technologies, this application introduces a periodically arranged trench structure network into the substrate, which artificially introduces stress quantization, alters the stress distribution on the substrate surface, and effectively releases localized stress concentrations on the substrate surface. This helps reduce dislocation nucleation and propagation during subsequent epitaxial growth. Furthermore, the introduction of the filling layers, especially their close integration with the trench structures, optimizes the interface quality between the substrate and the epitaxial layer, reduces defects caused by lattice mismatch, and ensures a low defect density in the epitaxial layer.

[0077] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A substrate structure, characterized in that, include: Substrate body; Multiple periodically arranged trench structures, the multiple trench structures are located in the substrate body, and any two adjacent trench structures are in contact; Multiple filling layers are located in the trench structure in a one-to-one correspondence. The surface of the filling layer is flush with the surface of the substrate body. The material of the filling layer includes silicon carbide. The material of the filling layer is lattice-matched with the material of the substrate body. The filling layer is an independent layer that is fabricated using a process different from that of the epitaxial layer and is distinct from the buffer layer and the epitaxial layer.

2. The substrate structure according to claim 1, characterized in that, The bottom surface of the trench structure can be a circle or an equilateral polygon with 2a sides, where a ≥ 3.

3. The substrate structure according to claim 1, characterized in that, Along a predetermined direction, the width of the trench structure gradually decreases. The predetermined direction is the direction from the bottom surface of the trench structure to the non-trench surface of the substrate body. The non-trench surface is the surface of the substrate body away from the trench structure. The predetermined direction is parallel to the thickness direction of the substrate body, and the direction of the width intersects the thickness direction of the substrate body.

4. The substrate structure according to claim 3, characterized in that, The angle between the extension direction of the sidewall of the trench structure and the thickness direction of the substrate body is 4°-8°.

5. The substrate structure according to claim 1, characterized in that, The trench structure has a depth of 0.5 μm–1.5 μm, and the direction of the depth is parallel to the thickness direction of the substrate body.

6. The substrate structure according to claim 1, characterized in that, The plurality of periodically arranged trench structures stop at a distance of ≥5 μm from the edge of the substrate body.

7. A method for preparing a substrate structure according to any one of claims 1 to 6, characterized in that, include: Provide a pre-prepared substrate; A mask layer is formed on the surface of the prepared substrate; The mask layer is patterned to remove a portion of the mask layer, resulting in a plurality of periodically arranged pre-trench structures, with any two adjacent pre-trench structures in contact. The pre-substrate is patterned using multiple pre-trench structures. After removing a portion of the pre-substrate, the multiple pre-trench structures are removed, and the remaining pre-substrate forms a substrate body and multiple trench structures located on the substrate body. A filling layer is formed in a one-to-one correspondence in the trench structure. The surface of the filling layer is flush with the surface of the substrate body. The material of the filling layer includes silicon carbide, and the material of the filling layer is lattice-matched with the material of the substrate body.

8. The method for preparing the substrate structure according to claim 7, characterized in that, Patterning the prepared substrate includes: The prepared substrate is patterned using plasma etching.

9. The method for preparing the substrate structure according to claim 7, characterized in that, A filling layer is formed in a one-to-one correspondence within the trench structure, comprising: A first sub-filling layer is formed in the trench structure using atomic layer deposition; A second sub-filling layer is formed on the surface of the first sub-filling layer using chemical vapor deposition, and the first sub-filling layer and the second sub-filling layer constitute the filling layer.

10. A semiconductor structure, characterized in that, include: The substrate structure according to any one of claims 1 to 6, or the substrate structure prepared by the method of any one of claims 7 to 9; An epitaxial layer is located on the surface of the substrate structure that has a filling layer.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure also includes: A buffer layer is located between the substrate structure and the epitaxial layer.

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