Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor having further improved mechanical strength. A laminated ceramic capacitor (1) is provided with: a laminated body (2) including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the first main face (M1) and the second main face (M2) face each other in the height direction (T), the first side face (S1) and the second side face (S2) face each other in the width direction (W) orthogonal to the height direction (T), and the first end face (E1) and the second end face (E2) face each other in the length direction (L) orthogonal to the height direction (T) and the width direction (W). And an external electrode layer provided on the laminate (2) and connected to a portion of the internal electrode layer, in which when the crystal orientation of the crystal grains (C) of the dielectric layer is measured by electron backscatter diffraction, the crystal orientation of the crystal grains (C) is measured by electron backscatter diffraction within an observation range of 2 [mu] square, and the crystal orientation of the crystal grains (C) is measured by electron backscatter diffraction. There are two or more groups of crystal grains in which the difference in crystal orientation between two adjacent crystal grains (C) is within 5 degrees with respect to an arbitrary direction.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] In recent years, the application of multilayer ceramic capacitors in electronic devices requiring high dielectric constants and high reliability, such as small automotive equipment, has been advancing. Patent Document 1 describes a technique for improving the performance of multilayer ceramic capacitors by adjusting the distribution of nickel near grain boundaries.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-228590 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] However, the technology described in Patent Document 1 may not provide sufficient improvements in electrical characteristics or reliability. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a multilayer ceramic capacitor having further improved mechanical strength.

[0008] A multilayer ceramic capacitor according to the present invention comprises: a laminate including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate having a first principal surface and a second principal surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and an external electrode layer provided on the laminate and connected to a portion of the internal electrode layers, wherein, when the crystal orientation of crystal grains in the dielectric layer is measured by electron backscatter diffraction, there are two or more sets of crystal grains in which the difference in crystal orientation between two adjacent crystal grains within an observation range of 2 μm square is within 5 degrees based on any direction.

[0009] Effects of the Invention

[0010] According to the present invention, a multilayer ceramic capacitor having further improved mechanical strength can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a perspective view of the multilayer ceramic capacitor according to the first embodiment.

[0012] Figure 2 yes Figure 1 Line II cross-sectional view.

[0013] Figure 3 yes Figure 1 Cross-sectional view along line II-II.

[0014] Figure 4A is an image quality map showing the crystal grains observed in the example of Embodiment 1.

[0015] Figure 4B is a crystal orientation map made based on Figure 4A

[0016] Figure 5A is an image quality map showing the crystal grains observed in the comparative example of Embodiment 1.

[0017] Figure 5B is a crystal orientation map made based on Figure 5A

[0018] Figure 6A is a graph showing the peak diffraction angle of the example of Embodiment 2.

[0019] Figure 6B is a graph showing the peak diffraction angle of the comparative example of Embodiment 2.

[0020] Figure 7A is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0021] Figure 7B is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0022] Figure 7C is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0023] Figure 7D is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0024] Figure 7E is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0025] Figure 7F is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0026] Figure 7G is a graph showing the case where the crystal orientation (100) plane was observed in observation by high-angle scattering dark-field scanning transmission electron microscopy.

[0027] Figure 7H ​​is a view showing a case where a crystal orientation (100) plane is not observed in observation by a high-angle scattering dark field scanning transmission electron microscope.

[0028] Figure 8 is a view showing a case where observation is performed by a high-angle scattering dark field scanning transmission electron microscope. DETAILED DESCRIPTION

[0029] (Embodiment 1)

[0030] Based on Figure 1 A mode for carrying out the invention will be described. Figure 1 is a perspective view of the multilayer ceramic capacitor 1 of Embodiment 1 of the present invention. Furthermore, Figure 1 A so-called two-terminal multilayer ceramic capacitor is shown. However, the multilayer ceramic capacitor 1 of the present invention is not limited to a two-terminal multilayer ceramic capacitor. The multilayer ceramic capacitor 1 of the present invention can also be a three-terminal or the like multiterminal multilayer ceramic capacitor.

[0031] (Laminate)

[0032] The laminate 2 includes a plurality of dielectric layers and a plurality of internal electrode layers which are laminated. The shape of the laminate 2 is substantially a rectangular parallelepiped shape.

[0033] In the laminate 2, a direction in which the dielectric layers and the internal electrode layers are laminated is set as a height direction T. A direction orthogonal to the height direction T is set as a width direction W. A direction orthogonal to the height direction T and the width direction W is set as a length direction L.

[0034] In the laminate 2, one of two faces facing each other in the height direction T is set as a first main face Ml. The other one is set as a second main face M2. In the laminate 2, one of two faces facing each other in the width direction W is set as a first side face SI. The other one is set as a second side face S2. In the laminate 2, one of two faces facing each other in the length direction L is set as a first end face El. The other one is set as a second end face E2.

[0035] Regarding the cross section of the laminate 2, a I-I line cross section of Figure 1 is set as an LT cross section. Regarding the cross section of the laminate 2, a II-II line cross section of Figure 1 is set as a WT cross section.

[0036] A portion where three faces of the laminate 2 intersect is set as a corner portion of the laminate 2, and a portion where two faces of the laminate 2 intersect is set as an edge line portion of the laminate 2. It is preferable that a round corner is provided at the corner portion and the edge line portion.

[0037] (Dielectric Layer)

[0038] The total number of pieces of the dielectric layers stacked in the laminate 2 is preferably 15 or more and 2000 or less. The main material of the dielectric layer is a ceramic material. Examples of the ceramic material are dielectric ceramics in which barium titanate, calcium titanate, strontium titanate, calcium zirconate, or the like is the main component. The ceramic material can also be a dielectric ceramic obtained by adding a secondary component such as a manganese compound, an iron compound, a chromium compound, a cobalt compound, a nickel compound, or the like to these main components.

[0039] The dielectric layer includes a crystal grain. The crystal grain is a particle that becomes the main component of the dielectric layer and is composed of a perovskite oxide including an A-site element and a B-site element. The perovskite oxide has a composition represented by the general formula: AB03. The atoms of the A-site element and the atoms of the B-site element are ionized and occupy the A-site and the B-site of the perovskite structure, respectively. As the A-site element, elements such as barium, calcium, and strontium, which are relatively large in ionic size, are exemplified. In addition, as the B-site element, elements such as titanium, zirconium, and hafnium, which are relatively small in ionic size, are exemplified.

[0040] The combination of the A-site element and the B-site element is not particularly limited as long as the perovskite structure is maintained. In addition, the A-site element and the B-site element can each include only one element, or a plurality of elements in combination.

[0041] It is preferable that the A-site element include barium and the B-site element include titanium. That is, the perovskite oxide is preferably a barium titanate-based compound.

[0042] The thickness of one layer of the dielectric layer is preferably 0.3 μm or more and 10 μm or less.

[0043] (Division of the laminate)

[0044] Based on Figure 2 The division of the length direction L of the laminate 2 will be described. Figure 2 is Figure 1 is a cross-sectional view taken along the line I-I of the laminate 2. The laminate 2 can be divided into a first main surface side outer layer portion OL1, an inner layer range IL, and a second main surface side outer layer portion OL2 in the height direction T. The first main surface side outer layer portion OL1, the inner layer range IL, and the second main surface side outer layer portion OL2 are arranged in order from the first main surface M1 toward the second main surface M2 in the height direction T.

[0045] The first main surface side outer layer portion OL1 is a portion between the internal electrode layer closest to the first main surface M1 and the first main surface M1. The inner layer range IL is a range in which the internal electrode layers face each other. The second main surface side outer layer portion OL2 is a portion between the internal electrode layer closest to the second main surface M2 and the second main surface M2.

[0046] The first main surface side outer layer portion OL1 is located on the first main surface M1 side of the laminate 2. The first main surface side outer layer portion OL1 is formed by a collection of a plurality of dielectric layers located between the first main surface M1 and the inner electrode layer closest to the first main surface M1. The first main surface side outer layer portion OL1 is formed by a plurality of dielectric layers located between the first main surface M1 and the outermost surface of the inner layer range IL on the first main surface M1 side and the extension line of the outermost surface.

[0047] The second main surface side outer layer portion OL2 is located on the second main surface M2 side of the laminate 2. The second main surface side outer layer portion OL2 is formed by a collection of a plurality of dielectric layers located between the second main surface M2 and the inner electrode layer closest to the second main surface M2. The second main surface side outer layer portion OL2 is formed by a plurality of dielectric layers located between the second main surface M2 and the outermost surface of the inner layer range IL on the second main surface M2 side and the extension line of the outermost surface.

[0048] The inner layer range IL is a range sandwiched by the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2.

[0049] The dielectric layer disposed in the first main surface side outer layer portion OL1 and the second main surface side outer layer portion OL2 among the dielectric layers is set as an outer layer dielectric layer 3. The dielectric layer disposed in the inner layer range IL among the dielectric layers is set as an inner layer dielectric layer 4.

[0050] In the description of length and position, the following terms are sometimes used.

[0051] The length in the length direction L is set as the length direction length. The length in the width direction W is set as the width direction length. The length in the height direction T is set as the height direction length.

[0052] The position of the length that is half the length direction length is set as the central position in the length direction L. The central position in the length direction L is set as the length direction central position.

[0053] The position of the width that is half the width direction length is set as the central position in the width direction W. The central position in the width direction W is set as the width direction central position.

[0054] The position of the height that is half the height direction length is set as the central position in the height direction T. The central position in the height direction T is set as the height direction central position.

[0055] The end in the length direction L is set as the length direction end. The end in the width direction W is set as the width direction end. The end in the height direction T is set as the height direction end.

[0056] The size of the laminate 2 is not particularly limited. The length direction length of the laminate is preferably 0.2 mm or more and 10 mm or less. The width direction length of the laminate 2 is preferably 0.1 mm or more and 5 mm or less. The height direction length of the laminate 2 is preferably 0.1 mm or more and 5 mm or less.

[0057] (L gap)

[0058] The division of the length direction L of the laminate 2 will be described. The laminate 2 can be divided into a first end surface side outer layer portion LG1, a length direction facing portion LF, and a second end surface side outer layer portion LG2 in the length direction L. The first end surface side outer layer portion LG1, the length direction facing portion LF, and the second end surface side outer layer portion LG2 are arranged in this order from the first end surface E1 toward the second end surface E2 in the length direction L.

[0059] The length direction facing portion LF is a portion in which the internal electrode layers face each other in the height direction T. The first end surface side outer layer portion LG1 is a portion between the length direction facing portion LF and the first end surface E1. The second end surface side outer layer portion LG2 is a portion between the length direction facing portion LF and the second end surface E2. The length direction facing portion LF is a portion corresponding to the facing electrode portion of the internal electrode layer. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are portions corresponding to the lead electrode portion of the internal electrode layer. The first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L gaps.

[0060] Further, the facing electrode portion includes a first facing electrode portion 7a and a second facing electrode portion 7b. In addition, the lead electrode portion includes a first lead electrode portion 8a and a second lead electrode portion 8b. The facing electrode portion and the lead electrode portion will be described later.

[0061] The first end surface side outer layer portion LG1 is located on the first end surface E1 side. The first end surface side outer layer portion LG1 is located between the first end surface E1 and the end of the second internal electrode layer 6b on the first end surface E1 side.

[0062] The second end surface side outer layer portion LG2 is located on the second end surface E2 side. The second end surface side outer layer portion LG2 is located between the second end surface E2 and the end of the first internal electrode layer 6a on the second end surface E2 side.

[0063] (W gap)

[0064] Based on Figure 3 The division of the width direction W of the laminate 2 will be described. Figure 3 is Figure 1FIG. 2 is a II-II line sectional view of the stack 2. The stack 2 can be divided into a first side surface side outer layer portion WG1, a width direction facing portion WF, and a second side surface side outer layer portion WG2 in the width direction W. The first side surface side outer layer portion WG1, the width direction facing portion WF, and the second side surface side outer layer portion WG2 are arranged in this order from the first side surface S1 toward the second side surface S2 in the width direction W.

[0065] The width direction facing portion WF is a portion in which the internal electrode layers face each other in the height direction T. The first side surface side outer layer portion WG1 is a portion between the width direction facing portion WF and the first side surface S1. The second side surface side outer layer portion WG2 is a portion between the width direction facing portion WF and the second side surface S2. The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are also referred to as W gaps.

[0066] The first side surface side outer layer portion WG1 and the second side surface side outer layer portion WG2 are portions in which the internal electrode layers are not present in the height direction T. The first side surface side outer layer portion WG1 is located on the first side surface S1 side.

[0067] The second side surface side outer layer portion WG2 is located on the second side surface S2 side. The second side surface side outer layer portion WG2 is formed of a plurality of dielectric layers located between the second side surface S2 and the most surface of the width direction facing portion WF on the second side surface S2 side.

[0068] (Internal electrode layer)

[0069] The internal electrode layer includes a plurality of first internal electrode layers 6a and a plurality of second internal electrode layers 6b. The first internal electrode layer 6a is an internal electrode layer exposed at the first end surface E1. The second internal electrode layer 6b is an internal electrode layer exposed at the second end surface E2.

[0070] The first internal electrode layer 6a can be divided into a first facing electrode portion 7a and a first lead electrode portion 8a. The first facing electrode portion 7a is a portion facing the second internal electrode layer 6b. The first lead electrode portion 8a is a portion led out to the first end surface E1 of the stack 2 from the first facing electrode portion 7a.

[0071] The end of the first lead electrode portion 8a on the first end surface E1 side is led out to the surface of the first end surface E1 of the stack 2. The end of the first lead electrode portion 8a led out to the first end surface E1 is exposed at the first end surface E1.

[0072] The second internal electrode layer 6b can be divided into a second facing electrode portion 7b and a second lead electrode portion 8b. The second facing electrode portion 7b is a portion facing the first internal electrode layer 6a. The second lead electrode portion 8b is a portion led out to the second end surface E2 of the stack 2 from the second facing electrode portion 7b.

[0073] The end of the second lead-out electrode portion 8b on the second end surface E2 side is led out to the surface of the second end surface E2 of the laminate 2. The end of the second lead-out electrode portion 8b led out to the second end surface E2 is exposed on the second end surface E2.

[0074] The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be, for example, a metal such as nickel, copper, silver, palladium, gold, or the like. The material of the first internal electrode layer 6a and the second internal electrode layer 6b can be an alloy including at least one of the aforementioned metals, such as a silver-palladium alloy, or the like.

[0075] In the multilayer ceramic capacitor 1, a capacitor is formed by the first opposing electrode portion 7a and the second opposing electrode portion 7b opposing each other with the internal dielectric layer 4 interposed therebetween. Thus, the multilayer ceramic capacitor 1 exhibits the characteristics of a capacitor.

[0076] The thickness of the first internal electrode layer 6a and the thickness of the second internal electrode layer 6b are, for example, preferably in the range of 0.2 μm or more and 2.0 μm or less. The total number of pieces, which is the sum of the number of pieces of the first internal electrode layer 6a and the number of pieces of the second internal electrode layer 6b, is preferably 15 pieces or more and 2000 pieces or less.

[0077] (Internal Layer)

[0078] The portion where the first internal electrode layer 6a and the second internal electrode layer 6b oppose each other is provided as an internal layer portion 10. The internal layer portion 10 is Figure 2 the portion where the length direction opposing portion LF and Figure 3 the portion where the width direction opposing portion WF and the internal layer range IL intersect. The shape of the internal layer portion 10 is substantially cuboid. In Figure 2 the length direction opposing portion LF and the internal layer range IL are shown as the internal layer portion 10. Also, in Figure 3 the width direction opposing portion WF and the internal layer range IL are shown as the internal layer portion 10.

[0079] (External Electrode)

[0080] The external electrode will be described. The external electrode includes a first external electrode 20a and a second external electrode 20b. The first external electrode 20a is an external electrode connected to the first internal electrode layer 6a. The second external electrode 20b is an external electrode connected to the second internal electrode layer 6b.

[0081] The first external electrode 20a is disposed on the first end surface E1, a portion of the first major surface M1, a portion of the second major surface M2, a portion of the first side surface S1, and a portion of the second side surface S2. The second external electrode 20b is disposed on the second end surface E2, a portion of the first major surface M1, a portion of the second major surface M2, a portion of the first side surface S1, and a portion of the second side surface S2.

[0082] The external electrode includes a base electrode layer and a plating layer. The plating layer includes a Ni plating layer and a Sn plating layer. These layers are arranged in the order of the base electrode layer, the Ni plating layer, and the Sn plating layer from the end surface of the laminate 2.

[0083] The first external electrode 20a includes a first base electrode layer 22a, a first Ni plating layer 23a, and a first Sn plating layer 24a. The second external electrode 20b includes a second base electrode layer 22b, a second Ni plating layer 23b, and a second Sn plating layer 24b.

[0084] (Base electrode layer)

[0085] The first base electrode layer 22a is arranged on the first end surface El of the laminate 2, covering the first end surface El. The first base electrode layer 22a extends from the first end surface El to a part of the first main surface Ml, a part of the second main surface M2, a part of the first side surface Sl, and a part of the second side surface S2.

[0086] The second base electrode layer 22b is arranged on the second end surface E2 of the laminate 2, covering the second end surface E2. The second base electrode layer 22b extends from the second end surface E2 to a part of the first main surface Ml, a part of the second main surface M2, a part of the first side surface Sl, and a part of the second side surface S2.

[0087] The base electrode layer includes a glass component and a metal. As the glass component, at least one selected from B, Si, Ba, Mg, Al, Li, and the like is included. As the metal, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, and the like is included, for example.

[0088] (Ni plating layer and Sn plating layer)

[0089] The first Ni plating layer 23a is arranged so as to cover the first base electrode layer 22a. The first Sn plating layer 24a is arranged so as to cover the first Ni plating layer 23a.

[0090] The second Ni plating layer 23b is arranged so as to cover the second base electrode layer 22b. The second Sn plating layer 24b is arranged so as to cover the second Ni plating layer 23b.

[0091] The Ni plating layer can prevent the base electrode layer from being eroded by solder when the laminate ceramic capacitor 1 is mounted. The Sn plating layer can improve the wettability of solder when the laminate ceramic capacitor 1 is mounted, making the mounting easy.

[0092] Further, a conductive resin layer can be arranged between the base electrode layer and the Ni plating layer. The conductive resin layer can include an epoxy resin and a metal filler, or the like.

[0093] The size of the multilayer ceramic capacitor 1 is not particularly limited. The preferable length direction length of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode is 0.2 mm or more and 10 mm or less. The preferable height direction length of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode is 0.1 mm or more and 5 mm or less. The preferable width direction length of the multilayer ceramic capacitor 1 including the multilayer body 2 and the external electrode is 0.1 mm or more and 10 mm or less.

[0094] (Method for manufacturing multilayer ceramic capacitor)

[0095] The method for manufacturing the multilayer ceramic capacitor 1 will be described.

[0096] (1) An electrically conductive paste for a dielectric sheet and an internal electrode layer is prepared. The electrically conductive paste for a dielectric sheet and an internal electrode layer includes a binder and a solvent. The binder and the solvent can be a publicly known organic binder and an organic solvent, etc.

[0097] (2) The electrically conductive paste for an internal electrode layer is printed on a dielectric sheet in a prescribed pattern. An internal electrode layer pattern is formed by the printing of the electrically conductive paste. The printing can be performed by screen printing or gravure printing, etc.

[0098] (3) A dielectric sheet for an outer layer portion is laminated a prescribed number of sheets. The dielectric sheet for an outer layer portion is not printed with an internal electrode layer pattern. A dielectric sheet printed with an internal electrode layer pattern is laminated in order on top of the laminated dielectric sheets. Further, a dielectric sheet for an outer layer portion is laminated a prescribed number of sheets on top of the dielectric sheet printed with an internal electrode layer pattern. A laminated sheet is manufactured by the lamination thereof.

[0099] (4) A laminated block is manufactured by pressing the laminated sheet in the height direction. The method of pressing can be set to isostatic pressing.

[0100] (5) The laminated block is cut to a prescribed size. By this cutting, a laminated chip is cut out. When cutting, a round corner can be provided to the corners and edges of the laminated chip. The method of providing a round corner can be set to barrel polishing.

[0101] (6) The laminated chip is fired. A multilayer body is manufactured by this firing. The preferable firing temperature is 900°C or more and 1200°C or less. The firing temperature can be changed according to the materials of the dielectric and the internal electrode layer.

[0102] The cooling after heating to the firing temperature is set to be faster than natural cooling. For example, cooling from 900°C or higher and 1200°C or lower as the firing temperature to 100°C or higher and 300°C or lower in 10 minutes or less. It is preferable to cool from 1000°C to 200°C in 7 minutes or less, for example. It is more preferable to cool from 1000°C to 200°C in 5 minutes or less, for example. It is further preferable to cool from 1000°C to 200°C in 1 minute or less, for example.

[0103] By cooling like this, productivity can be improved compared to the case of natural cooling by just leaving as it is.

[0104] Here, the cooling does not mean just arranging the stacked chip in a gas of a prescribed temperature. The cooling means more actively cooling the stacked chip. For example, a gas of a prescribed temperature can be blown to the stacked chip. Or, a solid or liquid of a prescribed temperature can be brought into contact with the stacked chip.

[0105] (External electrode)

[0106] Next, an external electrode is formed. First, a conductive paste that becomes a base electrode layer is applied to both end surfaces of the laminate 2. The conductive paste includes a glass component and a metal component, and the like. The application of the conductive paste can be performed by a method such as dipping. After the application, a firing process is performed to form the base electrode layer. The temperature of the firing process is preferably 500°C or higher and 900°C or lower. In addition, the time of the firing process is preferably 30 minutes or longer and 2 hours or shorter.

[0107] Next, a Ni plating layer is formed on the surface of the base electrode layer. Further, a Sn plating layer is formed on the surface of the Ni plating layer. The Ni plating layer and the Sn plating layer can be formed by a barrel plating method or the like. In this way, the stacked ceramic capacitor 1 is obtained.

[0108] The crystal orientation of the crystal grains of the dielectric layer in the stacked ceramic capacitor 1 of Embodiment 1 is described.

[0109] (Crystal orientation)

[0110] In the dielectric layer in the stacked ceramic capacitor 1 of Embodiment 1, the number of groups of crystal grains whose crystal orientations are close to each other is large in adjacent crystal grains. Hereinafter, the crystal orientation calculated by an electron backscatter diffraction method (EBSD: Electron Backscatter Diffraction Pattern) is described.

[0111] Figure 4A and Figure 4B An example of Embodiment 1 is shown, Figure 5A and Figure 5B A comparative example of Embodiment 1 is shown. Figure 4A andFigure 5B is an image quality map showing the case of the crystal grain C observed in the ND direction by the electron backscatter diffraction method.

[0112] Figure 4B is a crystal orientation map made based on the image quality map shown in Figure 4A . Also, Figure 5B is a crystal orientation map made based on the image quality map shown in Figure 5A . The crystal orientation map is also called an inverse pole figure (IPF) map.

[0113] Regarding Figure 4A and Figure 4B , Figure 5A and Figure 5B , the examples of Embodiment 1 and the comparative example of Embodiment 1 were subjected to the measurement based on the electron backscatter diffraction method with respect to the following samples. The laminated ceramic capacitor was polished to expose the surface of the sample. The polishing was performed by continuously grinding the surface parallel to the width direction W and the height direction T. The surface of the sample was set to the WT cross section at the central position in the length direction T.

[0114] In the measurement of the crystal orientation, the outer layer portion was measured. This is because the crystal orientation has a high correlation with the cracks generated in the outer layer portion.

[0115] In addition, the measurement based on the electron backscatter diffraction method was performed using a thin sample. The measurement was performed after the WT cross section at the central position in the length direction T of the laminated ceramic capacitor described above was processed into a thin sample. Specifically, the surface opposite to the measurement surface was polished so that the thickness of the sample became 100 nm, and then the WT cross section was measured.

[0116] The range in which the crystal orientation was measured in the outer layer portion was 2 μm square. The number of the crystal grains included in the observation range was usually observed to be 50 or more and 250 or less.

[0117] In the crystal orientation maps shown in Figure 4B and Figure 5B , in the adjacent crystal grains, a broken line A was described at the grain boundary of the two crystal grains whose difference in the crystal orientation was within 5 degrees with the arbitrary direction as the reference.

[0118] As shown in Figure 4B , in the example of Embodiment 1, the group of the crystal grains whose difference in the crystal orientation of the adjacent two crystal grains was within 5 degrees with the arbitrary direction as the reference had 24 groups in the measurement range shown in Figure 4B .

[0119] On the contrary, in the comparative example of Embodiment 1, as shown in Figure 5B , it was 1 group.

[0120] Also, in the example of Embodiment 1, the group of three crystal grains including one crystal grain, and two crystal grains adjacent to the one crystal grain and having a misorientation of 5 degrees or less from the crystal orientation of the one crystal grain has four groups. In contrast, in the comparative example of Embodiment 1, the number of groups is 0.

[0121] Thus, in the dielectric layers of the multilayer ceramic capacitor 1 of Embodiment 1, the number of groups of crystal grains having a close crystal orientation to each other is large.

[0122] Further, regarding the ratio of crystal grains having other crystal grains adjacent thereto with a difference in crystal orientation of 5 degrees or less as a reference in an arbitrary direction with respect to all crystal grains, the multilayer ceramic capacitor 1 of Embodiment 1 is also higher than the conventional multilayer ceramic capacitor. In Figure 4B In the multilayer ceramic capacitor 1 of Embodiment 1 shown in Table 1, 45 out of the total of 166 crystal grains have other crystal grains adjacent thereto with a difference in crystal orientation of 5 degrees or less as a reference in an arbitrary direction. The ratio is 27.1%. In contrast, in the comparative example of Embodiment 1 shown in Table 1, 2 out of the total of 113 crystal grains have other crystal grains adjacent thereto with a difference in crystal orientation of 5 degrees or less as a reference in an arbitrary direction. The ratio is 1.8%. Figure 5B

[0123] The generation of cracks in the outer layer portion was evaluated for the multilayer ceramic capacitors of the example of Embodiment 1 and the comparative example of Embodiment 1.

[0124] The evaluation method and the determination criteria of the generation of cracks are described below. For 10 multilayer ceramic capacitors, a flexural test was performed by the method of JIS C 6484, and the generation of cracks in the dielectric layers was evaluated with a flexural amount of 5 mm.

[0125] In the multilayer ceramic capacitors of the example of Embodiment 1, no cracks were generated, in contrast, in the multilayer ceramic capacitors of the comparative example of Embodiment 1, cracks were generated.

[0126] (Measurement method)

[0127] The length, thickness, and the like of each portion can be measured as follows. The multilayer ceramic capacitor 1 is ground to the central position in the width direction. Then, the cross section exposed by the grinding is observed with an optical microscope or the like. Measurement can be performed from the observed cross section.

[0128] (Embodiment 2)

[0129] A multilayer ceramic capacitor 1 of Embodiment 2 is described. In the following description, matters different from Embodiment 1 are mainly described. Matters not specifically described can be set to be the same as Embodiment 1.​

[0130] In the technology described in Patent Document 1, the improvement in the electrical characteristics or reliability is sometimes insufficient. Thus, an object of Embodiment 2 is to provide a multilayer ceramic capacitor with a larger relative dielectric constant.

[0131] The multilayer ceramic capacitor of Embodiment 2 includes: a laminate including a plurality of dielectric layers and a plurality of internal electrode layers, having first and second main surfaces opposing in a height direction, first and second side surfaces opposing in a width direction orthogonal to the height direction, and first and second end surfaces opposing in a length direction orthogonal to the height direction and the width direction; and an external electrode layer provided to the laminate and connected to a part of the internal electrode layers, wherein, in a case where X-ray diffraction intensity of the dielectric layers is measured by X-ray stress measurement in a cross section of the laminate parallel to the width direction and the height direction, the width direction is set as an azimuth angle of 0 degrees, a counterclockwise direction is set as a positive direction of the azimuth angle, a diffraction angle at which the X-ray diffraction intensity becomes the largest when an incident angle of X-rays is changed from a sample to a normal line of the sample at an azimuth angle of 30 degrees is set as a first peak diffraction angle, a diffraction angle at which the X-ray diffraction intensity becomes the largest when the incident angle of the X-rays is changed from the sample to the normal line of the sample at an azimuth angle of 90 degrees is set as a second peak diffraction angle, and a difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more.

[0132] According to the multilayer ceramic capacitor of Embodiment 2, a multilayer ceramic capacitor with a larger relative dielectric constant can be provided.

[0133] The characteristics of the dielectric layers in the multilayer ceramic capacitor 1 of Embodiment 2 are described.

[0134] (Peak Diffraction Angle)

[0135] The peak diffraction angle is described. In the dielectric layers in the multilayer ceramic capacitor 1 of Embodiment 2, the peak diffraction angle differs depending on the measured azimuth angle. The peak diffraction angle refers to a diffraction angle at which the X-ray diffraction intensity becomes the largest.

[0136] The peak diffraction angle can be measured by X-ray stress measurement. The X-ray stress measurement is as described in, for example, Vol. 47, No. 11, pp. 1188-1194, Nov. 1998 of the journal "Materials" (J. Soc. Mat. Sci., Japan).

[0137] In X-ray stress measurement, X-rays are radiated to a sample, and the diffracted X-rays from the sample are detected. The angle difference between the radiating direction of the X-rays to the sample and the outgoing direction of the diffracted X-rays from the sample is the diffraction angle. The diffraction angle is equivalent to twice the size of the Bragg angle.

[0138] The detection of the diffracted X-rays is performed while changing the radiating angle of the X-rays to the sample. The radiating angle of the X-rays to the sample can be changed by changing the radiating direction from the direction of the normal line of the sample surface to the direction parallel to the sample surface. Alternatively, the radiating angle of the X-rays to the sample can be changed by changing the radiating direction from the direction parallel to the sample surface to the direction of the normal line of the sample surface.

[0139] The radiating angle of the X-rays to the sample is changed, and the intensity of the diffracted X-rays from the (222) crystal plane of BaTiO3 becomes the maximum. This radiating angle is the peak diffraction angle.

[0140] The peak diffraction angle can be measured by changing the azimuth angle. The azimuth angle refers to the direction in which the angle is changed when the radiating angle of the X-rays is changed. In other words, the azimuth angle refers to the direction in which the radiating direction is inclined when the radiating direction is changed from the direction of the normal line of the sample surface to the direction parallel to the sample surface.

[0141] The sample used in the measurement of the peak diffraction angle is described. The surface of the sample is exposed by polishing a multilayer ceramic capacitor. The polishing is performed by continuously grinding the surface parallel to the width direction W and the height direction T. The surface of the sample is set to the WT cross section at the central position in the length direction T.

[0142] The circular range of 500 μm in diameter in the central portion of the WT cross section is set as the radiating range of the X-rays. The inner layer range IL of the multilayer body 2 becomes the measurement range.

[0143] The width direction W in the WT cross section is set as the azimuth angle 0 degree. The direction rotated counterclockwise from the width direction W is set as the positive direction of the azimuth angle.

[0144] When the incident angle of the X-rays is changed from the sample surface to the direction of the normal line of the sample surface at the azimuth angle 30 degrees, the diffraction angle at which the X-ray diffraction intensity becomes the maximum is set as the first peak diffraction angle. In addition, when the incident angle of the X-rays is changed from the sample surface to the direction of the normal line of the sample surface at the azimuth angle 90 degrees, the diffraction angle at which the X-ray diffraction intensity becomes the maximum is set as the second peak diffraction angle.

[0145] Figure 6A and Figure 6B is a graph showing the peak diffraction angles of the examples of Embodiment 2 and the comparative examples of Embodiment 2. Figure 6A the peak diffraction angles of the examples of Embodiment 2, Figure 6BThe peak diffraction angle of the comparative example of Embodiment 2 is shown. In Figure 6A The peak diffraction angle when the azimuth angle is 30 degrees and the peak diffraction angle when the azimuth angle is 90 degrees are shown in Figure 6B

[0146] As shown in Figure 6A Figure 6B In the example of Embodiment 2, the difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more. In contrast, in the comparative example of Embodiment 2, the difference between the first peak diffraction angle and the second peak diffraction angle is less than 0.023 degrees.

[0147] [Table 1]

[0148]

[0149] [Table 2]

[0150]

[0151] Table 1 and Table 2 are tables showing the relative dielectric constant and the like of the example of Embodiment 2 and the comparative example of Embodiment 2. Table 1 shows the case where the number of laminated pieces is 300 and the thickness of the dielectric layer is 1.0 μm, and Table 2 shows the case where the number of laminated pieces is 410 and the thickness of the dielectric layer is 0.6 μm. In either case, in the example of Embodiment 2, the relative dielectric constant shows a high value exceeding 3800. On the other hand, in the comparative example of Embodiment 2, the relative dielectric constant does not exceed 3800.

[0152] Thus, by making the difference between the first peak diffraction angle and the second peak diffraction angle 0.023 degrees or more, a higher relative dielectric constant can be achieved.

[0153] Further, regarding the size of the laminated ceramic capacitor of the example of Embodiment 2 and the comparative example of Embodiment 2, the length direction L is 1.0 mm, and the width direction W and the height direction T are 0.5 mm. In addition, the number of laminated pieces of the internal electrode layer is 300 pieces or 410 pieces, and the thickness of the dielectric layer is 0.60 μm or 1 μm. The thickness of the internal electrode layer is 0.5 μm.

[0154] (Measurement method)

[0155] The length and thickness and the like of each part can be measured as follows. The laminated ceramic capacitor 1 is ground to the central position in the width direction. Then, the cross section exposed by the grinding is observed using an optical microscope or the like. Measurement can be performed from the observed cross section. (1)

[0157] A laminated ceramic capacitor comprising:

[0158] ​​A laminate including a plurality of dielectric layers and a plurality of internal electrode layers, has first and second main surfaces opposite in a height direction, first and second side surfaces opposite in a width direction orthogonal to the height direction, and first and second end surfaces opposite in a length direction orthogonal to the height direction and the width direction; and

[0159] An external electrode layer is provided to the laminate and connected to a portion of the internal electrode layers,

[0160] wherein

[0161] In a case where X-ray diffraction intensity of the dielectric layer is measured by X-ray stress measurement in a cross section of the laminate parallel to the width direction and the height direction,

[0162] The width direction is set as an azimuth angle of 0 degrees,

[0163] The counterclockwise direction is set as a positive direction of the azimuth angle,

[0164] In a case where the incident angle of X-rays is changed from the direction of the normal line of the sample to the sample at an azimuth angle of 30 degrees, an angle of diffraction at which the X-ray diffraction intensity becomes the maximum is set as a first peak diffraction angle,

[0165] In a case where the incident angle of X-rays is changed from the direction of the normal line of the sample to the sample at an azimuth angle of 90 degrees, an angle of diffraction at which the X-ray diffraction intensity becomes the maximum is set as a second peak diffraction angle,

[0166] At this time,

[0167] The difference between the first peak diffraction angle and the second peak diffraction angle is 0.023 degrees or more.

[0168] (Embodiment 3)

[0169] A laminated ceramic capacitor 1 of Embodiment 3 will be described. In the following description, matters different from Embodiment 1 will be mainly described. Matters not particularly described can be set to be the same as Embodiment 1.

[0170] In the technology described in Patent Document 1, improvement in electrical characteristics or reliability is sometimes insufficient. Thus, an object of Embodiment 3 is to provide a laminated ceramic capacitor with a larger relative dielectric constant.

[0171] The multilayer ceramic capacitor of Embodiment 3 includes: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers, having first and second main surfaces opposite in a height direction, first and second side surfaces opposite in a width direction orthogonal to the height direction, and first and second end surfaces opposite in a length direction orthogonal to the height direction and the width direction; and an external electrode layer provided to the multilayer body and connected to a part of the internal electrode layers, wherein, when the dielectric layer is observed by high-angle annular dark-field scanning transmission electron microscopy, an optical axis of a microscope is arranged in a direction perpendicular to an observation surface, and the observation surface is tilted from a plane perpendicular to the optical axis by 20 degrees or more and 20 degrees or less, and thereby a (100) plane of a plurality of crystal orientations is observed.

[0172] According to the multilayer ceramic capacitor of Embodiment 3, a multilayer ceramic capacitor having a larger relative dielectric constant can be provided.

[0173] The detection of a (100) plane of a crystal orientation of a dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 3 will be described.

[0174] (100) plane of a crystal orientation

[0175] In the dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 3, the (100) plane of a crystal orientation has a high probability of existence. Hereinafter, the description will be made based on observation by high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM).

[0176] Figures 7A to 7G A case in which the (100) plane of a crystal orientation is observed in observation by high-angle annular dark-field scanning transmission electron microscopy is shown, Figure 7H A case in which the (100) plane of a crystal orientation is not observed is shown. The observation of the observation surface by high-angle annular dark-field scanning transmission electron microscopy is performed while tilting the observation surface.

[0177] Figure 8 is a diagram showing a case in which the observation surface is observed by high-angle annular dark-field scanning transmission electron microscopy. In Figure 8 In the XYZ orthogonal coordinate system shown in FIG. 10, when the observation surface is arranged in the YZ plane, the electron beam in the high-angle annular dark-field scanning transmission electron microscopy is irradiated from the positive side of the X axis toward the negative side of the X axis as shown by an arrow EB.

[0178] The observation surface arranged in the YZ plane can be rotated around the Z axis and rotated around the Y axis. InFigure 8 The rotation around the Z-axis is shown by arrow A. In addition, the rotation around the Y-axis is shown by arrow B.

[0179] In the rotation around the Z-axis, the angle after the rotation is set to an angle α. The rotation to the positive direction of the X-axis is set to the positive direction in the angle α. In the rotation around the Y-axis, the angle after the rotation is set to an angle β. The rotation to the positive direction of the X-axis is set to the positive direction in the angle β.

[0180] The observation by the high-angle scattering dark field scanning transmission electron microscope method was performed in the WT cross section at the middle position of the length direction T of the multilayer ceramic capacitor. The multilayer ceramic capacitor was polished so that the WT cross section was exposed. The polishing was performed by continuously grinding a surface parallel to the width direction W and the height direction T.

[0181] In addition, the observation based on the high-angle scattering dark field scanning transmission electron microscope method was performed using a thin slice sample. That is, the above-described thin slice sample including the WT cross section at the middle position of the length direction T of the multilayer ceramic capacitor was produced, and the WT cross section in the thin slice sample was observed. The surface opposite to the WT cross section to be observed was polished, and the thin slice sample was formed so that the thickness of the sample became 70 μm.

[0182] The observation was performed with the center portion of the crystal grain as the object. In the barium titanate having the core-shell structure, the core portion was the observation object.

[0183] Figure 7A The crystal orientation (100) surface observed by tilting the observation surface with α of 1.95 degrees and β of 0.27 degrees is shown. Also, Figure 7B The crystal orientation (100) surface observed by tilting the observation surface with α of 9.84 degrees and β of 1.87 degrees is shown, Figure 7C The crystal orientation (100) surface observed by tilting the observation surface with α of 9.06 degrees and β of 2.35 degrees is shown, Figure 7D The crystal orientation (100) surface observed by tilting the observation surface with α of 0.96 degrees and β of -13.75 degrees is shown, Figure 7E The crystal orientation (100) surface observed by tilting the observation surface with α of 9.21 degrees and β of 11.38 degrees is shown, Figure 7F The crystal orientation (100) surface observed by tilting the observation surface with α of 17.59 degrees and β of 10.94 degrees is shown, Figure 7G The crystal orientation (100) surface observed by tilting the observation surface with α of 17.59 degrees and β of 6.38 degrees is shown.

[0184] In the dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 3, the observation surface is tilted by -20 degrees or more and +20 degrees or less for the angle a, and the observation surface is tilted by -20 degrees or more and +20 degrees or less for the angle β, whereby the crystal orientation (100) plane can be observed.

[0185] On the other hand, in the conventional multilayer ceramic capacitor, the crystal orientation (100) plane cannot be observed by tilting the observation surface by -20 degrees or more and +20 degrees or less for the angle a and by -20 degrees or more and +20 degrees or less for the angle β. The observation result in the case where the crystal orientation (100) plane is not observed becomes Figure 7H like that.

[0186] In the multilayer ceramic capacitor 1 of Embodiment 3 in which the crystal orientation (100) plane can be observed by tilting the observation surface by -20 degrees or more and +20 degrees or less for the angle a and by -20 degrees or more and +20 degrees or less for the angle β, a high dielectric constant can be achieved compared to the conventional multilayer ceramic capacitor.

[0187] In addition, Figures 7A to 7G The observation result of the center portion of the crystal grain is shown. In the multilayer ceramic capacitor 1 of Embodiment 3, in the center portion of the crystal grain in which the crystal orientation (100) plane is difficult to be observed, the crystal orientation (100) plane is observed.

[0188] In addition, in the multilayer ceramic capacitor 1 of Embodiment 3, in the two adjacent crystal grains, the crystal orientation (100) plane is observed.

[0189] As described above, in the multilayer ceramic capacitor 1 of Embodiment 3, the crystal orientation (100) plane is present accurately and with high probability without being deformed.

[0190] (Measurement method)

[0191] The length, the thickness, and the like of each portion can be measured as follows. The multilayer ceramic capacitor 1 is ground to the central position in the width direction. Then, the cross section exposed by the grinding is observed with an optical microscope or the like. The measurement can be performed from the observed cross section. (1)

[0193] A multilayer ceramic capacitor includes:

[0194] a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers stacked, having a first main surface and a second main surface opposite in a height direction, a first side surface and a second side surface opposite in a width direction orthogonal to the height direction, and a first end surface and a second end surface opposite in a length direction orthogonal to the height direction and the width direction; and

[0195] an external electrode layer provided to the laminate and connected to a part of the internal electrode layer,

[0196] wherein

[0197] in a case where the dielectric layer is observed by a high-angle scattering dark field scanning transmission electron microscope,

[0198] an optical axis of a microscope is arranged in a direction perpendicular to the observation surface,

[0199] by tilting the observation surface from a plane perpendicular to the optical axis by 20 degrees or more and 20 degrees or less, a 100 plane of a plurality of crystal orientations is observed. (2)

[0201] The multilayer ceramic capacitor according to (1), wherein

[0202] in the observation, a center portion of a crystal grain included in the dielectric layer is observed. (3)

[0204] The multilayer ceramic capacitor according to (2), wherein

[0205] in the adjacent crystal grains, the 100 plane is observed.

[0206] (Embodiment 4)

[0207] A multilayer ceramic capacitor 1 of Embodiment 4 will be described. In the following description, matters different from Embodiment 1 will be mainly described. Matters not particularly described can be set to be the same as Embodiment 1.

[0208] In the technology described in Patent Document 1, improvement in electrical characteristics or reliability is sometimes insufficient. Thus, an object of Embodiment 4 is to provide a multilayer ceramic capacitor with a larger relative dielectric constant.

[0209] The multilayer ceramic capacitor of Embodiment 4 includes: a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers, having first and second main surfaces opposite in a height direction, first and second side surfaces opposite in a width direction orthogonal to the height direction, and first and second end surfaces opposite in a length direction orthogonal to the height direction and the width direction; and an external electrode layer provided to the multilayer body and connected to a part of the internal electrode layers, wherein a value of a second average grain size / first average grain size is 1.0 or greater, in a case where the first average grain size is a median grain size of the dielectric layers calculated by observation with a scanning transmission electron microscope, and the second average grain size is a median grain size of the dielectric layers calculated in a case where a crystal orientation of a grain of the dielectric layers is determined by electron backscatter diffraction, and grains in which a difference between the crystal orientations of adjacent two grains is within 5 degrees in an arbitrary direction are regarded as one grain.

[0210] According to the multilayer ceramic capacitor of Embodiment 4, a multilayer ceramic capacitor having a larger relative dielectric constant can be provided.

[0211] (Grain size)

[0212] The grain size of the dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 4 is described. In the dielectric layer in the multilayer ceramic capacitor 1 of Embodiment 4, in a case where the grain size calculated based on observation with a scanning transmission electron microscope is compared with the grain size calculated based on a transmission EBSD crystal orientation map, the same or the latter is larger.

[0213] Here, the grain size of the grain refers to a median grain size in an area particle size distribution. The median grain size is also referred to as d50.

[0214] In a case where the grain size is calculated based on the transmission EBSD crystal orientation map, first, the crystal orientation of the grain of the dielectric layer is determined by electron backscatter diffraction. Then, in adjacent two grains, in a case where a difference between the respective crystal orientations is within 5 degrees in an arbitrary direction, the grains are regarded as one particle. Therefore, in adjacent two grains, if the number of grains in which the difference between the respective crystal orientations is within 5 degrees in an arbitrary direction increases, the grain size calculated based on the transmission EBSD crystal orientation map increases.

[0215] [Table 3]

[0216]

[0217] Table 3 is a table showing the cooling time after firing of the laminated ceramic capacitor, and the values of the particle diameter and the relative dielectric constant. The median particle diameter of the crystal grains of the dielectric layer calculated based on observation using a scanning transmission electron microscope is set as the first average particle diameter. The median particle diameter of the crystal grains in a case where the crystal orientation is determined by electron backscatter diffraction and crystal grains having an offset angle of the crystal orientation of two adjacent particles of 5 degrees or less are regarded as one crystal grain with reference to an arbitrary direction is set as the second average particle diameter.

[0218] In Table 3, in addition to the first average particle diameter and the second average particle diameter, the value of the relative dielectric constant / first average particle diameter is also shown. The value of the relative dielectric constant / first average particle diameter shows the relative dielectric constant per unit particle diameter, and the larger the value, the better the electrical characteristics. In the samples in which the second average particle diameter / first average particle diameter is 1 or more, the value of the relative dielectric constant / first average particle diameter is 13 or more. That is, these samples show good electrical characteristics.

[0219] Further, the measurement shown in Table 3 was performed in the WT cross section at the middle position in the length direction T of the laminated ceramic capacitor. The laminated ceramic capacitor was polished so that the WT cross section was exposed. The polishing was performed by continuously grinding a surface parallel to the width direction W and the height direction T.

[0220] Measurement based on electron backscatter diffraction for obtaining a crystal orientation map by transmission EBSD was performed using a thin sample. The measurement was performed after processing the WT cross section at the middle position in the length direction T of the laminated ceramic capacitor described above into a thin sample. Specifically, the surface opposite to the measurement surface was polished so that the thickness of the sample became 100 nm, and then the WT cross section was measured.

[0221] Regarding the particle diameter, the central portion of the WT cross section was set as the evaluation object. The size of the evaluation object was 2 μm square. In electron backscatter diffraction, in a region where a plurality of crystal grains are overlapped in a direction perpendicular to the measurement surface and the like, an accurate value is sometimes not obtained. When such a region where an accurate value is not obtained is included at a high ratio within the range of the evaluation object, accurate evaluation becomes difficult. Therefore, the size of the evaluation object was set to 2 μm square.

[0222] (Measurement method)

[0223] The length and the thickness and the like of each portion can be measured as follows. The laminated ceramic capacitor 1 was polished to the central position in the width direction. Then, the cross section exposed by the polishing was observed using an optical microscope or the like. The measurement can be performed from the observed cross section. (1)

[0225] A laminated ceramic capacitor including:

[0226] A laminate including a plurality of dielectric layers and a plurality of internal electrode layers, has first and second main surfaces opposite in a height direction, first and second side surfaces opposite in a width direction orthogonal to the height direction, and first and second end surfaces opposite in a length direction orthogonal to the height and width directions; and

[0227] An external electrode layer is provided to the laminate and connected to a portion of the internal electrode layers,

[0228] wherein

[0229] The value of the second average grain diameter / the first average grain diameter is 1.0 or greater when the median grain diameter of the dielectric layer grains calculated by observation using a scanning transmission electron microscope is set as the first average grain diameter, and the median grain diameter of the grains in a case where the crystal orientation of the dielectric layer grains is determined by electron backscatter diffraction and grains in which the misorientation angle of the crystal orientation of two adjacent grains is within 5 degrees based on an arbitrary direction are regarded as one grain is set as the second average grain diameter.

[0230] The embodiments of the present application have been described above, but the present application is not limited to the above-described embodiments, and various modifications and alterations can be made.

[0231] Explanation of Reference Numerals

[0232] 1 Laminated ceramic capacitor

[0233] 2 Laminated body

[0234] 3 Outer dielectric layer

[0235] 4 Inner dielectric layer

[0236] 5a First dielectric layer

[0237] 5b Second dielectric layer

[0238] 6a First internal electrode layer

[0239] 6b Second internal electrode layer

[0240] 20a First external electrode

[0241] 20b Second external electrode

[0242] C Grain

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and an external electrode layer provided on the laminate and connected to a portion of the internal electrode layer; in, When the crystal orientation of the crystal grains of the dielectric layer is measured by electron backscatter diffraction, Within the 2μm square observation range, There are two or more groups of crystal grains in which the difference in crystal orientation between two adjacent crystal grains is within 5 degrees based on an arbitrary direction.

2. The multilayer ceramic capacitor according to claim 1, wherein There are 20 or more groups of crystal grains in which the difference in crystal orientation between two adjacent crystal grains is within 5 degrees based on any direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein There is at least one group of three crystal grains including one crystal grain and two crystal grains adjacent to the crystal grain and having a crystal orientation offset angle within 5 degrees from the crystal grain.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein 50 or more and 250 or less crystal grains are observed in the observation range.

5. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and an external electrode layer provided on the laminate and connected to a portion of the internal electrode layer; in, When the crystal orientation of the crystal grains of the dielectric layer is measured by electron backscatter diffraction, The crystal grains that are in contact with other crystal grains whose crystal orientation differs from that of other crystal grains by within 5 degrees based on any direction account for more than 2% of all the crystal grains.

6. The multilayer ceramic capacitor according to claim 5, wherein The crystal grains that are in contact with other crystal grains whose crystal orientation differs from that of other crystal grains by within 5 degrees based on any direction account for more than 20% of all crystal grains.

7. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and an external electrode layer provided on the laminate and connected to a portion of the internal electrode layer; in, When the median particle size of the crystal grains of the dielectric layer obtained by observation using a scanning transmission electron microscope is set as the first average particle size, and the crystal orientation of the crystal grains of the dielectric layer is measured by electron backscatter diffraction and the crystal orientation of two adjacent crystal grains whose deviation angles in any direction are within 5 degrees are regarded as one crystal grain is measured as the second average particle size, The value of the second average particle size / the first average particle size is 1.0 or more.

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