Power switch device transient overcurrent capability test circuit

Abstract

The invention relates to a transient overcurrent capability test circuit for a power switch device, which comprises a driving control circuit which comprises a CPU (central processing unit), a digital isolator and a driver, the grid electrode of the tested power switch device is connected with the first output end of the driver; a first inductor, first and second power switch devices, a relay, a power supply and a capacitor. The power supply supplies power to the digital isolator and the driver; four paths of control signals are externally controlled and input by giving instructions to the CPU, the four paths of control signals are input to a control input port of the high-voltage driver after being subjected to digital isolation, and the driver outputs power switch device driving signals after receiving the control signals, so that the power switch device is turned on and off, and transient overcurrent capability evaluation of the tested power switch device is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of test circuit, and particularly relates to a transient overcurrent capability test circuit of power switch device. BACKGROUND

[0002] The traditional double-pulse test technology is based on a half-bridge circuit, and the switching characteristics of the switch tube under the specified voltage and current, such as the on-time, the off-time and the switching loss, can be obtained by sending a double-pulse signal to the power switch device. However, the traditional method cannot evaluate the overcurrent capability, and only the parameters in the manual of the components are referred to in the circuit design, so the overcurrent capability of the power switch device cannot be effectively evaluated. In addition, due to the complex working environment of the hardware circuit, the power switch device frequently fails due to overcurrent problems.

[0003] Therefore, it is necessary to improve one or more problems in the related technical solutions.

[0004] It should be noted that this section aims to provide background or context to the technical solutions of the present application stated in the claims. The description herein is not admitted to be prior art merely because it is included in this section. SUMMARY

[0005] The purpose of the embodiment of the present application is to provide a transient overcurrent capability test circuit of power switch device, and to at least overcome one or more problems caused by the limitations and defects of the related art.

[0006] The embodiment of the present application provides a transient overcurrent capability test circuit of power switch device, comprising: a drive control circuit, the drive control circuit comprising a CPU, a digital isolator and a driver, the input end of the digital isolator being connected with the output end of the CPU, and the input end of the driver being connected with the output end of the digital isolator; a measured power switch device, the gate of the measured power switch device being connected with the first output end of the driver; a first inductor, the first end of the first inductor being connected with the drain of the measured power switch device; a first power switch device, the gate of the first power switch device being connected with the second output end of the driver, and the source of the first power switch device being connected with the first end of the first inductor; a second power switch device, the gate of the second power switch device being connected with the third output end of the driver, and the drain of the second power switch device being connected with the first end of the first inductor; a relay, first ends of the relay are connected with a source electrode of the measured power switch device, a drain electrode of the first power switch device and a source electrode of the second power switch device respectively; a power supply, a negative electrode of the power supply is connected with a second end of the relay, and a positive electrode of the power supply is connected with a second end of the first inductor; a capacitor, a first end of the capacitor is connected with the positive electrode of the power supply, and a second end of the capacitor is connected with the source electrode of the measured power switch device, the drain electrode of the first power switch device and the source electrode of the second power switch device respectively.

[0007] In the application, the gate electrode of the measured power switch device is connected with the first output end of the driver through the first resistor.

[0008] In the application, the gate electrode of the first power switch device is connected with the second output end of the driver through the second resistor.

[0009] In the application, the gate electrode of the second power switch device is connected with the third output end of the driver through the third resistor.

[0010] In the application, the test circuit further comprises: a third power switch device, a gate electrode of the third power switch device is connected with a fourth output end of the driver, a drain electrode of the third power switch device is connected with the second end of the first inductor, the first end of the capacitor and the positive electrode of the power supply respectively, and a source electrode of the third power switch device is connected with the drain electrode of the measured power switch device, the source electrode of the first power switch device and the drain electrode of the second power switch device respectively; a second inductor, a first end of the second inductor is connected with the drain electrode of the measured power switch device, the first end of the first inductor, the source electrode of the first power switch device and the drain electrode of the second power switch device respectively, and a second end of the second inductor is connected with the drain electrode of the third power switch device, the second end of the first inductor, the first end of the capacitor and the positive electrode of the power supply respectively.

[0011] In the application, the gate electrode of the third power switch device is connected with the fourth output end of the driver through the fourth resistor.

[0012] In the application, the third power switch device is an upper bridge arm power switch device, the measured power switch device, the first power switch device and the second power switch device are all lower bridge arm power switch devices, and the third power switch device and the measured power switch device are the same bridge arm power switch device.

[0013] The technical scheme provided by the application can have the following beneficial effects: The power switch device transient overcurrent capability test circuit of the application, the power supply is for digital isolator and driver power supply; external through the CPU instruction, control input four control signals, four control signals are input to the control input port of high voltage driver after digital isolation, the driver receives the control signal and outputs the power switch device drive signal, makes the power switch device open and shut, realizes the transient overcurrent capability evaluation of the measured power switch device; the control signal and the drive signal are electrically isolated through the digital isolator, avoid the interference of the power circuit to the control circuit, so as to avoid the phenomenon that the control circuit loses the control precision, protect the control circuit from being burned by the abnormally large current in the high voltage drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application. It is to be expressly understood, however, that the drawings are for illustration only and may not be to scale.

[0015] Figure 1 The circuit principle block diagram of the power switch device transient overcurrent capability test circuit in the exemplary embodiment of the application is shown; Figure 2 The simulation principle block diagram of the power switch device transient overcurrent capability test circuit in the exemplary embodiment of the application is shown; Figure 3 The simulation waveform diagram of the power switch device transient overcurrent capability test circuit in the exemplary embodiment of the application is shown. DETAILED DESCRIPTION

[0016] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein; rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects to those skilled in the art. Features, structures or characteristics described in conjunction with the described examples can be combined in any suitable manner in one or more implementations.

[0017] In addition, the drawings are to be regarded as being schematic only and therefore are not intended to limit the application in any way. The same or similar components are denoted by the same reference numerals throughout the drawings, and thus repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, and thus do not necessarily correspond to physical or logical independent entities.

[0018] A power switch device transient overcurrent capability test circuit is provided in the example implementation, please refer to Figure 1The test circuit comprises a drive control circuit 10, a power switch device Q1 to be tested, a first inductor L1, a first power switch device Q2, a second power switch device Q3, a relay K, a power supply DC and a capacitor C.

[0019] Specifically, the drive control circuit 10 comprises a CPU 11, a digital isolator 12 and a driver 13, wherein an input end of the digital isolator 12 is connected with an output end of the CPU 11, and an input end of the driver 13 is connected with an output end of the digital isolator 12.

[0020] A gate of the power switch device Q1 to be tested is connected with a first output end of the driver 13. A first end of the first inductor L1 is connected with a drain of the power switch device Q1 to be tested. A gate of the first power switch device Q2 is connected with a second output end of the driver 13, and a source of the first power switch device Q2 is connected with the first end of the first inductor L1. A gate of the second power switch device Q3 is connected with a third output end of the driver 13, and a source of the second power switch device Q3 is connected with the first end of the first inductor L1.

[0021] A first end of the relay K is connected with a source of the power switch device Q1 to be tested, a drain of the first power switch device Q2 and a source of the second power switch device Q3 respectively. A negative pole of the power supply DC is connected with a second end of the relay K, and a positive pole of the power supply DC is connected with a second end of the first inductor L1. A first end of the capacitor C is connected with the positive pole of the power supply DC, and a second end of the capacitor C is connected with the source of the power switch device Q1 to be tested, the drain of the first power switch device Q2 and the source of the second power switch device Q3 respectively.

[0022] In the embodiment, the power supply DC supplies power for the digital isolator 12 and the driver 13. The CPU 11 is externally given instructions to control input of four control signals A1, A2, A3 and A4, which are input to control input ports IN1, IN2, IN3 and IN4 of the high-voltage driver 13 after passing through the digital isolator 12. After receiving the control signals, the driver 13 outputs power switch device driving signals to make the power switch device open and shut, thereby realizing transient overcurrent capability evaluation of the power switch device Q1 to be tested. The control signals and the driving signals are electrically isolated by the digital isolator 12, which avoids the phenomenon that the power circuit interferes with the control circuit and causes the control circuit to lose control precision, thereby protecting the control circuit from being burned by an abnormally large current in the high-voltage driving circuit.

[0023] On the basis of the above embodiment, the gate of the measured power switch device Q1, the gate of the first power switch device Q2 and the gate of the second power switch device Q3 are connected to the first output end, the second output end and the third output end of the driver 13 through resistors R5, R4 and R7 respectively. The power switch device is connected to the resistor and the driver 13 to realize overcurrent protection and current closed-loop control.

[0024] In addition, the test circuit further comprises a third power switch device Q4 and a second inductor L2.

[0025] The gate of the third power switch device Q4 is connected to the fourth output end of the driver 13 through a resistor R3, and the drain of the third power switch device Q4 is connected to the second end of the first inductor L1, the first end of the capacitor C and the positive pole of the power supply DC respectively, and the source of the third power switch device Q4 is connected to the drain of the measured power switch device Q1, the source of the first power switch device Q2 and the drain of the second power switch device Q3 respectively.

[0026] The first end of the second inductor L2 is connected to the drain of the measured power switch device Q1, the first end of the first inductor L1, the source of the first power switch device Q2 and the drain of the second power switch device Q3 respectively, and the second end of the second inductor L2 is connected to the drain of the third power switch device Q4, the second end of the first inductor L1, the first end of the capacitor C and the positive pole of the power supply DC respectively.

[0027] In the embodiment, the third power switch device Q4 and the second inductor L2 are used to test the switching characteristics of the measured power switch device. When testing, the CPU sends a pulse signal to the gate of the measured switch tube through the isolation and driving chip, so that the measured switch tube is turned on or turned off at a specified time, so as to obtain the dynamic characteristics of the switch device under a specified bus voltage. The characteristics of the switch device are implemented by using the technical solutions in the prior art, and the present application does not make specific limitations thereto.

[0028] The test process of the test circuit of the present application is as follows: Generally, the CPU 11 outputs 4-way power switch device driving signals, which are converted in level by the digital isolator 12 and then used to drive the load by the high-voltage driver 13, so as to realize the test of the power switch device.

[0029] Specifically, the control signals A1, A2, A3 and A4 are input signals of the test circuit, which are input to the input ports IN1, IN2, IN3 and IN4 of the high-voltage driver 13 via the digital isolator 12. The input pins of the high-voltage driver 13 control one upper bridge arm power switch device (Q4) and three lower bridge arm power switch devices (Q1, Q2 and Q3) through the output of the driver 13, wherein the lower bridge arm power switch device in the same bridge arm as the upper bridge arm is the measured power switch device Q1, and the other two lower bridge arm devices (Q2 and Q3) cooperate with Q4 to control the on-off of the circuit to realize the overcurrent capability test of the measured power switch device Q1.

[0030] The present application is described by evaluating the 19.7A current of the measured power switch device Q1 and maintaining 10ms. The test circuit CPU 11 outputs a pulse switching signal to make the upper tube Q4 maintain a closed state through the digital isolator 12 and the high-voltage driver 13, Q2 is opened (connected) to charge the first inductor L1 within 0-20ms, and the bus voltage VBUS is disconnected through the relay K at 20ms-30ms, while Q2 is turned off and Q1 is turned on, so that the 19.7A current on the first inductor L1 flows through the measured power switch device Q1 and maintains the open state for 10ms, thereby achieving the test purpose. After reaching the test requirement, the measured power switch device Q1 is turned off, Q3 is turned on, and the remaining energy in the circuit is discharged to ensure the safety of the circuit.

[0031] Figure 2 The simulation principle block diagram of the test circuit of the present application is shown in Figure 3 The simulation waveform diagram of the test circuit of the present application is shown in Figure 3 It can be seen that IDS is the current waveform of the measured device, and it can be seen that the measured power switch device stably maintains the 19.7A current for 10ms, which proves the feasibility of the test circuit of the present application.

[0032] During the test, by changing the load inductor L2 and the filter capacitor C, any size of current can flow through the measured power switch device Q1 within a certain time, thereby realizing the transient overcurrent capability test of different types of power switch devices.

[0033] The present application also has the technical features of high precision, high reliability and low cost, and better solves the transient current test requirement of the power switch device.

[0034] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative but not limiting. Those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims, and these all belong to the protection of the present application.

Claims

1. The transient overcurrent capability test circuit of the power switching device is characterized by: include: A drive control circuit, comprising: a CPU, a digital isolator, and a driver, wherein the input end of the digital isolator is connected to the output end of the CPU, and the input end of the driver is connected to the output end of the digital isolator; A power switching device under test, wherein the gate of the power switching device under test is connected to the first output terminal of the driver; a first inductor, wherein a first end of the first inductor is connected to the drain of the power switching device under test; a first power switch device, wherein a gate of the first power switch device is connected to the second output terminal of the driver, and a source of the first power switch device is connected to the first terminal of the first inductor; a second power switch device, wherein a gate of the second power switch device is connected to the third output terminal of the driver, and a drain of the second power switch device is connected to the first end of the first inductor; a relay, wherein a first end of the relay is respectively connected to the source of the power switching device under test, the drain of the first power switching device, and the source of the second power switching device; a power supply, wherein a negative electrode of the power supply is connected to the second end of the relay, and a positive electrode of the power supply is connected to the second end of the first inductor; A capacitor, wherein a first end of the capacitor is connected to the positive electrode of the power supply, and a second end of the capacitor is respectively connected to the source of the power switching device under test, the drain of the first power switching device, and the source of the second power switching device.

2. The power switch device transient overcurrent capability test circuit according to claim 1, characterized in that: The gate of the power switch device under test is connected to the first output terminal of the driver through a first resistor.

3. The power switch device transient overcurrent capability test circuit according to claim 1, characterized in that: The gate of the first power switch device is connected to the second output terminal of the driver through a second resistor.

4. The power switch device transient overcurrent capability test circuit according to claim 1, characterized in that: The gate of the second power switch device is connected to the third output terminal of the driver through a third resistor.

5. The power switch device transient overcurrent capability test circuit according to claim 1, characterized in that: The test circuit further includes: a third power switching device, wherein the gate of the third power switching device is connected to the fourth output terminal of the driver, the drain of the third power switching device is respectively connected to the second end of the first inductor, the first end of the capacitor, and the positive electrode of the power supply, and the source of the third power switching device is respectively connected to the drain of the power switching device under test, the source of the first power switching device, and the drain of the second power switching device; a second inductor, wherein a first end of the second inductor is respectively connected to the drain of the power switching device under test, the first end of the first inductor, the source of the first power switching device, and the drain of the second power switching device; and a second end of the second inductor is respectively connected to the drain of the third power switching device, the second end of the first inductor, the first end of the capacitor, and the positive electrode of the power supply.

6. The power switch device transient overcurrent capability test circuit according to claim 5, characterized in that: The gate of the third power switch device is connected to the fourth output terminal of the driver through a fourth resistor.

7. The power switch device transient overcurrent capability test circuit according to claim 6, characterized in that: The third power switch device is an upper bridge arm power switch device, the measured power switch device, the first power switch device and the second power switch device are all lower bridge arm power switch devices, and the third power switch device and the measured power switch device are the same bridge arm power switch device.

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