Method for implementing photolithography technology with large exposure field and chip-level chip interconnection method

Abstract

The application discloses a large-exposure-field photolithography technology implementation method, a chip-level chip interconnection method and a photolithography device. The large-exposure-field photolithography technology implementation method is applied to the photolithography device, the photolithography device comprises a projection system with a reduction ratio of 0.1-2.5, and the method comprises the following steps: loading a patterned substrate to be exposed to a stage, performing alignment through alignment marks on the substrate, and offsetting by a set offset distance; performing first exposure, transferring a preset pattern of a mask to a first exposure area of the substrate through the projection system; laterally stepping the substrate or the mask by M times of the lateral size of an original pattern unit or vertically stepping the substrate or the mask by N times of the vertical size of the original pattern unit, performing second exposure, and transferring the preset pattern to a second exposure area of the substrate through the projection system; and continuously performing lateral stepping or vertical stepping and second exposure until exposure of a target area on the substrate is completed. The scheme can form a large-size exposure field and realize high-density interconnection of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of lithography technology, specifically to a method for implementing large exposure field lithography, a chip-level chip interconnection method, and lithography equipment. Background Technology

[0002] In modern semiconductor manufacturing, photolithography is a crucial step in realizing high-density integrated circuits. The photolithography process precisely transfers a pattern from a photomask onto a photoresist surface on a silicon wafer to form the desired circuit structure. With the continuous increase in the integration density of integrated circuits, the requirements for the minimum critical dimension (CD) are becoming increasingly stringent. In the pattern exposure of a photolithography machine, the theoretical limit of the minimum critical dimension can be given by Rayleigh's rule for resolution, as shown in equation (1):

[0003] Formula (1)

[0004] in, It refers to the wavelength of the light source used in the lithography machine. It is the numerical aperture of the projection system in a lithography machine used for exposure. It is an adjustment factor dependent on the photolithography process, also known as the Rayleigh constant. This is the minimum size of the graphic. From formula (1), we can see that there are three main ways to reduce the minimum size of the graphic: shortening the exposure wavelength... Increase numerical aperture or reduce Reducing the minimum pattern size through the three methods mentioned above is too difficult and costly. Furthermore, as device dimensions continue to shrink, leakage current problems caused by quantum tunneling become increasingly severe, limiting the feasibility of further reducing the minimum pattern size. Therefore, simply relying on reducing the critical dimensions of the device to increase the number of transistors is no longer feasible.

[0005] To accommodate more transistors, manufacturing larger chips has become extremely important. However, the maximum exposure field size of traditional lithography machines is limited to approximately 26mm × 33mm, which cannot meet the needs of manufacturing larger chips. While large exposure fields have been achieved in some LCD panel applications, the resulting line sizes are too wide, making it difficult to meet the high-density integration requirements of integrated circuits. Therefore, achieving a large exposure field has become a pressing technical problem in lithography. Summary of the Invention

[0006] This application provides a method for implementing large-exposure-field photolithography, a chip-level chip interconnection method, and photolithography equipment, which can form a large-size exposure field, realize high-density interconnection of integrated circuits, and provide photolithography technology support for high-density interconnection and integration of multiple large chips. The specific solution is as follows:

[0007] In a first aspect, embodiments of this application provide a method for implementing large exposure field photolithography, applied to a photolithography apparatus, the photolithography apparatus including a projection system with a reduction ratio of 0.1 to 2.5 times, the method comprising:

[0008] The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned using alignment marks on the substrate, and offset by a set offset distance.

[0009] Perform the first exposure by transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0010] The substrate is stepped M times the lateral dimension of the original pattern unit in the lateral direction, or N times the longitudinal dimension of the original pattern unit in the longitudinal direction, and aligned using alignment marks on the substrate, with a set offset distance.

[0011] A second exposure is performed, in which a preset pattern on the mask is transferred to a second exposure area on the substrate by the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0012] The lateral stepping or longitudinal stepping and the second exposure are performed continuously until the exposure of all target areas of the substrate is completed;

[0013] Wherein, at least one of M and N is an integer greater than or equal to 2.

[0014] Optionally, it further includes: when the alignment mark on the substrate is an alignment mark set for the projection system at a reduction ratio of 0.1 to 2.5, the set offset distance is 0.

[0015] Optionally, the reduction ratio of the projection system includes any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2, and 2.5 times.

[0016] Optionally, the size of the first exposure area is M×N times 26mm×33mm.

[0017] Optionally, the original graphic unit corresponds to a graphic area formed by exposure of a projection system with a reduction ratio of 4 to 10 times.

[0018] Optionally, the substrate is characterized in that it is a silicon substrate, a germanium substrate, a compound semiconductor substrate, or a ceramic substrate, a glass substrate, a quartz substrate, a silicon substrate, or a metal substrate.

[0019] Optionally, the substrate may be loaded with one or more of a silicon substrate, a germanium substrate, and a compound semiconductor substrate.

[0020] Optionally, the graphics in the original graphics unit are one or more of the following: integrated circuit graphics, optical path graphics, microfluidic pathways, metal wiring, vias, and sensor graphics.

[0021] Optionally, the original graphics unit is an integrated circuit graphics unit.

[0022] Optionally, the photolithography equipment includes a light source, and the method further includes: if the light source is a mercury lamp or an excimer laser, an immersion liquid is filled between the projection system and the substrate on the stage.

[0023] Optionally, there may be one or two stages, each stage being loaded with a substrate to be exposed.

[0024] Optionally, when there are two stages, the method further includes:

[0025] The two stages are controlled to move alternately under the projection system to complete the exposure.

[0026] Optionally, the two stages include a first stage and a second stage, and the method further includes:

[0027] During the alignment and exposure process performed on the first stage, the second stage is controlled to perform silicon wafer loading and unloading and pre-alignment steps.

[0028] Optionally, the photolithography apparatus includes a light source, and the method further includes:

[0029] If the light source is an EUV light source, the projection system is a reflective projection system.

[0030] Secondly, embodiments of this application provide a method for implementing large exposure field photolithography, applied to a photolithography apparatus, wherein the photolithography apparatus includes a projection system with a reduction ratio of 0.1 to 2.5 times, and the method includes:

[0031] The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned using alignment marks on the substrate, and offset by a set offset distance.

[0032] Perform the first exposure by transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0033] The substrate is stepped laterally by the sum of the lateral dimensions of M original pattern units, or longitudinally by the sum of the longitudinal dimensions of N original pattern units, and aligned using alignment marks on the substrate, with a set offset distance.

[0034] A second exposure is performed, in which a preset pattern on the mask is transferred to a second exposure area on the substrate by the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0035] The lateral stepping or longitudinal stepping and the second exposure are performed continuously until the exposure of all target areas of the substrate is completed;

[0036] Among the M×N original graphic units, at least some of the original graphic units have different sizes; at least M and N are integers greater than or equal to 2.

[0037] Thirdly, embodiments of this application provide a chip-level chip interconnection method, including:

[0038] A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having an in-chip interconnect and no interconnect between the semiconductor chips;

[0039] The photolithography steps for interconnecting the at least two semiconductor chips are achieved by means of a large exposure field photolithography technique as described in any of the first aspects.

[0040] Fourthly, embodiments of this application provide a photolithography apparatus, including a projection system with a reduction ratio of 0.1 to 2.5 times.

[0041] Compared with the prior art, this application has the following advantages:

[0042] The large exposure field photolithography method provided in the first embodiment of this application aligns the substrate with a preset pattern on a photomask after alignment by alignment marks on the substrate and offset by a set offset distance. Then, the preset pattern on the photomask is transferred to the first exposure area on the substrate by a projection system. Since the projection system has a reduction ratio of 0.1 to 2.5 times, the first exposure area formed will cover at least M×N original pattern units corresponding to the pattern areas, where at least M and N are integers greater than or equal to 2. Next, one of the substrates or masks is stepped horizontally by M times the lateral dimension of the original pattern unit, or vertically by N times the longitudinal dimension of the original pattern unit, and a second exposure is performed. The preset pattern on the mask is transferred to the second exposure area on the substrate through the projection system. In this way, the second exposure area will cover at least M×N pattern areas corresponding to the original pattern units. The above steps of stepping horizontally by M times the image size corresponding to the original pattern unit or stepping vertically by N times the image size corresponding to the original pattern unit and the second exposure are performed continuously until the exposure of all target areas on the substrate is completed.

[0043] As can be seen, the large exposure field lithography method provided in this application achieves this by using a projection system with a reduction ratio of 0.1 to 2.5 times to form a large exposure field in a single exposure. It compensates for alignment deviations caused by inconsistent projection magnifications through a biased offset distance. Furthermore, it overcomes image overlap problems when covering multiple patterns at the original pattern unit step distance by stepping M times the lateral dimension of the original pattern unit and N times the vertical dimension of the original pattern unit. This effectively achieves pattern alignment, coverage, and stepping of M×N original pattern units. Continuous stepping alignment, biasing, and exposure completes the exposure of the target area on the substrate, thereby realizing high-density interconnection of integrated circuits and providing lithography technology support for high-density interconnection integration of multiple large chips. Attached Figure Description

[0044] Figure 1 This is a structural diagram of a lithography apparatus used in the large exposure field lithography method provided in the embodiments of this application.

[0045] Figure 2 This is a schematic diagram of an example of an integrated circuit mounted on a substrate in a large exposure field lithography implementation method provided in this application embodiment.

[0046] Figure 3 This is a cross-sectional schematic diagram of a logic device in an integrated circuit.

[0047] Figure 4 This is a structural diagram of the lithography equipment based on the EUV light source provided in the embodiments of this application.

[0048] Figure 5 This is a flowchart of a large exposure field lithography technique implementation method provided in this application.

[0049] Figure 6 This is a schematic diagram of an example of the large exposure field lithography method provided in this application, which covers the image area corresponding to M×N original graphic units.

[0050] Figure 7 This is a schematic diagram of an example of the second exposure region in the large exposure field lithography method provided in the embodiments of this application.

[0051] Figure 8 This is a schematic diagram of an example of an M×N chip group including multiple original patterned units of different sizes in the large exposure field photolithography method provided in the embodiments of this application.

[0052] Figure 9 This is a schematic diagram of an example of a composite original pattern unit in the large exposure field photolithography method provided in the embodiments of this application. Detailed Implementation

[0053] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0054] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0055] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0056] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0057] Based on the reasons mentioned in the background technology, in order to form a large-size exposure field, realize high-density interconnection of integrated circuits, and provide photolithography technology support for high-density interconnection and integration of multiple large chips, this application provides a photolithography technology implementation method with a large exposure field, which is applied to photolithography equipment.

[0058] First, the application scenarios of the large exposure field lithography method provided in the embodiments of this application will be introduced:

[0059] The method provided in this application can be applied to top-layer or second-layer lithography processes. Top-layer or second-layer lithography processes are back-end steps in integrated circuit manufacturing, mainly used to form the topmost metal interconnects and contact holes. Since top-layer lithography does not involve fine transistor structures, its minimum critical size requirement is relatively low. The large exposure field lithography technique provided in this application can be used to achieve this, forming a large exposure field, reducing the number of exposures, improving lithography process efficiency, and achieving high-density interconnection of multiple large chips. It should be noted that although the line size of the large exposure field lithography technique provided in this application (usually at the 0.1 micrometer level (e.g., 0.1 micrometer to tens of micrometers)) is coarser than the line size of traditional lithography machines (e.g., EUV lithography machines, usually at the nanometer level (e.g., several nanometers to tens of nanometers)), it is several orders of magnitude finer than the line size of interconnection between multiple large chips achieved through traditional packaging (usually at the 0.1 millimeter level or larger).

[0060] like Figure 1 The diagram shown is a structural diagram of an example of the photolithography equipment used in the large exposure field photolithography method provided in this application embodiment. The photolithography equipment includes:

[0061] Light source 100 is used to provide the exposure beam required for photolithography. The type of light source 100 may include, but is not limited to, a mercury lamp, an excimer laser, or an extreme ultraviolet (EUV) light source. Mercury lamps can emit light with multiple discrete wavelengths, including g-lines (436 nm), i-lines (365 nm), etc., wavelengths suitable for photolithography processes with different resolution requirements. Excimer lasers can generate shorter wavelengths of ultraviolet light, such as KrF (248 nm) and ArF (193 nm), short wavelengths which help improve photolithography resolution and are suitable for fine patterning requirements. The wavelength of the EUV light source is 13.5 nm, much shorter than that of traditional DUV light sources. This allows for photolithography at extremely high resolution, suitable for state-of-the-art semiconductor manufacturing processes. Methods for generating EUV light sources include, but are limited to, converting materials into a plasma state having at least one element with one or more emission lines in the EUV range (e.g., xenon, lithium, or tin).

[0062] Mask 200 is used to provide the preset pattern required for exposure;

[0063] A projection system 300 with a reduction ratio of 0.1 to 2.5 times is used to transfer a preset pattern on a mask 200 onto a substrate 500 to be exposed. Optionally, the reduction ratio of the projection system 300 may include at least any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2, and 2.5 times. Specifically, the required reduction ratio can be selected according to the minimum critical size requirements and the size requirements of the exposure field to be formed (i.e., the first exposure area and the second exposure area). This application does not impose specific restrictions on this.

[0064] The stage 400 is used to mount the substrate 500 and to perform stepping on the substrate 500.

[0065] The substrate 500 can be a silicon wafer with integrated circuit patterns, a carrier board with integrated circuits, or a carrier board without integrated circuits. The carrier board includes, but is not limited to, one of ceramic carrier boards, glass carrier boards, quartz carrier boards, silicon carrier boards, and metal carrier boards.

[0066] The substrate 500 can be a composite substrate composed of a substrate containing integrated circuits (including silicon substrates, germanium substrates, compound semiconductors, etc.) and a carrier plate (including ceramic carrier plate, glass carrier plate, quartz carrier plate, silicon carrier plate, or metal carrier plate, etc.) for supporting the substrate containing integrated circuits. Using the photolithography method provided in this application embodiment, KGD (know-good die) chips can be precisely bonded to the carrier plate, and then the composite substrate can be further interconnected at high density through this invention. Here, KGD (know-good die) chips refer to independent chips that have been verified to be functionally normal in wafer-level testing, possessing good functionality and reliability before being integrated into more complex systems.

[0067] The substrate 500 may also be loaded with one or more of the following: a silicon substrate, a germanium substrate, a compound semiconductor substrate, and a carrier plate. The longitudinal dimensions of individual original patterned units existing on the silicon substrate, germanium substrate, and compound semiconductor substrate may be the same or different, and the lateral dimensions of individual original patterned units existing on the silicon substrate, germanium substrate, and compound semiconductor substrate may be the same or different.

[0068] In this way, mounting multiple small silicon wafers or small carrier boards on a large carrier board can improve efficiency. Furthermore, mounting small silicon wafers or small carrier boards of different models on a large carrier board can achieve high-density interconnection of different models of small silicon wafers or small carrier boards in the form of large-size chips.

[0069] When the substrate 500 is a structure in which multiple silicon substrates, multiple germanium substrates, multiple compound semiconductor substrates, or multiple carrier plates are mounted on the substrate 502, the silicon substrates may be the same or different, and / or the germanium substrates may be the same or different, and / or the compound semiconductors may be the same or different, and / or the carrier plates may be the same or different. The silicon substrates, germanium substrates, compound semiconductor substrates, and carrier plates can be placed according to actual needs, and this application does not impose any restrictions on this.

[0070] After one or more exposures, the substrate without integrated circuits will form one or more layers of metal wiring and / or optical wiring. These metal wiring and / or optical wiring will be used to connect integrated circuits, sensors, or optoelectronic devices in subsequent stages. Then, the large exposure field photolithography technique provided in this application embodiment can be used for exposure photolithography.

[0071] The pattern in the original pattern unit is one or more of the following: integrated circuit pattern, optical path pattern, microfluidic path, metal wiring, via, and sensor pattern. The original pattern unit can be a single integrated circuit pattern unit.

[0072] The carrier board may have one or more silicon wafers and / or one or more carrier boards. In this way, mounting multiple small silicon wafers or small carrier boards on a large carrier board can improve efficiency. Furthermore, mounting small silicon wafers or small carrier boards of different models on a large carrier board can achieve high-density interconnection of small silicon wafers or small carrier boards of different models in a large-size chip mode.

[0073] The size of the carrier plate can be from 40 mm to 4000 mm. For example, the size of the carrier plate can be one of 40 mm, 80 mm, 100 mm, 150 mm, 300 mm, 600 mm, 1200 mm, 2400 mm, 3000 mm, 3600 mm or 4000 mm.

[0074] The carrier can be circular or square. Compared with square carriers, circular carriers have a higher degree of compatibility with silicon wafers; compared with circular carriers, square carriers have a higher utilization rate.

[0075] The substrate 500 also includes a primary alignment device 510, which is used to perform preliminary alignment of the substrate. It should be noted that when the substrate 500 does not have a primary alignment device 510, alignment can also be performed by means of the shape of the carrier plate itself.

[0076] It should be noted that for thinned integrated circuits, the warpage is often too large, or the thinness makes them difficult to clamp. In such cases, such as... Figure 2 The diagram shown is a schematic of an example of an integrated circuit mounted on a carrier plate in the large exposure field photolithography technology implementation method provided in this application embodiment. The thinned integrated circuit 503 can be mounted on the carrier plate 502.

[0077] The integrated circuit pattern can be a single-layer integrated circuit pattern or a multi-layer integrated circuit pattern. As 3D integrated circuit technology matures, the large-exposure-field photolithography method provided in this application can also be applied to chips with stacked multi-layer integrated circuits. In other words, the method provided in this application can be effectively implemented even under complex structures formed after multi-layer circuit integration.

[0078] In the aforementioned multilayer integrated circuit pattern, the materials of the integrated circuit patterns in different layers can be the same or different. In this way, large-exposure-size silicon-based, silicon-based compound semiconductor, silicon-based carbon-based, and silicon-based germanium silicon semiconductors can be integrated together to obtain complex large chips.

[0079] like Figure 3The diagram shown is a cross-sectional schematic of a logic device in an integrated circuit. In the large-exposure-field photolithography method provided in this application, the integrated circuit on the substrate to be exposed can be an integrated circuit that has completed both front-end of line (FEOL) and back-end of line (BEOL) processes, and / or an integrated circuit that has partially completed both front-end of line (FEOL) and back-end of line (BEOL) processes. The specific process step to begin with can be selected according to actual needs to achieve the desired effect.

[0080] The type of integrated circuit may include, but is not limited to, at least one of integrated circuits integrating electrical functions, integrated circuits integrating optical-optoelectronic functions, and integrated circuits integrating sensor functions. In other words, the large exposure field photolithography technique provided in this application embodiment can be applied to integrated circuits with the aforementioned functions for further large exposure field integration. The type of integrated circuit can be selected according to actual needs, and this application does not specifically limit it.

[0081] exist Figure 1 In the photolithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200 and transfers the preset pattern on the mask 200 to the substrate 500 mounted on the stage 400 through a projection system 300. Then, photolithography is performed on the photoresist material to form an exposure field pattern.

[0082] It should be noted that if the light source 100 is an EUV light source, and the projection system 300 is a reflective projection system, such as... Figure 4 The diagram shown is a structural diagram of a lithography device based on an EUV light source provided in an embodiment of this application. Figure 4 In the lithography apparatus shown, the light source 100 forms an exposure beam through an illumination system. The exposure beam passes through the mask 200, and the preset pattern on the mask 200 is reflected onto the substrate 500 mounted on the stage 400 by a reflective projection system 300. Then, photolithography is performed on the photoresist material to form the exposure field pattern. This avoids the problem that extreme ultraviolet (EUV) light is easily absorbed by light-transmitting materials, preventing the exposure beam from reaching the substrate.

[0083] If the light source 100 is a mercury lamp or an excimer laser, the space between the projection system 300 and the substrate 500 is filled with an immersion liquid (such as deionized water). Compared to traditional photolithography where the exposure beam reaches the silicon wafer surface directly from the projection system, this solution increases the refractive index of the medium by filling with an immersion liquid, thereby increasing the numerical aperture (NA) of the optical system and reducing the minimum critical dimension.

[0084] The above is an introduction to the photolithography equipment provided in the embodiments of this application.

[0085] It should be noted that the large exposure field lithography method provided in this application is mainly used to solve the interconnection between multiple large chips approaching the exposure field limit of traditional integrated circuits (approximately 26mm*33mm). However, after creating a new pattern using this application, alignment and exposure can also be performed using the new alignment structure of the new pattern; or, by utilizing the large exposure field characteristics of this application, patterns can be directly fabricated on a substrate without integrated circuit patterns, thereby efficiently fabricating chips larger than those fabricated by traditional lithography methods, or fabricating substrates with higher density lines while maintaining a large area compared to traditional substrate fabrication methods. These are all inherent aspects of this application and will not be elaborated upon here.

[0086] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0087] like Figure 5 The diagram shown is a flowchart of the large exposure field photolithography method provided in the first embodiment of this application, including steps S101 to S105:

[0088] Step S101: The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned by the alignment marks on the substrate, and offset by a set offset distance.

[0089] This step is used to initially position the patterned substrate when it is initially loaded onto the stage.

[0090] The substrate has alignment marks (as shown in the attached image). Figure 6 The alignment mark 520 shown, taking a NIKON lithography machine as an example, can be a laser step alignment mark (LSA) and / or a field image alignment mark (FIA), or an alignment mark designed for the alignment system of the lithography equipment involved in this application. One or more alignment marks can be provided on the substrate, and the alignment marks can be provided in the dicing track to avoid affecting the functional areas of the chip.

[0091] Specifically, before photolithography begins, the wafer is transferred from the carrier to the stage of the photolithography equipment by a robotic arm or vacuum adsorption system. At this point, the wafer is roughly placed in a certain position on the stage. Then, a high-resolution camera or other sensors installed on the photolithography equipment scan the wafer, and preliminary alignment is performed using the primary alignment device 510 or the shape characteristics of the substrate itself. If necessary, precise alignment of the substrate is performed using one or more alignment marks of alignment markers 520, preparing the substrate for exposure. Afterwards, the stage moves the area of ​​the substrate to be exposed under the projection system, where precise alignment is performed using one or more alignment marks of alignment markers 520 on the substrate.

[0092] It is important to note that since the lithography machine used in this application is a large-field lithography machine, the exposure field size is different from that of the lithography machine used to create the original pattern. This generally results in alignment misalignment. Therefore, it is necessary to pre-set the offset distance and align and expose at the offset position during exposure. That is, after precise alignment using one or more alignment marks 520 on the substrate, the set offset distance is then applied. It should be noted that this offset distance can be set in the silicon wafer alignment offset, the mask alignment offset, or a portion can be set for both the silicon wafer and the mask; all of these methods can achieve the desired offset distance.

[0093] In one alternative embodiment, the alignment marks on the substrate are alignment marks set for the projection system with a reduction ratio of 0.1 to 2.5. That is, alignment marks are specifically set for compatibility with the lithography machine using the projection system with a reduction ratio of 0.1 to 2.5 when creating the original pattern, and the set alignment marks have taken offset values ​​into account. In this case, the offset distance of the lithography machine can be set to 0.

[0094] It should be noted that in the appendix Figure 6 In the diagram, alignment mark 520 is only shown at the original graphic unit 620. In actual applications, each original graphic unit (such as 610, 620, 630, and 640) has its own alignment mark. Figure 6 The markings shown are for illustrative purposes only. In actual use, it is usually sufficient to use the alignment mark 520 of only one of the original graphic units (such as 620) (if necessary, the alignment marks of multiple original graphic units can be used simultaneously to better ensure the alignment accuracy of large exposure areas).

[0095] Step S102: Perform the first exposure, and transfer the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0096] Wherein, at least one of M and N is an integer greater than or equal to 2. M and N can be the same or different, and this application does not impose any restrictions on the specific values ​​of M and N. For example, when interconnecting two chips horizontally, M can be chosen to be 2 and N to be 1; when interconnecting three chips horizontally, M can be chosen to be 3 and N to be 1; when interconnecting two chips vertically, M can be chosen to be 1 and N to be 2; when interconnecting four chips arranged in a 2×2 matrix (i.e., two chips distributed horizontally and two chips distributed vertically), M can be chosen to be 2 and N to be 2; when interconnecting 12 chips arranged in a 3×4 matrix (i.e., three chips distributed horizontally and four chips distributed vertically), M can be chosen to be 3 and N to be 4.

[0097] The original graphic unit here generally refers to a single large chip integrated circuit that is close to the maximum size of the exposure field of a traditional lithography machine (such as a DUV (deep ultraviolet) lithography machine) (approximately 26mm*33mm). This application mainly breaks through the limitation of the maximum size of the exposure field of traditional lithography machines and connects multiple large chips (such as a single chip size close to 26mm*33mm) with high-density lines.

[0098] This step is used to project and expose a preset pattern on the mask onto the area to be exposed on the substrate.

[0099] The projection system has a scaling factor of 0.1 to 2.5 times, which means that the projection system can magnify the preset pattern on the mask by 10 times to reduce it by 2.5 times and project it onto the substrate.

[0100] Optionally, the projection system has a scaling factor of 0.1. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 0.5 micrometers will be formed on the substrate.

[0101] Optionally, the projection system has a scaling factor of 0.125. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 0.4 micrometers will be formed on the substrate.

[0102] Optionally, the projection system has a scaling factor of 0.2. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 0.25 micrometers will be formed on the substrate.

[0103] Optionally, the projection system has a scaling factor of 0.25. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 0.2 micrometers will be formed on the substrate.

[0104] Optionally, the projection system has a scaling factor of 0.4. In this case, if the width of the line on the mask is 50 nanometers, the projection system will project a line of 0.125 micrometers onto the substrate.

[0105] Optionally, the projection system has a scaling factor of 0.5. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 0.1 micrometers will be formed on the substrate.

[0106] Optionally, the projection system can be scaled down by 1x. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a 50-nanometer line will be formed on the substrate.

[0107] Optionally, the projection system has a scaling factor of 1.25. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 40 nanometers will be formed on the substrate.

[0108] Optionally, the projection system can be scaled down by a factor of 2. In this case, if the width of the lines on the mask is 50 nanometers, then after projection through the projection system, lines of 25 nanometers will be formed on the substrate.

[0109] Optionally, the projection system has a scaling factor of 2.5. In this case, if the width of the line on the mask is 50 nanometers, then after projection through the projection system, a line of 20 nanometers will be formed on the substrate.

[0110] The projection system transfers a preset pattern from the photomask to a first exposure area on the substrate. A single exposure of this first exposure area can cover at least M (horizontal) × N (vertical) original pattern units corresponding to their respective pattern areas. These original pattern units refer to the single-exposure pattern areas formed using a projection system with a reduction ratio of 4 to 10 times or other magnifications. For example, the original pattern unit corresponding to the pattern area is a single-exposure pattern area formed using a projection system with a reduction ratio of 4 times; another example is a single-exposure pattern area formed using a projection system with a reduction ratio of 5 times; yet another example is a single-exposure pattern area formed using a projection system with a reduction ratio of 8 times; and yet another example is a single-exposure pattern area formed using a projection system with a reduction ratio of 10 times. In other words, the exposure field of this application covers at least two conventional exposure pattern areas (covering the dicing area between the two conventional exposure pattern areas) in a single exposure. By increasing the area of ​​a single exposure, more original pattern units corresponding to the pattern areas can be covered at once, thereby enabling interconnection between chips.

[0111] When the method provided in this application embodiment is applied to the top-layer photolithography process, the original pattern unit corresponding to the pattern area can be understood as the pattern area formed by one exposure in the previous layer photolithography process.

[0112] It should be noted that the front-end lithography process typically employs a projection system with a reduction ratio of 4 to 10. Taking a projection system with a reduction ratio of 5 as an example, after the workpiece stage and mask stage of the lithography machine scan synchronously, the maximum size of the exposure field formed by exposure is generally 26mm × 33mm. In this case, the maximum size of the pattern area corresponding to the original pattern unit is generally less than or equal to 26mm × 33mm.

[0113] In other words, taking the largest 26mm×33mm area as an example, the first exposure area formed in this step covers at least two 26mm×33mm single-exposure pattern areas. Specifically, the first exposure area can cover one, two, three, or four 26mm×33mm single-exposure pattern areas horizontally, and it can also cover one, two, three, or four 26mm×33mm single-exposure pattern areas vertically. When the first exposure area covers one 26mm×33mm single-exposure pattern area horizontally, it will cover two, three, or four 26mm×33mm single-exposure pattern areas vertically; conversely, when the first exposure area covers one 26mm×33mm single-exposure pattern area vertically, it will cover two, three, or four 26mm×33mm single-exposure pattern areas horizontally.

[0114] It should be noted that the 26mm × 33mm mentioned above is a special example; the actual original graphic unit corresponding to the graphic area can also be smaller than 26mm × 33mm. That is to say, the first exposure area formed in this step can cover at least two single-exposure graphic areas smaller than 26mm × 33mm. Specifically, the first exposure area can cover one, two, three, or four single-exposure graphic areas smaller than 26mm × 33mm horizontally, and it can also cover one, two, three, or four single-exposure graphic areas smaller than 26mm × 33mm vertically. When the first exposure area covers one single-exposure pattern area smaller than 26mm×33mm in the horizontal direction, it will cover two, three, or four other single-exposure pattern areas smaller than 26mm×33mm in the vertical direction; when the first exposure area covers one single-exposure pattern area smaller than 26mm×33mm in the vertical direction, it will cover two, three, or four other single-exposure pattern areas smaller than 26mm×33mm in the horizontal direction.

[0115] like Figure 6 The diagram shown is an example of a large exposure field lithography method provided in this application, covering an image area corresponding to M×N original pattern units. Figure 1 The photolithography equipment shown or Figure 4 The photolithography apparatus shown can transfer a preset pattern on the mask 200 to the first exposure area 700 of the substrate 500. The first exposure area covers 2×2 original pattern units corresponding to the pattern areas, specifically covering 2 original pattern units corresponding to the pattern areas horizontally, namely the front pattern 610 and the front pattern 620, and covering 2 original pattern units corresponding to the pattern areas vertically, namely the front pattern 630 and the front pattern 640.

[0116] Through this step, a single exposure can cover the corresponding graphic areas of M×N original graphic units, resulting in a large first exposure area. In this way, multiple chips that could previously only be connected by a few hundred or a few thousand lines can now be connected by tens of thousands or even hundreds of thousands of lines, greatly improving the communication capability between chips and enabling high-density interconnection between multiple chips.

[0117] In existing technologies, chip interconnection is mainly achieved through on-board level interconnection. This method typically involves interconnecting via a circuit board after packaging, resulting in a complex structure and large size. During use, signals need to travel through long circuit board paths, leading to significant signal delays. Furthermore, long traces are susceptible to electromagnetic interference, causing signal distortion. Longer traces and driving circuits also result in larger capacitive loads, inevitably increasing power consumption. In contrast, the large exposure field photolithography method provided in this application enables chip-level interconnection. This allows multiple chips to be connected simultaneously during chip manufacturing. During use, the shortened interconnection distance significantly reduces signal transmission time, lowers the risk of signal distortion, improves signal integrity, and reduces parasitic loads, thereby reducing power consumption.

[0118] Step S103: The substrate is aligned by stepping M times the lateral dimension of the original pattern unit in the lateral direction, or N times the longitudinal dimension of the original pattern unit in the longitudinal direction, using the alignment marks on the substrate, and offset by a set offset distance.

[0119] This step is used to step the substrate after the first exposure area has been exposed, providing a good foundation for the formation of a second exposure area adjacent to the first exposure area on the substrate.

[0120] Before performing the second exposure, a target stepping mode can be selected according to the requirements. The target stepping mode can be either horizontal or vertical. Then, the stage can be controlled to step according to the target stepping mode.

[0121] In step S102, after the first exposure is performed, the size of the first exposure area formed covers at least M (horizontal) × N (vertical) original graphic unit corresponding graphic areas. Thus, when the target stepping mode is horizontal stepping mode, the stepping distance is M times the horizontal size of the original graphic unit; when the target stepping mode is vertical stepping mode, the stepping distance is N times the vertical size of the original graphic unit.

[0122] Specifically, when the target stepping mode is a horizontal stepping mode, the stage is controlled to step horizontally by M times the horizontal dimension of the original graphic unit, so that the substrate is stepped horizontally by M times the horizontal dimension of the original graphic unit; when the target stepping mode is a vertical stepping mode, the stage is controlled to step vertically by N times the vertical dimension of the original graphic unit, so that the substrate is stepped vertically by N times the vertical dimension of the original graphic unit.

[0123] It should be noted that the horizontal dimension and vertical dimension of the original graphic unit can be the same or different. For example, the horizontal dimension of the original graphic unit is 26mm (including the scribe line), and the vertical dimension of the original graphic unit is 33mm (including the scribe line); or the horizontal dimension and vertical dimension of the original graphic unit are both 25mm (including the scribe line).

[0124] Thus, after the stepping is completed, alignment is performed using the alignment marks on the substrate according to the method in step S101, and a set offset distance is set. The alignment and offset distance can be referred to the aforementioned description of step S101, which will not be repeated here.

[0125] Step S104: Perform a second exposure by transferring the preset pattern on the mask to the second exposure area on the substrate through the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0126] This step is used to expose a second exposure area on the substrate, adjacent to the first exposure area.

[0127] By performing a second exposure, the projection system can transfer a preset pattern on the photomask to a second exposure area on the substrate. For example... Figure 7 The diagram illustrates an example of the second exposure region in the large exposure field lithography method provided in this application. After the substrate 500 or mask is longitudinally stepped by twice the distance corresponding to the image size of the original pattern unit, and aligned or offset using a second alignment mark, a second exposure is performed. The preset pattern on the mask is transferred to the second exposure region 710 on the substrate, which is longitudinally adjacent to the first exposure region 700, using a projection system with a magnification of 0.1 to 2.5 times. This second exposure region 710 also covers the 2×2 pattern area corresponding to the original pattern unit. Generally, 710 and 700 will appropriately overlap in their non-functional pattern areas to prevent the appearance of uncontrolled (irrelevant) patterns.

[0128] In this step, after the first exposure area is formed on the substrate, the substrate is first stepped. During lateral stepping, the stepping distance is the size of the pattern area covered by the first exposure area in the lateral direction, and during vertical stepping, the stepping distance is the size of the pattern area covered by the first exposure area in the vertical direction. This avoids the second exposure area formed by the second exposure and the first exposure area from overlapping in the functional pattern area. Then, by aligning with the alignment marks and setting the offset distance, the precise alignment between the mask and the corresponding exposure position on the substrate where the second exposure area is to be formed is ensured, thus guaranteeing the effectiveness of the second exposure.

[0129] Step S105: Continuously perform the lateral stepping or longitudinal stepping and the second exposure until the exposure of all target areas of the substrate is completed.

[0130] This step is used to continuously step through and expose all target areas on the substrate.

[0131] The target area can be the entire area on the substrate or a designated area on the substrate; this application does not impose any restrictions on this.

[0132] After the second exposure in step S104 is completed, the substrate is stepped M times the lateral dimension of the original pattern unit, or N times the longitudinal dimension of the original pattern unit. Then, alignment or alignment offset is performed using alignment marks on the substrate. A second exposure is then performed. This allows the preset pattern on the mask to be transferred to a third exposure area on the substrate via a projection system. The third exposure area covers at least M×N pattern areas corresponding to the original pattern units, and the third exposure area is adjacent to the second exposure area. This process continues until all target areas on the substrate are exposed.

[0133] In this way, after each exposure, the steps of stepping, alignment or alignment bias and re-exposure are performed, which can realize the continuous exposure of multiple exposure areas on the substrate that cover the corresponding pattern areas of at least M×N original pattern units. Furthermore, the stepping distance can effectively avoid the functional patterns between exposure areas from overlapping.

[0134] In one optional embodiment, there are one or two stages. When there are two stages, each stage is loaded with a substrate to be exposed.

[0135] When there are two stages, multiple stages can be controlled to move in turn to the projection system to complete the exposure.

[0136] By using a method of alternating movement of the stage to the projection system to complete the exposure, one stage can perform other preparatory work while the other stage is performing exposure, such as loading the substrate or performing preliminary substrate alignment. In one example, multiple stages include a first stage and a second stage. During the exposure performed by the first stage, the second stage can be controlled to perform silicon wafer loading and unloading and pre-alignment steps. Here, pre-alignment refers to preliminary alignment using alignment marks on the substrate to be exposed loaded on the second stage.

[0137] For example, a lithography machine includes stage a and stage b. During alignment and exposure on stage a, stage b is controlled to perform wafer loading / unloading and pre-alignment. Correspondingly, during alignment and exposure on stage b, stage a is controlled to perform wafer loading / unloading and pre-alignment. In this way, after the first stage completes exposure, the exposure of the second stage can be started immediately, effectively reducing the time the lithography machine is idle. On the other hand, the time consumed by switching between stages is shorter than the time consumed by substrate replacement and preliminary alignment on a single stage, achieving a near-seamless workflow and thus improving lithography efficiency.

[0138] In one optional embodiment, there are three to thirty stages. Each stage carries the substrate, and the three to thirty stages are moved in turn to the projection system to complete the exposure. This approach effectively reduces the idle time of the lithography machine, improving lithography efficiency. Furthermore, since the exposure field of the lithography machine used in this application is already very large, using a circular substrate as the carrier would result in significant waste. For hard and brittle substrates such as ceramics and glass, traditional cutting processes may cause edge damage or cracks. This method, by exposing each substrate independently, avoids the problem of non-destructive cutting of ceramic and glass substrates, improving production flexibility.

[0139] The large exposure field photolithography method provided in the first embodiment of this application involves aligning the substrate with a preset pattern on a photomask after alignment using alignment marks on the substrate and setting a predetermined offset distance. Then, the preset pattern on the photomask is transferred to a first exposure area on the substrate using a projection system. Since the projection system has a reduction ratio of 0.1 to 2.5, the resulting first exposure area will cover at least M×N original pattern units, where at least M and N are integers greater than or equal to 2. Next, the substrate or photomask is stepped laterally by M times the lateral dimension of the original pattern unit, or longitudinally by N times the longitudinal dimension of the original pattern unit, to perform a second exposure. The preset pattern on the photomask is then transferred to the second exposure area on the substrate using the projection system. This second exposure area will again cover at least M×N original pattern units. The steps of stepping laterally by M times the lateral dimension of the original pattern unit or longitudinally by N times the longitudinal dimension of the original pattern unit, along with the second exposure, are performed continuously until the exposure of all target areas on the substrate is completed.

[0140] As can be seen, the large exposure field lithography method provided in this application achieves this by using a projection system with a reduction ratio of 0.1 to 2.5 times to form a large exposure field in a single exposure. It compensates for alignment deviations caused by inconsistent projection magnifications through a biased offset distance. Furthermore, it overcomes image overlap problems when covering multiple patterns at the original pattern unit step distance by stepping M times the lateral dimension of the original pattern unit and N times the vertical dimension of the original pattern unit. This effectively achieves pattern alignment, coverage, and stepping of M×N original pattern units. Continuous stepping, alignment, biasing, and exposure complete the exposure of the target area on the substrate, thereby realizing high-density interconnection of integrated circuits and providing lithography technology support for high-density interconnection integration of multiple large chips.

[0141] The second embodiment of this application provides a method for implementing large exposure field lithography technology, which is applied to a lithography equipment, the lithography equipment including a projection system with a reduction ratio of 0.1 to 2.5 times.

[0142] Before introducing the large-exposure lithography method provided in the second embodiment of this application, the application scenario of the large-exposure lithography method provided in the second embodiment of this application will be introduced first: The second embodiment of this application can integrate different types of chips (such as GPU and high-speed memory) together and support optical communication access. Specifically, firstly, computing chips (such as GPU) and memory chips (such as DRAM) are cut and mounted on a carrier board. The carrier board may contain a portion of pre-designed interconnects for initial electrical connection; then, the large-exposure lithography method provided in the second embodiment of this application is used to further interconnect the chips mounted on the carrier board.

[0143] The large-exposure lithography method provided in the second embodiment of this application interconnects chips of different sizes (such as GPUs and DRAMs), allowing different functional modules to be optimized according to their specific needs and to work collaboratively through efficient interconnection technology. It has at least the following advantages: First, each chip can be optimized for its specific function. For example, a GPU may focus on computationally intensive tasks, while DRAM is designed to provide high-bandwidth memory access, ensuring that each component achieves optimal performance in its assigned task. Second, by interconnecting different types of chips, such as directly connecting a GPU to a cache or DRAM, data transmission latency can be significantly reduced, communication lines increased, and data transmission efficiency improved. Third, it effectively shortens data transmission distance and reduces energy loss caused by long-distance transmission.

[0144] The large exposure field photolithography method provided in the second embodiment of this application specifically includes the following steps:

[0145] The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned using alignment marks on the substrate, and offset by a set offset distance.

[0146] Perform the first exposure by transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0147] The substrate is stepped laterally by the sum of the lateral dimensions of M original pattern units, or longitudinally by the sum of the longitudinal dimensions of N original pattern units, and aligned using alignment marks on the substrate, with a set offset distance.

[0148] A second exposure is performed, in which a preset pattern on the mask is transferred to a second exposure area on the substrate by the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas.

[0149] The lateral stepping or longitudinal stepping and the second exposure are performed continuously until the exposure of all target areas of the substrate is completed;

[0150] Among the M×N original graphic units, at least some of the original graphic units have different sizes; at least M and N are integers greater than or equal to 2.

[0151] The steps described above, namely "loading the patterned substrate to be exposed onto the stage of the photolithography equipment, aligning it with the alignment marks on the substrate, and offsetting it by a set offset distance", and "performing the first exposure, transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system, wherein the first exposure area covers at least M×N original pattern units corresponding to the pattern areas", are the same as steps S101 and S102 in the first embodiment of this application, respectively. Please refer to the relevant description of the corresponding steps in the first embodiment of this application, which will not be repeated here.

[0152] The difference from the first embodiment of this application is that the original patterned units on the substrate in the large exposure field lithography method provided in the first embodiment of this application all have the same size. However, in the second embodiment of this application, the original first patterned unit can be, for example, a GPU, the original second patterned unit can be, for example, a DRAM, and the original third patterned unit can be, for example, a communication module. The original first, second, and third patterned units may have the same or different sizes. In other words, the original patterned units in the second embodiment of this application are not all the same size; there are original patterned units with different sizes.

[0153] Specifically, the original first graphic unit, the original second graphic unit, and the original third graphic unit have the same or different vertical dimensions. That is, the original first graphic unit and the original second graphic unit have the same or different vertical dimensions, the original first graphic unit and the original third graphic unit have the same or different vertical dimensions, and the original second graphic unit and the original third graphic unit have the same or different vertical dimensions.

[0154] Accordingly, the original first graphic unit, the original second graphic unit, and the original third graphic unit have the same or different horizontal dimensions. That is, the original first graphic unit and the original second graphic unit have the same or different horizontal dimensions, the original first graphic unit and the original third graphic unit have the same or different horizontal dimensions, and the original second graphic unit and the original third graphic unit have the same or different horizontal dimensions.

[0155] When the original first graphic unit, the original second graphic unit, and the original third graphic unit have different longitudinal dimensions, after the first exposure area covering at least M×N original graphic units is exposed by the mask, the substrate can be stepped along the longitudinal direction by the sum of the longitudinal dimensions of N original graphic units, and alignment, offset, and exposure can be performed to transfer the preset pattern on the mask to the exposure area that is longitudinally adjacent to the first exposure area.

[0156] like Figure 8 The diagram illustrates an example of an M×N chip group comprising multiple original patterned units of different sizes in the large exposure field photolithography method provided in this application embodiment. The 2×2 chip group includes original patterned units 610, 620, 630, and 640. After selecting the first mask to complete the exposure of the exposure areas covering the original patterned units 610, 620, 630, and 640, the substrate can be moved longitudinally by the sum of the longitudinal dimensions of the original patterned units 610 and 630, thereby exposing the exposure areas of the patterned units corresponding to the original patterned units 610, 620, 630, and 640 in the exposure area adjacent to the longitudinal direction of the exposure area 700.

[0157] Accordingly, after the first exposure area, which covers at least M×N original pattern units corresponding to the pattern area, is exposed by the mask, the substrate can be stepped laterally by the sum of the lateral dimensions of M original pattern units, and alignment, offset and exposure can be performed to transfer the preset pattern on the mask to the exposure area that is laterally adjacent to the first exposure area.

[0158] Combined with appendix Figure 8The 2×2 chipset includes original pattern units 610, 620, 630, and 640. After selecting the first mask to complete the exposure of the exposure areas covering the original pattern units 610, 620, 630, and 640, the substrate can be laterally moved by the sum of the lateral dimensions of the original pattern units 610 and 620. This allows for the exposure of the exposure areas of the pattern units corresponding to the original pattern units 610, 620, 630, and 640 in the exposure area laterally adjacent to the exposure area 700.

[0159] Optionally, the original graphic unit includes a composite original graphic unit, which includes at least two of the original first graphic units, the original second graphic unit, and the graphic units in the original third graphic unit.

[0160] like Figure 9 The diagram shown is a schematic diagram of an example of a composite original pattern unit in the large exposure field photolithography technology implementation method provided in this application embodiment. Both the original pattern unit 630 and the original pattern unit 640 are composite original pattern units. The original pattern unit 630 includes original pattern unit 6301 and original pattern unit 6302, and the original pattern unit 640 includes original pattern unit 6401 and original pattern unit 6402.

[0161] It should be noted that different graphic unit sizes in embodiments mainly occur when different chips are mounted on the carrier board, and even the chips come from different manufacturers. Taking the simultaneous occurrence of multiple rows and columns (M and N are both greater than or equal to 2) of different graphic unit sizes as an example, the sum of the horizontal dimensions of the aforementioned M original graphic units, or the sum of the vertical dimensions of the N original graphic units, is not necessarily equal and cannot be mechanically added together. For example, if mechanically added together, using... Figure 8 For example, the cumulative vertical dimensions on the left (e.g., 610, 630) are not necessarily equal to the cumulative vertical dimensions on the right (e.g., 620, 640), or the cumulative horizontal dimensions at the top (e.g., 610, 620) are not necessarily equal to the cumulative horizontal dimensions at the bottom (e.g., 630, 640). To overcome this problem, when placing the graphics on the carrier board, it is necessary to plan the dimensions of each original graphic in both the vertical and horizontal directions (e.g., using the dimensions of the larger original graphic units as a reference). When gaps exist, they need to be filled and polished to prevent exposure depth-of-field issues.

[0162] The third embodiment of this application also provides a chip-level chip interconnection method, including the following steps:

[0163] A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having an in-chip interconnect and no interconnect between the semiconductor chips.

[0164] The photolithography steps for interconnecting the at least two semiconductor chips are achieved by using the large exposure field photolithography method provided in the first embodiment of this application or the large exposure field photolithography method provided in the second embodiment of this application.

[0165] In this embodiment, two, three, four, six, eight, or nine semiconductor chips have been fabricated on the substrate using processes such as photolithography, etching, and deposition. Furthermore, internal metal layers (such as copper interconnects) within each semiconductor chip form intra-chip interconnects, but there are no inter-chip interconnects.

[0166] The at least two semiconductor chips can be arranged horizontally, vertically, or in a matrix. For example, a semiconductor structure comprising 2×1 semiconductor chips is formed on the substrate; another example is a semiconductor structure comprising 1×2 semiconductor chips formed on the substrate; yet another example is a semiconductor structure comprising 2×3 semiconductor chips formed on the substrate.

[0167] Each of the semiconductor chips can be a single-exposure patterned area formed using a projection system with a reduction ratio of 4 to 10 times or other ratios. For example, each of the semiconductor chips is a single-exposure patterned area formed using a projection system with a reduction ratio of 4 times; another example is that each of the semiconductor chips is a single-exposure patterned area formed using a projection system with a reduction ratio of 5 times; yet another example is that each of the semiconductor chips is a single-exposure patterned area formed using a projection system with a reduction ratio of 8 times; and yet another example is that each of the semiconductor chips is a single-exposure patterned area formed using a projection system with a reduction ratio of 10 times.

[0168] Taking a projection system with a scaling factor of 5 as an example, the size of each semiconductor chip formed is generally up to 26mm × 33mm.

[0169] It should be understood that the size of each semiconductor chip formed can also be less than 26mm×33mm, such as 25mm×30mm, etc. This application does not limit the specific size of the semiconductor chip.

[0170] The single semiconductor chip can be understood as the original pattern unit corresponding to the pattern area in the large exposure field photolithography method provided in the first embodiment of this application.

[0171] With the substrate described above provided, the photolithography steps for interconnecting the at least two semiconductor chips can be implemented using the large exposure field photolithography technique provided in the first embodiment of this application.

[0172] It should be noted that the photolithography steps for realizing the interconnection between the at least two semiconductor chips through the large exposure field photolithography method provided in the first embodiment of this application can refer to the foregoing description of the large exposure field photolithography method provided in the first embodiment of this application or the large exposure field photolithography method provided in the second embodiment of this application, and will not be repeated here.

[0173] As can be seen, the chip-level interconnection method provided in this application embodiment can realize high-density interconnection of integrated circuits and provide photolithography technology support for high-density interconnection and integration of multiple large chips.

[0174] The fourth embodiment of this application also provides a photolithography apparatus, which includes a projection system with a reduction ratio of 0.1 to 2.5 times. The photolithography apparatus has been described in detail above and will not be repeated here.

[0175] As can be seen, the lithography equipment provided in this application embodiment enables a large-size exposure field to be formed on the substrate in a single exposure through a projection system with a reduction ratio of 0.1 to 2.5 times, thereby realizing high-density interconnection of integrated circuits and providing lithography technology support for high-density interconnection and integration of multiple large chips.

[0176] It should be noted that the photolithography equipment provided in this application embodiment, in addition to being used in top-layer or second-layer photolithography processes to achieve high-density interconnection of multiple large chips, can also be applied to the first-layer photolithography STI (also known as shallow trench isolation). STI is a step performed in the initial stage of integrated circuit manufacturing, mainly used to create shallow trenches on the silicon wafer surface and fill them with insulating material to isolate different active regions (such as the source and drain of transistors). The photolithography equipment provided in this application embodiment can cover more areas at once during the STI stage, improving production efficiency.

[0177] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A method for implementing large exposure field photolithography, characterized in that, The method is applied to a photolithography apparatus, the photolithography apparatus including a projection system with a reduction ratio of 0.1 to 2.5 times, and includes: The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned using the alignment marks of the original patterned units on the substrate, and offset by a set offset distance; each original patterned unit has its own alignment mark. The first exposure is performed by transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas, so that the M×N original pattern units are interconnected. The substrate is stepped M times the lateral dimension of the original pattern unit in the lateral direction, or N times the longitudinal dimension of the original pattern unit in the longitudinal direction, and aligned using the alignment marks of the original pattern unit on the substrate, and offset by a set offset distance. A second exposure is performed, in which a preset pattern on the mask is transferred to a second exposure area on the substrate through the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas, so that another set of M×N original pattern units are interconnected. The horizontal or vertical stepping and the second exposure are continuously executed until the exposure of all target areas of the substrate is completed. The distance of each step is M times the horizontal dimension of the original pattern unit or N times the vertical dimension of the original pattern unit, so that adjacent exposure areas can be seamlessly spliced ​​in the functional pattern area and the functional patterns can be avoided from overlapping. Wherein, at least one of M and N is an integer greater than or equal to 2.

2. The method according to claim 1, characterized in that, Also includes: When the alignment mark on the substrate is an alignment mark set for the projection system at a reduction ratio of 0.1 to 2.5, the set offset distance is 0.

3. The method according to claim 1, characterized in that, The reduction ratio of the projection system includes any one of 0.1, 0.125, 0.2, 0.25, 0.4, 0.5, 1.0, 1.25, 2, and 2.5 times.

4. The method according to claim 1, characterized in that, The size of the first exposure area is M×N times 26mm×33mm.

5. The method according to claim 1, characterized in that, The stage may be one or two, and each stage is loaded with a substrate to be exposed.

6. The method according to claim 5, characterized in that, When there are two stages, the method further includes: The two stages are controlled to move alternately under the projection system to complete the exposure.

7. The method according to claim 6, characterized in that, The two stages include a first stage and a second stage, and the method further includes: During the alignment and exposure process performed on the first stage, the second stage is controlled to perform silicon wafer loading and unloading and pre-alignment steps.

8. A method for implementing large exposure field photolithography, characterized in that, The method is applied to a photolithography apparatus, the photolithography apparatus including a projection system with a reduction ratio of 0.1 to 2.5 times, and includes: The patterned substrate to be exposed is loaded onto the stage of the photolithography equipment, aligned using the alignment marks of the original patterned units on the substrate, and offset by a set offset distance; each original patterned unit has its own alignment mark. The first exposure is performed by transferring the preset pattern on the mask to the first exposure area on the substrate through the projection system. The first exposure area covers at least M×N original pattern units corresponding to the pattern areas, so that the M×N original pattern units are interconnected. The substrate is stepped by the sum of the lateral dimensions of M original pattern units or the sum of the longitudinal dimensions of N original pattern units, and aligned using the alignment marks of the original pattern units on the substrate, with a set offset distance. A second exposure is performed, in which a preset pattern on the mask is transferred to a second exposure area on the substrate through the projection system. The second exposure area covers at least M×N original pattern units corresponding to the pattern areas, so that another set of M×N original pattern units are interconnected. The horizontal or vertical stepping and the second exposure are continuously executed until the exposure of all target areas of the substrate is completed. The distance of each step is M times the horizontal dimension of the original pattern unit or N times the vertical dimension of the original pattern unit, so that adjacent exposure areas can be seamlessly spliced ​​in the functional pattern area and the functional patterns can be avoided from overlapping. Among the M×N original graphic units, at least some of the original graphic units have different sizes; at least M and N are integers greater than or equal to 2.

9. A chip-level chip interconnection method, characterized in that, include; A substrate is provided on which a semiconductor structure comprising at least two semiconductor chips is formed, each semiconductor chip having an in-chip interconnect and no interconnect between the semiconductor chips; The photolithography steps for interconnecting the at least two semiconductor chips are achieved by using the large exposure field photolithography technique method described in any one of claims 1-8.

10. A photolithography apparatus, characterized in that, The system includes a projection system with a reduction ratio of 0.1 to 2.5 times; the lithography apparatus is used to perform the method of claim 9 to achieve interconnection between the at least two semiconductor chips.

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