DEM-based voltage and current conversion device and method

Abstract

The invention provides a DEM-based voltage and current conversion device and method, and the device comprises a current generation module, the current generation module generates a current ISET, and the ISET passes through a DEM module and is inputted to a current amplification module; the current amplification module comprises a plurality of PMOS transistors; the voltage following digital ground module generates a dynamically adjusted digital ground DGND according to the grid voltage of a transistor in the current amplification module; the clock frequency division shift module generates a clock of which the amplitude is in linear relation with the ISET according to the DGND, and controls the DEM module to perform periodic switching; a switch tube in the DEM module performs periodic switching based on a clock, dynamic element matching is performed, a transistor in the periodic switching current amplification module amplifies ISET, and IOUT is output.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuit design, and particularly relates to a voltage-current conversion device and method based on DEM. BACKGROUND

[0002] With the development of electronic technology, more electronic circuit applications require converting voltage signals into precisely amplified current signals. Voltage-current amplifiers, as a kind of high-performance amplifiers, are favored in various application scenarios. Voltage-current amplifiers integrate key components inside the amplifier to achieve low gain error, low nonlinearity error, low offset drift and other characteristics with specific structures.

[0003] Generally, the input voltage V VIN is copied to the other end of a high-precision low-temperature-drift resistor R SET , and the I SET current is obtained through the voltage-to-resistance ratio, and then output after current amplification. The use of a common-source common-gate structure reduces the influence of the output voltage on the drain-source voltage, which can improve the accuracy of the output current. At the same time, a large-area PMOS tube is used to form a current mirror, and through multi-bit trimming, the influence of mismatch on the performance of the transistor is reduced.

[0004] The prior art with the application number CN118349064A discloses a VI conversion circuit based on DEM and trimming technology, which has a total of 12 current mirror tubes, of which 1 current mirror tube is connected to a calibration branch, 1 current mirror tube is connected to an input branch, and the remaining 10 current mirror tubes are connected to an output branch. The calibration is performed with the reference branch as a template. Using DEM technology, each current mirror tube is calibrated after 12 cycles, and the ratio of the output current to the input current is 10:1. However, due to the switching of the DEM technology, a large number of glitches are generated in the output waveform, and the glitches are periodic and have the same direction peak. The amplitude is greatly affected by the input current, so that the direct current component introduced by the glitch changes with the input current, affecting the gain error in the current range. SUMMARY

[0005] The prior art increases the area of the current mirror PMOS tube and adds a multi-bit trimming circuit to improve the output current accuracy of the voltage-current amplifier. However, the large-area PMOS tube increases the layout area, and in order to reduce the influence of mismatch, a better matching method and more complex wiring are needed, which limits the width of the metal line. Since the overcurrent capacity of the metal is limited, the maximum value of the output current may be limited. In addition, increasing the trimming requires more complex circuit design and production cost. Due to the large process mismatch range of the PMOS tube, a small amount of trimming still increases the deviation of the current amplification factor, and the gain error in the current range is large, while the multi-bit trimming increases the layout area.

[0006] Therefore, it is necessary to switch the current branch by the DEM technology, which aims to calibrate all the current mirror branches. However, due to the switching of the DEM technology, a large number of glitches are generated in the output waveform, and the glitches are periodic and have the same direction peak, and the amplitude is greatly affected by the input current, so that the direct current component introduced by the glitches changes with the input current, which affects the gain error in the current range. Even if a low-pass filter is used, only the high-frequency component of the glitch can be filtered out, but the direct current component of the glitch cannot be filtered out, and the average value of the output current and the gain error in the current range are still affected.

[0007] In order to solve the above technical problems, the technical scheme provided by the present application is: a high-precision voltage-current converter based on DEM, comprising a current generation module, the current generation module generates a current I SET , I SET passes through the DEM module, and an input current amplification module; the current amplification module comprises a plurality of PMOS transistors; a digital ground module following the voltage generates a dynamically adjusted digital ground DGND according to the gate voltage of the transistor in the current amplification module; a clock frequency shift module generates a clock with a linear relationship with I SET amplitude according to the DGND, and controls the DEM module to perform periodic switching; the transistors in the DEM module are periodically switched based on the clock to perform dynamic element matching, and the transistors in the current amplification module are periodically switched to amplify I SET , and output I OUT .

[0008] Specifically, the current amplification module includes a PMOS tube group PM1 composed of n+1 PMOS tubes; the gate of each PMOS tube in PM1 is used as the input end of I SET , and the source is connected to the positive voltage VSP; PM1 is controlled by the DEM module, and in a period, one of the PMOS tubes is switched to a diode connection, and the remaining PMOS tubes form a current amplification mirror to amplify the current by n times.

[0009] Specifically, the DEM module includes two groups of PMOS transistors K1 and K2, and the clock frequency shift module includes clocks Φ1 and Φ2, and the clocks Φ1 and Φ2 control the PMOS transistors K1 and K2 to perform periodic switching; the number of K1 and K2 transistors is the same as the number of PMOS tubes in PM1, and they are connected one by one; the source of each transistor of K1 is connected to the gate of the corresponding transistor in PM1, and the drain of each transistor of K1 is connected to the drain of the corresponding transistor in PM1; the source of each transistor of K2 is connected to the drain of the corresponding transistor in PM1, and the drain of each transistor of K2 is used as the output end of I OUT .

[0010] Specifically, the voltage-following digital ground module includes three ground branches connected in parallel to a positive supply voltage VSP; the first branch includes, in series, an NMOS transistor NM1, a resistor R1 and a PMOS transistor PM2; the drain of NM1 is connected to the positive supply voltage VSP, the gate of NM1 is connected to the gate of PM1, and the source of NM1 is connected to one end of R1; the source of PM2 is connected to the other end of R1, the drain of PM2 is connected to one end of a current source I1, the other end of I1 is grounded, and the gate of PM2 is shorted to the drain of PM2; the second branch includes PMOS transistors PM4 and PM3; the source of PM4 is connected to the positive supply voltage VSP, and the drain of PM4 is connected to the source of PM3; the gate of PM3 is connected to the gate of PM2, the drain of PM3 is grounded, and the source of PM3 is connected to the output end of a digital ground DGND as an output end of a clock frequency division shift module; and the third branch is provided with a PMOS transistor PM5; the source of PM5 is connected to the positive supply voltage VSP, the gate of PM5 is connected to the gate of PM4, and the gate of PM5 is shorted to the drain of PM5; and the drain of PM5 is connected to one end of a current source I2, and the other end of I2 is grounded.

[0011] Specifically, the DGND voltage and the input current I SET are in a linear relationship; the clock frequency division shift module generates a clock Φ1 and a clock Φ2 having a linear relationship with I SET and complementary duty cycles according to a voltage difference between the input voltage and the DGND.

[0012] Specifically, the input current I SET increases, the gate voltage of the PMOS transistor group in the current amplification module decreases, the DGND voltage decreases, and the lowest potential of Φ1 decreases, so that the gate-source voltage of the DEM module transistor group when the transistor group is turned on remains unchanged, the on-resistance does not change with the input voltage, the change of the gate RC constant of the PMOS transistor group is suppressed, and the amplitude of the glitch generated by the switching of the DEM module changes with the input current.

[0013] Specifically, the clock frequency division shift module is provided with a variable k, which is cyclically increased from 1 to n+1 in a cycle; in a cycle, the clock frequency division shift module controls the kth transistor in the transistor group K1 of the DEM module to be turned on and the other transistors to be turned off, and controls the kth transistor in the transistor group K2 to be turned off and the other transistors to be turned on, so as to control the kth PMOS transistor to be switched to a diode connection.

[0014] Specifically, the sizes of PM2 and PM3 are the same, and the sizes of PMOS transistors PM4 and PM5 are the same.

[0015] Specifically, the current generation module includes an operational amplifier, an NMOS transistor NM0 and a resistor R SET ; the same input end of the operational amplifier is an input end of a voltage signal V VIN , and the operational amplifier and the NMOS transistor NM0 constitute a unit gain negative feedback.

[0016] A DEM-based voltage-to-current conversion method applied to the DEM-based voltage-to-current conversion device described above, comprising the following steps: S1, a voltage signal V VIN An input current generation module generates a current I SET ; S2, I SET The input current amplification module is controlled by the DEM module, and the DEM module periodically switches the on-off of the PMOS transistor group in the current amplification module through two groups of transistors K1 and K2 to amplify the current; S3, the current amplification module controls the voltage following digital ground module to generate a dynamically adjusted digital ground DGND; S4, the dynamic DGND is provided to the clock frequency division shift module, and the clock frequency division shift module generates a clock that has a linear relationship with I SET The amplitude and controls the DEM module to periodically switch on and off.

[0017] The beneficial effects of the present application are: the present application converts a voltage signal into a current signal, modulates the influence of mismatch to high frequency through DEM technology, and distributes the influence evenly in a period, thereby improving the accuracy of the average output current. This scheme overcomes the influence of process mismatch on the current mirror, does not require complex matching methods and wiring forms, improves the upper limit of the metal line width and the output current. At the same time, the present application designs a voltage following DGND, so that the on-resistance of the switch does not change with the input current. Therefore, the DC component introduced by the burr becomes more constant, and the gain error in the current range is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 It is a schematic diagram of the current generation module circuit of the present application.

[0019] Figure 2 It is a schematic diagram of the DEM module, the current amplification module and the digital ground module circuit of the present application.

[0020] Figure 3 It is a switch control logic flow chart of the DEM module. DETAILED DESCRIPTION

[0021] The present application will be described in detail below in combination with the drawings and examples.

[0022] Example 1: A DEM-based voltage-to-current conversion device, comprising a current generation module, a voltage signal V VIN An input current generation module generates a current I SET , I SET Controlled by the DEM module, dynamic element matching is performed; I SETInput current amplification module; the current amplification module includes several PMOS transistors, the switch period of DEM module Current amplification module transistor switching, output I OUT ; Voltage following digital ground module according to the gate voltage of the transistor in the current amplification module, generate dynamic adjustment of digital ground DGND; Clock frequency shift module according to DGND, generate amplitude and I SET Linear relationship of clock control DEM module for periodic switching.

[0023] DEM module includes two groups of 11 PMOS switch K1 <1:11> and K2 <1:11>, respectively controlled by clock frequency shift module clock Φ1 <1:11> and Φ2 <1:11>, for periodic switching.

[0024] The current amplification module of the embodiment includes 11 PMOS transistors PM1 <1:11>, one of which is diode connection, and the other 10 PMOS transistors achieve 10 times amplification effect.

[0025] In a period, the clock frequency shift module controls the switch group K1 in the DEM module, only the kth switch K1 <k>Conducting, other is disconnected; Only the kth switch tube K2 in switch tube group K2 <k>off, others on.

[0026] kth PMOS transistor PM1 in the current amplification module <k>is diode connection, other PMOS transistors constitute 10 times current mirror for current amplification.

[0027] In a cycle, the clock frequency shift module controls k from 1 to 11, completes a cycle, a cycle of continuous output amplification 10 times the current I OUT .

[0028] The gate voltage of PM1 in the current amplification module is output to the voltage follower digital ground module, and the DGND voltage of the digital ground module is linearly related to I SET The clock frequency shift module generates clock Φ1<1:11> and 1 / 11 clock Φ2<1:11> with amplitude linearly related to I SET and duty cycle of 10 / 11 and 1 / 11 respectively according to the voltage difference between the input voltage and DGND.

[0029] When the input current I SET increases, the gate voltage of PM1 in the current amplification module decreases, the DGND voltage decreases, and the lowest potential of Φ1 decreases, ensuring that the gate-source voltage of the switch tube group K1 is unchanged when it is turned on, so that the on-resistance of the switch does not change with the input voltage, thereby suppressing the change of PM1 gate RC constant and reducing the amplitude of the glitch generated by the DEM module switching.

[0030] In a cycle, the clock frequency shift module judges the value of k and performs shift register, if k is not equal to 11, k is incremented; if k is equal to 11, k is assigned to 1.

[0031] The current generation module includes an operational amplifier, an NMOS tube NM0 and a resistor R SET , the same input end of the operational amplifier as the input end of the voltage signal V VIN , the operational amplifier and the NMOS tube NM0 constitute a unit gain negative feedback.

[0032] The voltage signal V VIN is input to the same input end of the operational amplifier, and the operational amplifier and the NMOS tube NM0 constitute a unit gain negative feedback. If the gain of the operational amplifier is large enough, according to the "virtual short" principle, the voltage at the reverse input end of the operational amplifier is equal to V VIN , which is converted into current I SET through the ratio of voltage V VIN and resistor R SET . Current I SET flows into the current amplification module after passing through the dynamic element matching (DEM) module.

[0033] The DGND voltage generated by the voltage follower digital ground module is linearly related to I SET linearly; the clock frequency shift module generates clock Φ1<1:11> and clock Φ2<1:11> with linear relationship and duty ratio of 10 / 11 and 1 / 11 respectively according to the voltage difference between the input voltage and DGND SET linearly and duty ratio of 10 / 11 and 1 / 11 respectively. The switch of DEM module switches the transistor in current mirror module constantly, maintaining the ability of current mirror module to amplify current. The current I SET is amplified 10 times to get output current I OUT .

[0034] When the external input voltage V VIN is input, the voltage difference between the input voltage and DGND is amplified by the operational amplifier, NMOS transistor NM0 and resistor R SET to generate current I SET , which flows into the DEM module. If k equals 1 in the initial state, the first switch K1<1> in K1 is turned on and other switches K1<2:11> are turned off; the first switch K2<1> in K2 is turned off and other switches K2<2:11> are turned on. Under the control of DEM module, the first PMOS transistor PM1<1> is connected in diode mode and other 10 PMOS transistors PM1<2:11> constitute 10 times current mirror. After the clock frequency shift module judges the value of k, the shift register is performed. Since k is not equal to 11, k is increased to 2. At this time, the second switch K1<2> in K1 is turned on and other switches K1<1> and K1<3:11> are turned off; the second switch K2<2> in K2 is turned off and other switches K2<1> and K2<3:11> are turned on. Under the control of DEM module, the second PMOS transistor PM1<2> is connected in diode mode and other 10 PMOS transistors PM1<1> and PM1<3:11> constitute 10 times current mirror. After the clock frequency shift module judges the value of k, the shift register is performed. Since k is not equal to 11, k is increased, and the above operation will be repeated. When k is increased to 11, the eleventh switch K1<11> in K1 is turned on and other switches K1<1:10> are turned off; the eleventh switch K2<11> in K2 is turned off and other switches K2<1:10> are turned on. Under the control of DEM module, the eleventh PMOS transistor PM1<11> is connected in diode mode and other 10 PMOS transistors PM1<1:10> constitute 10 times current mirror. After the clock frequency shift module judges the value of k, the shift register is performed. Since k is equal to 11, k is reset to 1, completing a cycle. In this process, the continuous output current I OUT is output. After 11 times of repeated operation in the above cycle, each PMOS transistor of PM1 is connected in diode mode once and is used to output current 10 times.

[0035] If there is mismatch between PMOS transistors in PM1 due to process generation, the current amplification factor of each time in a cycle deviates from the ideal gain, but after dynamic element matching, the influence of mismatch is modulated to high frequency and evenly distributed in the cycle. After external low-pass filtering, the current in a cycle is averaged, the ratio between the average output current and the average input current tends to the ideal gain, the influence of process mismatch is averaged, the precision of average output current is improved, and the gain error in the current range is reduced. In addition, this scheme overcomes the influence of process mismatch on the current mirror, and does not require complex matching methods and wiring forms.

[0036] Due to the switching of the DEM module, a large number of glitches are generated in the output waveform, and the glitches are periodic and have the same direction peak. The amplitude is greatly affected by the input current, so that the direct current component introduced by the glitch changes with the input current, which affects the gain error in the current range. Even if a low-pass filter is used, only the high-frequency component of the glitch can be filtered out, but the direct current component of the glitch cannot be filtered out, which still affects the average value of the output current and the gain error in the current range.

[0037] The specific circuit of the DEM module, the current amplification module and the voltage follower digital ground module is shown in Figure 2 The DEM module is composed of PMOS switch tube groups K1<1:11> and K2<1:11>, which are controlled by clocks Φ1<1:11> and Φ2<1:11> respectively. The current amplification module is composed of PMOS switch tube group PM1<1:11>, of which 10 transistors are used as current amplification elements to achieve a 10-fold amplification effect. The voltage follower digital ground module includes three ground branches connected in parallel to the positive supply voltage VSP; the first branch includes NMOS tube NM1, resistor R1 and PMOS tube PM2 connected in series; the drain of NM1 is connected to the positive voltage VSP, the gate is connected to the gate of PM1, and the source is connected to one end of R1; the source of PM2 is connected to the other end of R1, the drain is connected to one end of current source I1, the other end of I1 is grounded, and the gate of PM2 is shorted with the drain; the second branch includes PMOS tubes PM4 and PM3; the source of PM4 is connected to the positive voltage VSP, and the drain is connected to the source of PM3; the gate of PM3 is connected to the gate of PM2, the drain is grounded, and the source is connected to the output end of the digital ground DGND connected to the clock frequency division shift module; the third branch is provided with PMOS tube PM5; the source of PM5 is connected to the positive voltage VSP, the gate is connected to the gate of PM4, and the gate of PM5 is shorted with the drain of PM5; the drain of PM5 is connected to one end of current source I2, and the other end of I2 is grounded.

[0038] The DEM module is controlled by Φ1<1:11> and Φ2<1:11>, and the state of the switch controls PM1 to form a 10 times current mirror. The gate voltage of PM1 is output to the voltage following digital ground module, and the voltage at point A is obtained through NM1 and R1 A In this embodiment, PM2 and PM3 are of the same size, PMOS PM4 and PM5 are of the same size, and I1 is equal to I2, that is, the voltage of DGND is equal to V A The size of V SG,PM1 is linearly related to I SET , so the voltage of DGND is also linearly related to I SET . The clock frequency division shift module generates clock Φ1<1:11> and 1 / 11 clock Φ2<1:11> with amplitude linearly related to I SET and duty cycle of 10 / 11 and 1 / 11 respectively according to the voltage difference between VSP and DGND.

[0039] If there is a mismatch between the PMOS transistors in PM1 due to process generation, the current amplification factor deviates from the ideal gain each time in a cycle, but after dynamic element matching, the effect of the mismatch is modulated to high frequency and evenly distributed in a cycle. After external low-pass filtering, the current in a cycle is averaged, and the ratio between the average of the input and output currents tends to the ideal gain, the effect of process mismatch is averaged, the precision of the average output current is improved, and the gain error in the current range is reduced. In addition, this scheme overcomes the influence of process mismatch on the current mirror, without the need for complex matching methods and wiring forms.

[0040] When the input current I SET increases, the gate voltage of PM1 in the current amplification module decreases, the DGND voltage decreases, and the lowest potential of Φ1 decreases, ensuring that V GS does not change when K1 is turned on, so that the on-resistance of the switch does not change with the input voltage. Therefore, even if the size of the input current I SET changes, the change of the PM1 gate RC constant can be suppressed, thereby reducing the change of the glitch amplitude with the input current, and the DC component introduced by the glitch becomes more constant, thereby reducing the gain error in the current range.

[0041] The embodiment realizes high-precision voltage current converter, can linearly convert voltage provided by sensor, DAC or MCU into high-precision milliampere current signal. It is suitable for instrument transmitter, industrial controller, analog output module and PLC output driver. In use, voltage signal is converted into current signal, DEM technology is used to modulate the influence caused by mismatch to high frequency, and average distribution is realized in a cycle, the precision of average output current is improved. The scheme overcomes the influence of process mismatch on current mirror, does not need complex matching mode and wiring form, improves the upper limit of metal line width and output current. Meanwhile, the voltage following DGND is designed, the on-resistance of switch does not change with input current, therefore, the DC component introduced by burr becomes more constant, the gain error in current range is reduced.

[0042] Embodiment two: a high-precision voltage current converter based on DEM, comprising an operational amplifier module, voltage signal V VIN Input operational amplifier module to generate current I SET , SET Input DEM module, DEM module carries out dynamic element matching control I SET flows into current amplification module; the current amplification module comprises 11 PMOS transistors, the switch period of the DEM module switches the transistor in the current amplification module to carry out current amplification; the current amplification module controls the voltage following digital ground module, generates dynamically adjusted digital ground DGND; the dynamic DGND is provided for clock frequency division shift module, the clock frequency division shift module generates clock control DEM module with linear relationship with I SET Periodic switch of the module is carried out.

[0043] Voltage signal V VIN Is input to the same direction input end of operational amplifier, the operational amplifier and NMOS tube NM0 constitute unit gain negative feedback. If the gain of operational amplifier is large enough, according to the principle of "virtual short", the voltage of reverse input end of operational amplifier is equal to V VIN , through the ratio of voltage V VIN And resistance R SET , it is converted into current I SET =V VIN / R SET . Current I SET flows into current amplification module after dynamic element matching (DEM) module, the current amplification module according to I SET The control voltage follows the digital ground module to generate a dynamically adjusted digital ground (DGND). The dynamic DGND is provided to the clock division and shift module to generate a clock with different amplitudes, which controls the DEM module after clock division and shift. The switches of the DEM module constantly switch the transistors in the current amplification module to maintain the 10 times amplification capability of the current amplification module. The current I SET is amplified 10 times to obtain the output current I OUT .

[0044] The specific circuit of the DEM module, the current amplification module, and the voltage-following digital ground module is shown in Figure 2 . The DEM module is composed of PMOS switch tube groups K1<1:11> and K2<1:11>, which are controlled by clocks Φ1<1:11> and Φ2<1:11>, respectively. The current amplification module is composed of PMOS transistor group PM1<1:11>, which consists of 10 transistors to achieve 10 times amplification effect. The voltage-following digital ground module includes three ground branches connected in parallel to the positive supply voltage VSP; the first branch includes NMOS tube NM1, resistor R1, and PMOS tube PM2 connected in series; the drain of NM1 is connected to the positive voltage VSP, the gate is connected to the gate of PM1, and the source is connected to one end of R1; the source of PM2 is connected to the other end of R1, the drain is connected to one end of current source I1, the other end of I1 is grounded, and the gate of PM2 is shorted with the drain; the second branch includes PMOS tubes PM4 and PM3; the source of PM4 is connected to the positive voltage VSP, and the drain is connected to the source of PM3; the gate of PM3 is connected to the gate of PM2, the drain is grounded, and the source is connected to the output end of the digital ground DGND connected to the clock division and shift module; the third branch is provided with PMOS tube PM5; the source of PM5 is connected to the positive voltage VSP, the gate is connected to the gate of PM4, and the gate of PM5 is shorted with the drain of PM5 itself; the drain of PM5 is connected to one end of current source I2, and the other end of I2 is grounded.

[0045] As shown in Figure 1 , when the external input voltage V VIN is applied, the current I SET is generated by the operational amplifier, NMOS tube NM0, and resistor R SET , and flows into the DEM module. As shown in Figure 3 As shown, in the DEM module, if k equals 1 in the initial state, the first switch K1<1> in K1 is turned on, and other switches K1<2:11> are turned off; the first switch K2<1> in K2 is turned off, and other switches K2<2:11> are turned on. Under the control of the DEM module, the first PMOS transistor PM1<1> is in diode connection, and other 10 PMOS transistors PM1<2:11> constitute a current amplification module. After the clock frequency division shift module judges the value of k, shift register is performed, and since k is not equal to 11, k is increased to 2. At this time, the second switch K1<2> in K1 is turned on, and other switches K1<1> and K1<3:11> are turned off; the second switch K2<2> in K2 is turned off, and other switches K2<1> and K2<3:11> are turned on. Under the control of the DEM module, the second PMOS transistor PM1<2> is in diode connection, and other 10 PMOS transistors PM1<1> and PM1<3:11> constitute a 10 times current mirror. After the clock frequency division shift module judges the value of k, shift register is performed, and since k is not equal to 11, k is increased, and the above operation will be repeated. When k is increased to 11, the eleventh switch K1<11> in K1 is turned on, and other switches K1<1:10> are turned off; the eleventh switch K2<11> in K2 is turned off, and other switches K2<1:10> are turned on. Under the control of the DEM module, the eleventh PMOS transistor PM1<11> is in diode connection, and other 10 PMOS transistors PM1<1:10> constitute a 10 times current mirror. After the clock frequency division shift module judges the value of k, shift register is performed, and since k is equal to 11, k will be reset to 1, and a period is completed. In this process, the output current I OUT After 11 repeated operations in the above period, each PMOS transistor of PM1 is connected in diode connection once and used for outputting current 10 times.

[0046] If there is mismatch between PMOS transistors in PM1 due to process generation, the current amplification multiple deviates from the ideal gain each time in a period, but after dynamic element matching, the influence of mismatch is modulated to high frequency and is evenly distributed in the period. After external low-pass filtering, the current in a period is averaged, the ratio between the average value of the output current and the average value of the input current tends to the ideal gain, the influence of process mismatch is averaged, the precision of the average output current is improved, and the gain error in the current range is reduced. In addition, the scheme overcomes the influence of process mismatch on the current mirror, and does not need complex matching mode and wiring form.

[0047] Due to the switching of the DEM module switch, a large number of glitches are generated in the output waveform, and the glitches are periodic and have the same direction peak, and the amplitude is greatly affected by the input current, so that the direct current component introduced by the glitches changes with the input current, and the gain error in the current range is affected. Even if a low-pass filter is used, only the high-frequency component of the glitch can be filtered out, but the direct current component of the glitch cannot be filtered out, and the average value of the output current and the gain error in the current range are still affected.

[0048] The DEM module is controlled by Φ1<1:11> and Φ2<1:11>, and the state of the switch controls the 10 times current mirror composed of 10 transistors in PM1. The gate voltage of PM1 is output to the voltage following digital ground module, and the voltage V A In this embodiment, the size of PM2 and PM3 is the same, the size of PMOS PM4 and PM5 is the same, and I1 is equal to I2, that is, the voltage of DGND is equal to V A . Since the size of V SG,PM1 is linearly related to I SET , the voltage of DGND is also linearly related to I SET . The clock frequency division shift module generates clock Φ1<1:11> and 1 / 11 clock Φ2<1:11> with amplitude linearly related to I SET and duty cycle of 10 / 11 and 1 / 11 respectively according to the voltage difference between VSP and DGND. Therefore, when the input current I SET increases, the gate voltage of PM1 in the current amplification module decreases, the voltage of DGND decreases, and the lowest potential of Φ1 decreases, which ensures that V GS is unchanged when K1 is turned on, so that the on-resistance of the switch does not change with the input voltage. Therefore, even if the size of the input current I SET changes, the change of the RC constant of the PM1 gate can be suppressed, so that the amplitude of the glitch changes with the input current, and the direct current component introduced by the glitch becomes more constant, thereby reducing the gain error in the current range.

[0049] In this embodiment, the voltage signal is converted into a current signal, and the influence of mismatch is modulated to high frequency through DEM technology, and is evenly distributed in a period, thereby improving the accuracy of the average output current. This scheme overcomes the influence of process mismatch on the current mirror, and does not need complex matching mode and wiring form, thereby improving the upper limit of the metal line width and the output current. At the same time, the voltage following DGND is designed, so that the on-resistance of the switch does not change with the input current, so that the direct current component introduced by the glitch becomes more constant, thereby reducing the gain error in the current range.

[0050] Embodiment three: the embodiment also provides a DEM-based voltage-current conversion method, applied to the DEM-based voltage-current conversion device in any of the preceding embodiments, and characterized in that it comprises the following steps: S1: the current generation module generates a current I SET ; S2: I SET passes through the DEM module and enters the input current amplification module; S3: the voltage-following digital ground module generates a dynamically adjusted digital ground DGND according to the gate voltage of the transistor in the current amplification module; S4: the clock frequency division shift module generates a clock with a linear relationship with I SET , according to the DGND, to control the DEM module to perform periodic switching; S5: the switch inside the DEM module performs periodic switching based on the clock to perform dynamic element matching, and the transistor in the current amplification module performs amplification on I SET to output I OUT .

[0051] This embodiment converts a voltage signal into a current signal, modulates the influence of mismatch to high frequency through DEM technology, and distributes the influence evenly in a period, thereby improving the precision of the average output current. This scheme overcomes the influence of process mismatch on the current mirror, does not require a complex matching method and wiring form, improves the upper limit of the metal line width and the output current, and designs a voltage-following DGND, so that the on-resistance of the switch does not change with the input current, and therefore, the DC component introduced by the glitch becomes more constant, thereby reducing the gain error in the current range.

[0052] Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art can modify the technical solutions described in the foregoing embodiments, or make equivalent replacements to some of the technical features, as long as the modifications, equivalent replacements, improvements, etc. are within the spirit and principles of the present application, which should be included in the protection scope of the present application.< / k> < / k> < / k>

Claims

1. A voltage-current conversion device based on DEM, characterized in that: The current generating module includes a current generating module, which generates a current I SET , I SET After passing through the DEM module, input into the current amplification module; The current amplification module includes several PMOS transistors; the voltage-following digital ground module generates a dynamically adjusted digital ground DGND according to the gate voltage of the transistors in the current amplification module; The clock frequency division and shift module generates amplitude and I according to DGND SET A linear clock controls the DEM module to perform periodic switching. The switch tube inside the DEM module performs periodic switching based on the clock, performs dynamic component matching, and periodically switches the transistor pair I in the current amplifier module. SET Amplify and output I OUT .

2. The voltage-current conversion device based on DEM according to claim 1, characterized in that: The current amplification module includes a PMOS transistor group PM1 composed of n+1 PMOS transistors; the gate of each PMOS transistor in PM1 serves as an I SET The source of PM1 is connected to the positive power supply voltage VSP; PM1 is controlled by the DEM module, and one of the PMOS transistors is switched to a diode connection in sequence during one cycle, and the remaining PMOS transistors form a current amplifier to amplify the current by n times.

3. The voltage-current conversion device based on DEM according to claim 2, characterized in that: The DEM module includes two groups of PMOS switch tubes K1 and K2. The clock frequency division and shifting module includes clocks Φ1 and Φ2. Clocks Φ1 and Φ2 control the PMOS switch tubes in K1 and K2 to perform periodic switching. The number of PMOS switches in K1 and K2 is the same as the number of PMOS transistors in PM1, and the PMOS switches in K1 and K2 are connected to the PMOS transistors in PM1 one by one. The source of each PMOS switch in K1 is connected to the gate of the corresponding PMOS transistor in PM1, and the drain of each PMOS switch in K1 is connected to the drain of the corresponding PMOS transistor in PM1; the source of each PMOS switch in K2 is connected to the drain of the corresponding PMOS transistor in PM1, and the drain of each PMOS switch in K2 serves as I OUT output terminal.

4. The voltage-current conversion device based on DEM according to claim 2, characterized in that: The voltage-following digital ground module includes three grounding branches connected in parallel to the positive power supply voltage VSP; the first branch includes an NMOS transistor NM1, a resistor R1, a PMOS transistor PM2 and a current source I1 connected in series in sequence; the drain of NM1 is connected to the positive voltage VSP, the gate is connected to the gate of the PMOS transistor in PM1, and the source is connected to one end of R1; the source of PM2 is connected to the other end of R1, the drain is connected to one end of the current source I1, the other end of I1 is grounded, and the gate and drain of PM2 are short-circuited; the second branch includes a PMOS transistor PM4 and PM3; the source of PM4 is connected to the positive voltage VSP, and the drain is connected to the source of PM3; the gate of PM3 is connected to the gate of PM2, and the drain is grounded. At the same time, the source of PM3 is connected to the clock division and shifting module as the output end of the digital ground DGND; the third branch includes a PMOS tube PM5 and a current source I2; the source of PM5 is connected to the positive voltage VSP, the gate is connected to the gate of PM4, and the gate of PM5 is short-circuited with the drain of PM5 itself; the drain of PM5 is connected to one end of the current source I2, and the other end of I2 is grounded.

5. The voltage-current conversion device based on DEM according to claim 1 or 4, characterized in that: DGND voltage and I SET The clock frequency division and shift module generates an amplitude and I SET Clock Φ1 and clock Φ2 have a linear relationship and complementary duty cycles.

6. The voltage-current conversion device based on DEM according to claim 5, characterized in that: Input current I SET When the input voltage increases, the gate voltage of the PMOS transistor group in the current amplifier module decreases, the DGND voltage decreases, and the lowest potential of Φ1 decreases, ensuring that the gate-source voltage of the DEM module switch tube group remains unchanged when it is turned on, so that the on-resistance does not change with the input voltage, thereby suppressing the change of the RC constant of the gate of the PMOS transistor group and reducing the amplitude of the glitch generated by the switching of the DEM module with the change of the input current.

7. The voltage-current conversion device based on DEM according to claim 3, characterized in that: A variable k is provided in the clock frequency division and shift module, and k is cyclically incremented from 1 to n+1 in one cycle. In one cycle, the clock frequency division and shift module controls the kth switch tube in the DEM module switch tube group K1 through the variable k to be turned on and the others to be turned off, and the kth switch tube in the switch tube group K2 to be turned off and the others to be turned on, so as to control the kth transistor in PM1 to switch to a diode connection.

8. The voltage-current conversion device based on DEM according to claim 4, characterized in that: The PMOS transistors PM2 and PM3 have the same size, and the PMOS transistors PM4 and PM5 have the same size.

9. The voltage-current conversion device based on DEM according to claim 1, characterized in that: The current generation module includes an operational amplifier, an NMOS tube NM0 and a resistor R SET , the non-inverting input terminal of the operational amplifier is used as the voltage signal V VIN The input end, operational amplifier and NMOS tube NM0 form a unity gain negative feedback.

10. A voltage-current conversion method based on DEM, applied to the voltage-current conversion device based on DEM according to any one of claims 1 to 9, characterized in that: The following steps are involved: The current generation module generates current I SET ; I SET After passing through the DEM module, input into the current amplification module; The voltage-following digital ground module generates a dynamically adjusted digital ground DGND according to the gate voltage of the transistor in the current amplifier module; The clock frequency division and shift module generates amplitude and I according to DGND SET A linear clock controls the DEM module to perform periodic switching. The switch tube inside the DEM module performs periodic switching based on the clock, performs dynamic component matching, and periodically switches the transistor pair I in the current amplifier module. SET Amplify and output I OUT .

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