Efficient flash memory management method, device and equipment based on table look-up algorithm

Abstract

The invention relates to a high-efficiency flash memory management method, device and equipment based on a table look-up algorithm, and the method comprises the steps: mapping a write cache programming command issued by a chip bus step by step through three configured lookup tables, indexing a corresponding programming group in a table look-up mode in a programming execution process, indexing back to a corresponding programming address and programming data through the programming group, and carrying out the programming operation through the corresponding programming address and programming data. According to the method, the programming time of the same cache size is reduced to 2 / 3 of that of a traditional scheme, so that the whole write cache programming process of the flash memory is accelerated, more efficient write management operation on the high-capacity flash memory is realized, the write time is saved while chip resources are saved, and the overall performance of the flash memory is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer data access, and relates to a high-efficiency flash memory management method, device and equipment based on a lookup table algorithm. BACKGROUND

[0002] Flash memory is an important non-volatile memory. With the rapid development of artificial intelligence applications, the demand for flash memory is rapidly increasing, which puts forward higher requirements for flash memory in the era of artificial intelligence. Not only does flash memory need to have a larger storage space, but also needs to have a faster read-write speed. Therefore, it is necessary to develop a more efficient flash memory read-write management method to improve the overall performance of flash memory. However, in the traditional flash memory read-write management method, the common management method is based on a flash translation layer (FTL). The FTL is responsible for mapping the logical address of the host to the physical address of the flash memory, and performs operations such as wear leveling and garbage collection. There is also a management method represented by SPI flash memory, which sends a write command through an SPI bus, writes data into a cache area first, and then writes it into the actual storage location. However, these traditional methods have deficiencies in overall performance: the garbage collection process of FTL can cause write amplification, increase the amount of actual data written, and reduce write performance; the cache management mechanism of SPI flash memory is complex in maintaining consistency between the cache and the actual storage, and is prone to cache data loss due to unexpected power failure, which is difficult to meet the stringent performance requirements of large capacity and high read-write speed of flash memory in the era of artificial intelligence. SUMMARY

[0003] In view of the problems in the above-mentioned traditional technology, the present application provides a high-efficiency flash memory management method based on a lookup table algorithm, a high-efficiency flash memory management device based on a lookup table algorithm, and a computer device, which can more efficiently manage large-capacity flash memory, save chip resources and write time, and improve the overall performance of flash memory.

[0004] To achieve the above-mentioned purpose, the embodiments of the present application adopt the following technical solutions: On the one hand, a high-efficiency flash memory management method based on a lookup table algorithm is provided, comprising the steps of: obtaining a write cache programming command issued by a chip bus; mapping programming data to be written into flash memory to a lookup table one according to the programming address of the write cache programming command; the lookup table one is used to map the write cache programming command to the real storage space of the flash memory; mapping the programming data in the lookup table one that needs to be programmed into the real storage body of the flash memory to a programming group in a lookup table two; the lookup table two is used to map the data that needs to be programmed into the real storage space to the programming group; Mapping the programming group in the lookup table 2 to the programming group index to be programmed in the lookup table 3; the lookup table 3 is used to index the programming address and data during the programming process; Look up the table in lookup table 3 according to the programming number of the write cache programming command, index the programming group in lookup table 2 through the matching programming operation information, and then index the programming address and programming data in lookup table 1 according to the hit programming group; The hit program data is programmed in parallel to the corresponding real memory bank according to the hit program address.

[0005] On the other hand, an efficient flash memory management device based on a table lookup algorithm is also provided, comprising: A command acquisition module is used to obtain write cache programming commands issued by the chip bus; A command mapping module is used to map the programming data to be written into the flash memory to a first lookup table according to the programming address of the write cache programming command; the first lookup table is used to map the write cache programming command to the real storage space of the flash memory; A programming group mapping module is used to map the programming data in the lookup table 1 that needs to be programmed into the real storage volume of the flash memory to the programming group in the lookup table 2; the lookup table 2 is used to map the data that needs to be programmed into the real storage space into the programming group; A programming index mapping module is used to map the programming group in the lookup table 2 to the programming group index to be programmed in the lookup table 3; the lookup table 3 is used to index the programming address and data during the programming process; A table lookup index module is used to look up the table in lookup table 3 according to the programming number of the write cache programming command, index the programming group in lookup table 2 through the matching programming operation information, and then index the programming address and programming data in lookup table 1 according to the hit programming group; The write programming module is used to program the hit programming data into the corresponding real storage body in parallel according to the hit programming address.

[0006] On the other hand, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned efficient flash memory management method based on the table lookup algorithm are implemented.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The high-efficiency flash memory management method, device and equipment based on the table lookup algorithm, through the three configured lookup tables, maps the write cache programming commands issued by the chip bus step by step, indexes the corresponding programming group in the programming process in the form of table lookup, uses the programming group index to return the corresponding programming address and programming data, reduces the programming time of the same cache size to 2 / 3 of the traditional scheme, thereby accelerating the entire write cache programming process of the flash memory, realizing more efficient write management operation on the large-capacity flash memory, saving the chip resources and write time, and improving the overall performance of the flash memory. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0009] Figure 1 A flowchart of the high-efficiency flash memory management method based on the table lookup algorithm in an embodiment; Figure 2 A flowchart of the write cache programming algorithm in an embodiment; Figure 3 A mapping diagram of the WB_C2M_LUT lookup table in an embodiment; Figure 4 A mapping diagram of the WB_M2G_LUT lookup table in an embodiment; Figure 5 A mapping diagram of the WB_T2P_LUT lookup table in an embodiment; Figure 6 A diagram of the programming process lookup table index in an embodiment; Figure 7 A flowchart of the multi-sector erase algorithm in an embodiment; Figure 8 A mapping diagram of the SERS_EN_LUT lookup table in an embodiment; Figure 9 A diagram of the SERS_ADDR_P pointer update in an embodiment; Figure 10 A diagram of the multi-sector erase address index in an embodiment; Figure 11 A module block diagram of the high-efficiency flash memory management device based on the table lookup algorithm in an embodiment. DETAILED DESCRIPTION

[0010] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application.

[0011] It should be noted that the term "embodiment" mentioned herein means that the specific features, structures or characteristics described in conjunction with the embodiment can be included in at least one embodiment of the present application. The phrase is shown at various places in the specification does not necessarily refer to the same embodiment, nor is it independent or alternative to other embodiments. Those skilled in the art can understand that the embodiments described herein can be combined with other embodiments. The term "and / or" used herein refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0013] In one embodiment, as shown in Figure 1 a high-efficiency flash memory management method based on a lookup table algorithm can include the following steps S10 to S20: S10, obtaining a write cache programming command issued by a chip bus; S12, mapping programming data to be written into a flash memory to a lookup table one according to a programming address of the write cache programming command; the lookup table one is used to map the write cache programming command to a real storage space of the flash memory; S14, mapping programming data in the lookup table one that needs to be programmed to a real storage bank in the flash memory to a programming group in a lookup table two; the lookup table two is used to map data that needs to be programmed to the real storage space to the programming group; S16, mapping the programming group in the lookup table two to a programming group index that needs to be programmed in a lookup table three; the lookup table three is used to index a programming address and data during programming; S18, according to the number of programming times of the write cache programming command, looking up the lookup table three, and then according to the matching programming operation information, indexing the programming group in the lookup table two, and according to the hit programming group index, indexing the programming address and the programming data in the lookup table one; S20, according to the hit programming address, programming the hit programming data to the corresponding real storage bank in parallel.

[0014] It can be understood that, when the NOR flash chip is performing write buffer programming (for example, 32 bits, and the same applies to other bit lengths), the entire write buffer programming process of the flash is accelerated by three configured lookup tables. The first lookup table is used to map the write buffer programming command issued by the chip bus to the real storage space of the flash; the second lookup table is used to map the data to be programmed to the real storage space into programming groups according to the requirements (for example, the requirement for parallel programming, if 4 memory banks are required to be programmed in parallel, then the data is grouped into 4); and the third lookup table is used to index the programming address and data during programming. When the flash chip is performing write buffer programming of the real storage space, the three lookup tables are retrieved to shorten the data arrangement time, and the programming time is reduced by using the programming groups. Based on this, the write buffer programming algorithm flow can be as shown in Figure 2 .

[0015] It should be noted that the purpose of the lookup table is mainly to change the traditional single memory bank programming mode to multi-memory bank parallel programming, so that the programming time of the same size storage space can be greatly reduced. In addition, the operation of the lookup table can be performed in parallel, and the time consumption is less, compared with the reduction of the programming time, the time consumption of the lookup table is small enough to be ignored, therefore, the new two-stage processing logic design is adopted as follows: the command stage is “command >> lookup table one >> lookup table two >> lookup table three”, and the programming stage is “lookup table three >> lookup table two >> lookup table one”.

[0016] Specifically, when the chip bus issues the write buffer programming command, the corresponding programming data is mapped into the lookup table one (denoted as WB_C2M_LUT lookup table) according to the programming address of the write buffer programming command, as shown in Figure 3 . Taking the memory bank of 32 bit width and the chip bus of 16 bit width as an example (in order to align the bit width, two 16 bit command data need to be saved in one lookup table address), the write buffer programming command of the chip bus maps the carried programming data into the WB_C2M_LUT lookup table according to the carried programming address, and sets the to-be-programmed flag of the highest bit of the corresponding real storage space in the WB_C2M_LUT lookup table to 1 (to inform the subsequent lookup table to avoid repeated saving).

[0017] Then, the lookup table two (which can be denoted as WB_M2G_LUT lookup table) maps the programming data to be programmed to the real storage space into programming groups according to the information in the WB_C2M_LUT lookup table, as shown in Figure 4 . Taking the four groups of real memory banks of the flash to be programmed simultaneously as an example, the corresponding programming data to be programmed to the real memory bank is mapped into the programming group in the WB_M2G_LUT lookup table, and the to-be-programmed flag of the highest bit of the real memory bank is set to 1 according to the mapping relationship.

[0018] The programming data is mapped to the programming group index (e.g., the WB_M2G_LUT index) to be programmed in the lookup table three (which can be referred to as the WB_T2P_LUT lookup table) according to the programming group in the WB_M2G_LUT lookup table, for example Figure 5 As shown in the figure, the index with the high four bits not being 0 in the WB_M2G_LUT lookup table is mapped to the WB_T2P_LUT lookup table, and the programming times are added by one at the same time.

[0019] When performing programming, first, the index in the WB_T2P_LUT lookup table is started according to the programming times indicated by the write cache programming command, the programming group corresponding to the programming times is obtained from the WB_M2G_LUT lookup table, and finally the real programming address and programming data are obtained from the WB_C2M_LUT lookup table according to the programming group index hit by the lookup table, and the simultaneous writing programming of the four groups of real memory banks is performed. The flow of the lookup table index in the programming process is shown in Figure 6 .

[0020] The above efficient flash memory management method based on the lookup table algorithm maps the write cache programming command issued by the chip bus through the three configured lookup tables in stages, indexes the corresponding programming group in the lookup table during the execution of the programming, and uses the programming group index to return the corresponding programming address and programming data, so that the programming time of the same cache size is reduced to 2 / 3 of the traditional scheme, thereby accelerating the entire write cache programming process of the flash memory, realizing more efficient write management operation on the large-capacity flash memory, saving the chip resources and write time, and improving the overall performance of the flash memory.

[0021] In one embodiment, the above efficient flash memory management method based on the lookup table algorithm can further include the following steps: Obtaining the multi-sector erase command issued by the chip bus; Setting the valid bit in the lookup table A to 1 according to the sector address in the multi-sector erase command; the valid bit is used as the erase sector address index; Updating the dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is the invalid pointer 2048; Starting from the starting address of the dynamic pointer P, performing the erase according to the erase times indicated by the multi-sector erase command; When the updated erase sector address in the lookup table A is smaller than the value of the current dynamic pointer P, updating the value of the dynamic pointer P to the next valid erase sector address index in the lookup table A; When the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A, the sector erase is ended.

[0022] It can be understood that, when the NOR flash chip performs multi-sector erase, the embodiment reduces the chip resource usage amount during the execution of the multi-sector erase command by configuring a lookup table A and a dynamic pointer mechanism, as shown in Figure 7 The lookup table A is used to record the sectors that need to be erased in the multi-sector erase process, and the dynamic pointer P is set to dynamically find the sector address corresponding to the sector that needs to be erased according to the lookup table A when the real erase is performed. When the NOR flash chip performs real storage space erase, the lookup table A guides the jumping of the dynamic pointer P to obtain the sector address required for real erase, thereby reducing the usage amount of chip resources in the multi-sector erase process.

[0023] Specifically, when multi-sector erase of the flash memory needs to be processed, the chip bus sets the valid bit in the lookup table A (which can be denoted as SERS_EN_LUT lookup table) to 1 according to the sector address in the multi-sector erase command when issuing the multi-sector erase command, and the valid bit is used as an erase sector address index. As shown in Figure 8 Taking a 2G bit flash chip as an example, the SERS_EN_LUT lookup table updates the valid bit according to the received valid multi-sector erase command.

[0024] At the same time of updating the SERS_EN_LUT lookup table, the dynamic pointer P (which can be denoted as SERS_ADDR_P pointer) is also updated synchronously according to the data in the SERS_EN_LUT lookup table. As shown in Figure 9 The initial value of the SERS_ADDR_P pointer is an invalid pointer 2048, and the SERS_ADDR_P pointer is updated when the updated erase sector address in the SERS_EN_LUT lookup table is less than the value of the current SERS_ADDR_P pointer.

[0025] When performing erase, the erase starts from the starting address of the SERS_ADDR_P pointer according to the erase times indicated by the multi-sector erase command, and in the process of erase, when the SERS_ADDR_P pointer finds the next valid erase address, if the next valid erase address is found, the SERS_ADDR_P pointer stops at the valid erase sector address index in the SERS_EN_LUT lookup table, so as to erase the next sector, as shown in Figure 10 .

[0026] When performing multi-sector erase, the embodiment saves the chip resources required for multi-sector erase of the flash memory by means of the lookup table and dynamic pointer mechanism, and reduces the chip resources used in multi-sector erase by 90% (taking a 2G bit flash chip as an example). For example, normal sector erase needs to save multiple erase sector addresses, if there are 100 sector addresses occupying 10 bits, the conventional method needs to save 100 10=1000bit, the high-efficiency flash memory management method based on the table lookup algorithm adopts a pointer mode, only needs a 10-bit pointer and a 100-bit SERS_EN_LUT lookup table, and only needs 100+10=110 bits, thereby greatly saving resources and significantly improving the write performance of the flash memory chip and making the flash memory chip have higher performance and lower power consumption.

[0027] It should be understood that, although the above flow Figure 1 shows the steps in sequence according to the arrows, the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps has no strict order limitation, and the steps can be executed in other orders. Moreover, at least part of the steps of the above flow Figure 1 may include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of the sub-steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or sub-steps or stages of other steps.

[0028] In one embodiment, as Figure 11 shown, a high-efficiency flash memory management device based on a table lookup algorithm is also provided, which includes a command acquisition module 11, a command mapping module 13, a programming group mapping module 15, a programming index mapping module 17, a table lookup index module 19, and a write programming module 21. The command acquisition module 11 is configured to acquire a write cache programming command issued by a chip bus. The command mapping module 13 is configured to map programming data to be written into a flash memory to a lookup table one according to a programming address of the write cache programming command. The lookup table one is configured to map the write cache programming command to a real storage space of the flash memory. The programming group mapping module 15 is configured to map programming data in the lookup table one that needs to be programmed to a real storage bank of the flash memory to a programming group in a lookup table two. The lookup table two is configured to map data that needs to be programmed to the real storage space to the programming group. The programming index mapping module 17 is configured to map the programming group in the lookup table two to a programming group index that needs to be programmed in a lookup table three. The lookup table three is configured to index a programming address and data during programming. The table lookup index module 19 is configured to perform table lookup in the lookup table three according to a programming number of the write cache programming command, index the programming group in the lookup table two through matching programming operation information, and index the programming address and the programming data in the lookup table one according to the hit programming group index. The write programming module 21 is configured to program the hit programming data to the corresponding real storage bank according to the hit programming address.

[0029] The high-efficiency flash memory management device based on the table lookup algorithm reduces the programming time of the same cache size to 2 / 3 of the traditional scheme by mapping the write cache programming command issued by the chip bus through the three configured lookup tables, indexing the corresponding programming group in the table lookup manner in the programming process, and using the programming group index to return the corresponding programming address and programming data, thereby accelerating the entire write cache programming process of the flash memory, realizing more efficient write management operation on the large-capacity flash memory, saving chip resources and write time, and improving the overall performance of the flash memory.

[0030] In one embodiment, the command acquisition module 11 is also configured to acquire a multi-sector erase command issued by the chip bus; the high-efficiency flash memory management device based on the table lookup algorithm can further include: an erase mapping module configured to set the valid bit in the lookup table A to 1 according to the sector address in the multi-sector erase command; the valid bit is used as an erase sector address index. A pointer updating module configured to update the dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is the invalid pointer 2048. A sector erasing module configured to perform erasing from the starting address of the dynamic pointer P according to the number of erasing indicated by the multi-sector erase command. Wherein, when the updated erase sector address in the lookup table A is smaller than the value of the current dynamic pointer P, the pointer updating module updates the value of the dynamic pointer P to the next valid erase sector address index in the lookup table A; when the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A, the sector erasing ends.

[0031] It can be understood that the explanations and descriptions of the features of the above-mentioned high-efficiency flash memory management device based on the table lookup algorithm can be understood in the same way by referring to the corresponding explanations and descriptions in the above-mentioned embodiments of the high-efficiency flash memory management method based on the table lookup algorithm. Each module in the above-mentioned high-efficiency flash memory management device based on the table lookup algorithm can be realized by software, hardware and their combinations in whole or in part. The above-mentioned components can be embedded in or independent of a device with data processing function in hardware form, or stored in the memory of the aforementioned device in software form, so as to be called and executed by the processor to perform the operations corresponding to each module. The aforementioned device can be, but is not limited to, various types of computers in the prior art.

[0032] In one embodiment, a computer device is also provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following processing steps when executing the computer program: obtaining a write cache programming command issued by a chip bus; mapping programming data to be written into a flash memory to a lookup table one according to a programming address of the write cache programming command; the lookup table one is used to map the write cache programming command to a real storage space of the flash memory; mapping programming data in the lookup table one that needs to be programmed to a real storage bank of the flash memory to a programming group in a lookup table two; the lookup table two is used to map data that needs to be programmed to the real storage space to the programming group; mapping the programming group in the lookup table two to a programming group index that needs to be programmed in a lookup table three; the lookup table three is used to index a programming address and data during programming; according to the programming times of the write cache programming command, looking up the lookup table three, and after indexing the programming group in the lookup table two through matching programming operation information, according to the hit programming group index, the programming address and the programming data in the lookup table one; and according to the hit programming address, programming the hit programming data to the corresponding real storage bank in parallel.

[0033] In one embodiment, the processor, when executing the computer program, can also implement the steps or sub-steps added in each embodiment of the above-mentioned high-efficiency flash memory management method based on the lookup table algorithm.

[0034] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. Any reference to memory, storage, database or other medium used in each embodiment of the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (Rambus DRAM, RDRAM for short) and interface dynamic random access memory (DRDRAM) and the like.

[0035] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, any combination of the technical features is deemed to be within the scope of the present disclosure.

[0036] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and all of them belong to the protection scope of the present application.

Claims

1. An efficient flash memory management method based on a table lookup algorithm, characterized in that: Including steps: Get the write cache programming command issued by the chip bus; Mapping the programming data to be written into the flash memory to a first lookup table according to the programming address of the write cache programming command; the first lookup table is used to map the write cache programming command to the real storage space of the flash memory; Mapping the programming data in the lookup table 1 that needs to be programmed into the real storage volume of the flash memory to the programming group in the lookup table 2; the lookup table 2 is used to map the data that needs to be programmed into the real storage space to the programming group; Map the programming group in the lookup table 2 to the programming group index that needs to be programmed in the lookup table 3; Lookup table three is used to index programming addresses and data during programming; Look up the table in lookup table 3 according to the programming number of the write cache programming command, index the programming group in lookup table 2 through the matching programming operation information, and then index the programming address and programming data in lookup table 1 according to the hit programming group; The hit program data is programmed in parallel to the corresponding real memory bank according to the hit program address.

2. The efficient flash memory management method based on table lookup algorithm according to claim 1, characterized in that: Also includes the steps: Get the multi-sector erase command sent by the chip bus; According to the sector address in the multi-sector erase command, the valid bit in the lookup table A is set to 1; the valid bit is used as the erase sector address index; According to the sector address in the multi-sector erase command, the dynamic pointer P is updated so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is an invalid pointer 2048; According to the erase times indicated by the multi-sector erase command, erase starts from the starting address of the dynamic pointer P; When the erased sector address updated in the lookup table A is less than the current value of the dynamic pointer P, the value of the dynamic pointer P is updated to the next valid erased sector address index in the lookup table A; When the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A, the sector erase ends.

3. An efficient flash memory management device based on a table lookup algorithm, characterized in that: include: A command acquisition module is used to obtain write cache programming commands issued by the chip bus; A command mapping module is used to map the programming data to be written into the flash memory to a first lookup table according to the programming address of the write cache programming command; the first lookup table is used to map the write cache programming command to the real storage space of the flash memory; A programming group mapping module is used to map the programming data in the lookup table 1 that needs to be programmed into the real storage volume of the flash memory to the programming group in the lookup table 2; the lookup table 2 is used to map the data that needs to be programmed into the real storage space into the programming group; A programming index mapping module is used to map the programming group in the lookup table 2 to the programming group index to be programmed in the lookup table 3; the lookup table 3 is used to index the programming address and data during the programming process; A table lookup index module is used to look up the table in lookup table 3 according to the programming number of the write cache programming command, index the programming group in lookup table 2 through the matching programming operation information, and then index the programming address and programming data in lookup table 1 according to the hit programming group; The write programming module is used to program the hit programming data into the corresponding real storage body in parallel according to the hit programming address.

4. The efficient flash memory management device based on table lookup algorithm according to claim 3, characterized in that: The command acquisition module is also used to obtain the multi-sector erase command issued by the chip bus; The efficient flash memory management device also includes: The erase mapping module is used to set the valid bit in the lookup table A to 1 according to the sector address in the multi-sector erase command; the valid bit is used as the erase sector address index; The pointer update module is used to update the dynamic pointer P according to the sector address in the multi-sector erase command, so that the dynamic pointer P always points to the smallest sector address in the multi-sector erase command; the initial value of the dynamic pointer P is an invalid pointer 2048; The sector erase module is used to erase from the starting address of the dynamic pointer P according to the number of erase times indicated by the multi-sector erase command; wherein, when the erase sector address updated in the lookup table A is less than the current value of the dynamic pointer P, the pointer update module updates the value of the dynamic pointer P to the next valid erase sector address index in the lookup table A; when the dynamic pointer P cannot find the next valid erase sector address index in the lookup table A, the sector erase is completed.

5. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the efficient flash memory management method based on the table lookup algorithm as claimed in claim 1 or 2 are implemented.

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