Storage system and storage system cluster

Abstract

The application provides a storage system and a storage system cluster, which can be applied to the fields of servers and storage technologies. The storage system comprises a plurality of control nodes and at least one interconnection device, wherein the interconnection device comprises a first switching module and a memory module, the first switching module is electrically connected with the plurality of control nodes respectively and is electrically connected with the memory module, and the first switching modules of the at least one interconnection device are connected with each other; wherein the first switching module is used for writing first cache data provided by the control nodes into the memory module, or is used for providing second cache data stored in the memory module to the control nodes, so that the plurality of control nodes realize cache sharing through the at least one interconnection device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers and storage, and more particularly to a storage system and a storage system cluster. BACKGROUND

[0002] In the digital era of explosive data growth, the performance, reliability and scalability requirements of storage systems as the core infrastructure for data bearing and management continue to rise. Current mainstream high-end storage devices have formed a multi-controller networking architecture. Common two-controller and four-controller solutions can achieve system deployment through topologies such as 'one frame two controllers', 'one frame four controllers', and 'two frames four controllers' to meet the concurrent access and load balancing requirements in large-scale data processing scenarios.

[0003] To realize data sharing and collaborative work among multiple controllers, related technologies mainly use NTB (Non-Transparent Bridge) or ROCE (Remote Direct Memory Access Over Converged Ethernet) solutions to build interconnection links. However, the solutions based on NTB or ROCE have performance splicing and cannot meet the comprehensive needs of new-generation storage systems for high-performance interconnection, centralized caching, and low-cost backup power. SUMMARY

[0004] Therefore, the present application provides a storage system and a storage system cluster.

[0005] One aspect of the present application provides a storage system, comprising: a plurality of control nodes; and at least one interconnection device, the interconnection device comprising a first switching module and a memory module, the first switching module being electrically connected to the plurality of control nodes respectively and being electrically connected to the memory module, the first switching modules of at least one interconnection device being connected to each other; wherein the first switching module is configured to write first cache data provided by the control nodes to the memory module, or to provide second cache data stored in the memory module to the control nodes, so that the plurality of control nodes realize cache sharing through at least one interconnection device.

[0006] Another aspect of the present application provides a storage system cluster, comprising at least two storage systems as described above. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other objects, features and advantages of the present application will become more apparent from the following description of the preferred embodiments of the present application taken with reference to the accompanying drawings, in which:

[0008] Figure 1AA schematic diagram of an example controller node is shown.

[0009] Figure 1B A schematic diagram of an example four-control shared storage architecture implemented based on ROCE is shown.

[0010] Figure 2 A schematic diagram of a storage system according to an embodiment of the present application is shown.

[0011] Figure 3 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0012] Figure 4 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0013] Figure 5 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0014] Figure 6 A schematic diagram of a data flushing scheme according to an embodiment of the present application is shown.

[0015] Figure 7 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0016] Figure 8A A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0017] Figure 8B A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0018] Figure 9 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0019] Figure 10 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0020] Figure 11 A schematic diagram of a storage system cluster according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, the drawings are for illustration purposes only and should not be taken as limiting the scope of the present application. In the following detailed description of embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, it will be apparent to one skilled in the art that one or more embodiments of the present application can be practiced without these specific details. In other instances, well-known structures and

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the terms "comprises", "comprising", "includes", "including" and the like are specifically intended to be open-ended and to mean that other features, steps, operations, and / or components can be added.

[0023] All terms used herein including technical and scientific terms have the meanings commonly understood by one of ordinary skill in the art unless otherwise specified. It should be noted that the terms "comprise", "comprising", "comprises", "including", "includes" or "contain", "containing", "contains" when used herein, are taken to specify the presence of stated features, steps or components but do not preclude the presence or addition of one or more other features, steps, operations, components or groups thereof.

[0024] In the case of using expressions similar to "at least one of A, B, and C, etc.", it is generally to be interpreted that the meaning is "at least one of A, B, or C" rather than "A or B or C" in the sense that the expression is used in the field of the art.

[0025] In the digital era of explosive data growth, storage systems as the core infrastructure for data bearing and management, the performance, reliability and scalability requirements continue to rise. The current mainstream high-end storage devices have formed a multi-controller networking architecture. Common two-controller and four-controller solutions can achieve system deployment through topologies such as one-frame two-controller, one-frame four-controller, and two-frame four-controller to meet the concurrent access and load balancing requirements in large-scale data processing scenarios. One-frame two-controller means inserting two controllers in one chassis or frame, and one-frame four-controller, two-frame four-controller and the like are similar.

[0026] To realize data sharing and collaborative work among multiple controllers, related technologies mainly use NTB or ROCE solutions to build interconnection links. Taking the ROCE solution as an example, the multi-controller shared storage architecture in related technologies is described below.

[0027] Figure 1A A schematic diagram of an example controller node is shown.

[0028] As Figure 1A shown, a plurality of memories, system disks, central processing units and a plurality of ROCE chips can be provided in the controller node. The central processing units can be connected with the plurality of memories, system disks and the plurality of ROCE chips respectively. The controller node can be used to connect with other controller nodes through the plurality of ROCE chips.

[0029] Figure 1B A schematic diagram of an example four-controller shared storage architecture based on ROCE implementation is shown.

[0030] AsFigure 1B As shown, the four controller nodes can constitute a four-control shared storage architecture with a mesh topology, each controller node can include three ROCE chips, and each ROCE chip of each controller node can be connected with another ROCE chip of another controller node, respectively, to realize interconnection between the four controller nodes.

[0031] However, the four-control shared storage architecture implemented based on ROCE has significant defects. On the one hand, the network topology has high complexity, and each controller node needs to additionally deploy multiple special chips, which not only increases the difficulty of board layout and wiring, but also greatly increases the hardware cost. On the other hand, the link delay problem is prominent. For example, in an example of a four-control shared storage architecture, when using a tool to test the transmission delay, it can be found that when transmitting an 8kb data packet, the maximum delay of the architecture is 5us, when transmitting a 32kb data packet, the maximum delay of the architecture is 8us, and when transmitting a 36kb data packet, the maximum delay of the architecture is 10us. High delay directly restricts the data processing performance of the whole machine, and it is difficult to meet the needs of scenes such as finance and industrial control that have strict real-time requirements.

[0032] At the same time, the cache data security of the storage system is one of the core design indicators. In a multi-controller environment, if a controller node encounters an AC (Alternating Current) power failure, it needs to ensure that the data in its cache that has not been persisted can be written to the data disk in time to avoid data loss. Related solutions generally use the design of independently configuring a BBU (Battery Backup Unit) on each controller node, that is, each controller node is equipped with a dedicated BBU, which provides power to maintain cache operation after power failure until the data is written to the disk. Although this mode can achieve data protection, it has obvious disadvantages, including waste of hardware resources, cost stacking, etc. Specifically, under the multi-controller node architecture, the number of BBUs needs to be configured, which increases the space occupancy rate in the chassis, limits the expansion of other components, and the repeated deployment of BBUs greatly increases the hardware cost of the whole machine, reduces the product performance ratio, and does not meet the trend of the development of storage systems towards high density and low cost.

[0033] To solve the industry pain points such as memory capacity, sharing efficiency and IO (Input / Output) delay, related enterprises have launched CXL (Compute Express Link) technology. As an open industry standard interconnection protocol, CXL technology has the characteristics of low delay, high bandwidth, memory sharing friendly, etc., and can realize seamless connection with peripherals such as FPGA (Field-Programmable Gate Array) and GPU (Graphics Processing Unit), and has significant application potential in the field of servers and storage.

[0034] However, the multi-controller node sharing scheme of the current storage system has not fully utilized the advantages of CXL technology, and is still limited by the performance bottleneck of the traditional NTB / ROCE scheme and the cost problem of BBU configuration, which cannot meet the comprehensive needs of the new generation of storage system for high-performance interconnection, centralized cache and low-cost standby power, and it is urgent to propose an innovative architecture based on CXL technology to break through the related design limitations.

[0035] Therefore, embodiments of the present application propose a cache sharing scheme based on a three-layer architecture of "control node-interconnection device-memory module", which realizes the centralized connection of control nodes and memories and the cascade of multiple interconnection devices through the first switching module of the interconnection device, and solves the complexity, delay and scalability problems of multi-control node cache sharing. Specifically, the embodiments of the present application provide a storage system and a storage system cluster, the storage system comprising: a plurality of control nodes; and at least one interconnection device, the interconnection device comprising a first switching module and a memory module, the first switching module being electrically connected with the plurality of control nodes respectively and being electrically connected with the memory module, the first switching modules of the at least one interconnection device being connected with each other; wherein the first switching module is configured to write first cache data provided by the control node into the memory module, or to provide second cache data stored in the memory module to the control node, so that the plurality of control nodes realize cache sharing through the at least one interconnection device.

[0036] Figure 2 A schematic diagram of a storage system according to an embodiment of the present application is shown.

[0037] As Figure 2 shown, the storage system can include a plurality of control nodes 10 and at least one interconnection device 20.

[0038] The plurality of control nodes 10 can represent a plurality of control ends of the storage system respectively. The control node 10 is a core computing unit responsible for business IO processing, data read-write scheduling and local resource management in the storage system, and is also the initiator and consumer of cache data in the multi-controller sharing scheme.

[0039] The interconnection device 20 can be a Jointly-shared Block / Object-Storage Multi-controller (JBOM). In a storage system, the interconnection device 20 can be a cache resource pooling center and a redundant control center, and is a core hub for implementing a multi-controller sharing solution.

[0040] The interconnection device 20 can include a first switching module 21 and a memory module 22. The first switching module 21 is electrically connected to the plurality of control nodes 10 respectively, and is electrically connected to the memory module 22.

[0041] The first switching module 21 can be a Switch chip supporting the CXL protocol, which can realize high-speed interconnection between the plurality of control nodes 10 and the memory module 22.

[0042] The first switching module 21 can be connected to the control nodes 10 and the memory module 22 through PCIe (Peripheral Component Interconnect Express) links respectively. In an example, each read / write operation of each control node 10 needs to occupy an 8-channel PCIe link, so that the read / write performance of the control node 10 is optimized. Therefore, each control node 10 can be electrically connected to the first switching module 21 through a 16-channel PCIe link.

[0043] The memory module 22 can include a plurality of memory banks supporting the CXL protocol. In an example, the memory bank can adopt a half-duplex design, which is electrically connected to the first switching module 21 through an 8-channel PCIe link. The link between the memory bank and the first switching module 21 only supports read operation or write operation to be performed asynchronously alone, so as to save the PCIe channel resources of the first switching module 21, and more memory banks can be configured in the interconnection device 20.

[0044] The memory module 22 can provide a cache space, which can be logically divided into a cache partition corresponding to each control node 10. The cache data related to each control node 10 can be stored in the cache partition related to the control node 10.

[0045] The plurality of control nodes 10 can realize cache sharing through at least one interconnection device 20.

[0046] When writing the cache data, the control node 10 can provide the first cache data to the first switching module 21, and the first switching module 21 can be configured to write the first cache data provided by the control node 10 into the memory module 22, specifically, the first cache data can be written into the cache partition of the memory module 22 corresponding to the control node 10.

[0047] When reading the cache data, the first switching module 21 can receive the data reading request from the control node 10, and in response to the request, the second cache data can be read from the corresponding cache partition of the memory module 22 and sent to the corresponding control node 10, so as to provide the second cache data stored in the memory module 22 to the control node 10.

[0048] Alternatively, the control node 10 can also access the memory module 22 directly through the first switching module 21 to read and write the cache data. For example, the control node 10 can write the first cache data into the memory module 22 through the first switching module 21 to realize the writing of the first cache data; or the control node 10 can read the second cache data from the memory module 22 through the first switching module 21 to realize the reading of the second cache data, so that the plurality of control nodes 10 can share the cache through the at least one interconnection device 20.

[0049] For the at least one interconnection device 20, the first switching modules 21 of the at least one interconnection device 20 can be connected to each other to realize the interconnection between the at least one first switching module 21, so as to establish a connection path between the at least one memory module 22 to ensure the consistency of the cache data recorded in the at least one memory module 22.

[0050] In the storage system, the at least one interconnection device 20 can back up the cache data by hot backup. For example, taking the number of interconnection devices 20 as n, for any control node 10, the control node 10 can be connected to the first switching modules 21 of the n interconnection devices 20. When the control node 10 generates cache data, the cache data can be copied into n parts, and the control node 10 can send the n parts of cache data to the first switching modules 21 of the n interconnection devices 20, so that the first switching modules 21 can write one part of the cache data into the memory module 22 of the interconnection device 20 to realize the hot backup of the cache data generated by the control node 10 on the n interconnection devices 20.

[0051] Alternatively, in the storage system, the at least one interconnection device 20 can include a master interconnection device and one or more slave interconnection devices, the master interconnection device can store cache data in a hot backup manner, and synchronize the cache data to the one or more slave interconnection devices in a cold backup manner. Taking an example of that there is one master interconnection device and m slave interconnection devices in the at least one interconnection device 20, the plurality of control nodes 10 can be connected to at least the first switching module 21 of the master interconnection device, and the first switching module 21 of the master interconnection device can be connected to the first switching module 21 of the m slave interconnection devices respectively. When the control node 10 generates cache data, the cache data can be sent to at least the first switching module 21 of the master interconnection device, and the cache data can be written into the memory module of the master interconnection device through the first switching module 21, so as to realize the hot backup of the cache data generated by the control node 10 on the master interconnection device. When the master interconnection device meets the cold backup condition, the master interconnection device can synchronize the cache data recorded in the memory module 22 of the master interconnection device to the memory module 22 of the m slave interconnection devices through the connection link between the master interconnection device and the first switching module 21 of the m slave interconnection devices, so as to realize the cold backup of the cache data on the m slave interconnection devices. The cold backup condition can include that the storage system stops working, the master interconnection device does not read and write the cache data within a certain period of time, etc., which is not limited herein.

[0052] According to the embodiment of the application, the plurality of control nodes can be electrically connected to the first switching module in the at least one interconnection device respectively, so that each control node can share the memory module of the at least one interconnection device. By means of the three-layer architecture of the control node-interconnection device-memory module, the centralized connection of the control node and the memory and the multi-interconnection device cascade can be realized through the first switching module of the interconnection device, the cache data can be summarized in the same cache pool for sharing design, which can at least partially solve the complexity, delay and scalability of the cache sharing of the plurality of control nodes, effectively improve the cache sharing efficiency in the multi-control shared storage system, and reduce the read-write delay of the cache data. On the other hand, through the connection link between the first switching modules of the at least one interconnection device, the at least one interconnection device can realize the sharing of data through various backup modes, so as to reduce the loss rate of the cache data and improve the reliability of the storage system.

[0053] The storage system shown in the specific embodiments will be further described below with reference to the accompanying drawings. Figure 2

[0054] ​Optionally, the first processor can be arranged in the interconnection device, and the first processors of the at least one interconnection device are interconnected, so that when the first processor of a single interconnection device is abnormal, the first processors of other interconnection devices can realize backup of the cached data through the interconnection link between the at least one first processor, to ensure the safety of the data.

[0055] Figure 3 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0056] As shown in Figure 3 In the storage system, the interconnection device 20 further comprises a first processor 23, and the first processors 23 of the at least one interconnection device 20 are interconnected.

[0057] The first processor 23 can be a CPU (Central Processing Unit) of the interconnection device 20.

[0058] The first processors 23 of the at least one interconnection device 20 can be interconnected through an NTB, a network or other types of links, which are not limited herein.

[0059] In the storage system, the connection channels between the first switching modules 21 of the at least one interconnection device 20 can be used for cache synchronization and data mirroring in normal working conditions, i.e., the hot backup and cold backup of the cached data as described above. The connection channels between the first processors 23 of the at least one interconnection device 20 can be used for emergency data backup when the interconnection device 20 fails. That is, in the case of failure of one interconnection device, other interconnection devices are used to read the third cached data from the memory module of the failed interconnection device via the first processor of the failed interconnection device, and write the third cached data into the memory module of the other interconnection device.

[0060] For example, three interconnected devices, i.e., interconnected device JBOM1, interconnected device JBOM2 and interconnected device JBOM3, can be provided in the storage system, and the first processor CPU1 of the interconnected device JBOM1, the first processor CPU2 of the interconnected device JBOM2 and the first processor CPU3 of the interconnected device JBOM3 can be connected with each other through the NTB. In an abnormal working condition, the interconnected device JBOM1 fails, and then the first processor CPU2 of the interconnected device JBOM2 can read the cache data from the memory module of the interconnected device JBOM1 through the NTB channel between the first processor CPU2 and the first processor CPU1 of the interconnected device JBOM1, and write the cache data into the memory module of the interconnected device JBOM2 via the first processor CPU1 of the interconnected device JBOM1; similarly, the first processor CPU3 of the interconnected device JBOM3 can read the cache data from the memory module of the interconnected device JBOM1 through the NTB channel between the first processor CPU3 and the first processor CPU1 of the interconnected device JBOM1, and write the cache data into the memory module of the interconnected device JBOM3 via the first processor CPU1 of the interconnected device JBOM1. Thus, the interconnected device JBOM2 and the interconnected device JBOM3 can realize the emergency backup of the data when the interconnected device JBOM1 fails.

[0061] Optionally, the first processor of one interconnected device can detect the working state of the first processor of another interconnected device in real time to determine whether the other interconnected device fails, which is not limited herein.

[0062] According to the embodiment of the present application, the interconnection channel between the first switching modules and the interconnection channel between the first processors in at least one interconnected device can realize the fast backup of the cache data between the at least one interconnected device, which can effectively reduce the data loss rate, improve the fault handling capability of the storage system and improve the security of the cache data.

[0063] Optionally, in the emergency backup scenario of the cache data as described above, the failure of the interconnected device can be represented as the failure of the first processor of the interconnected device, such as power failure of the first processor, shutdown of the first processor, etc. Alternatively, the failure of the interconnected device can also be represented as the abnormality of the power supply of the interconnected device, and in this case, the power supply of the interconnected devices can also be shared.

[0064] Figure 4 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0065] As Figure 4As shown, in the storage system, the interconnection device 20 can further comprise a main power module 24, which can be used to supply power to various components of the interconnection device 20. For example, the main power module 24 can form power channels with the first switching module 21, the memory module 22 and the first processor 23 respectively, through which the main power module 24 can supply power to the first switching module 21, the memory module 22 and the first processor 23 respectively.

[0066] The main power module 24 can be a PSU (Power Supply Unit) of the interconnection device 20.

[0067] Optionally, the main power module 24 can implement multiple power level grades and multiple types of power supply, such as 220V AC, 12V DC, 5V DC and 3.3V DC, without limitation.

[0068] Optionally, the interconnection device 20 can form a power interface, and the power interfaces of at least two interconnection devices 20 can be connected to each other. In the case of abnormal operation of the main power module 24, for example, in the case that the main power module 24 cannot normally provide at least one of 220V AC, 12V DC, 5V DC and 3.3V DC, or the supply voltage of the main power module 24 is low, the first switching module 21, the memory module 22 and the first processor 23 can be in an abnormal working state due to insufficient power supply, causing the interconnection device 20 to malfunction. In the case of malfunction of the interconnection device 20, through the interconnection link between the power interfaces of at least two interconnection devices 20, the main power module 24 of the other interconnection device can serve as a backup power supply for the malfunctioning interconnection device, and supply power to the malfunctioning interconnection device.

[0069] For example, three interconnected devices, i.e., interconnected device JBOM1, interconnected device JBOM2 and interconnected device JBOM3, can be provided in the storage system, and the main power module PSU1 of the interconnected device JBOM1, the main power module PSU2 of the interconnected device JBOM2 and the main power module PSU3 of the interconnected device JBOM3 can be interconnected through the power supply interfaces of the interconnected device JBOM1, the interconnected device JBOM2 and the interconnected device JBOM3. In an abnormal working condition, the main power module PSU1 of the interconnected device JBOM1 cannot provide 220V AC power, so that the first switching module, the memory module, the first processor and the like in the interconnected device JBOM1 are powered off. The first processor of the interconnected device JBOM2 can detect the power supply abnormality of the interconnected device JBOM1, and control the main power module PSU2 of the interconnected device JBOM2 to serve as a backup power supply of the interconnected device JBOM1 through the power supply path between the main power module PSU2 of the interconnected device JBOM2 and the main power module PSU1 of the interconnected device JBOM1, to supply power to the first switching module, the memory module, the first processor and the like in the interconnected device JBOM1. Similarly, the first processor of the interconnected device JBOM3 can detect the power supply abnormality of the interconnected device JBOM1, and control the main power module PSU3 of the interconnected device JBOM3 to serve as a backup power supply of the interconnected device JBOM1 through the power supply path between the main power module PSU3 of the interconnected device JBOM3 and the main power module PSU1 of the interconnected device JBOM1, to supply power to the first switching module, the memory module, the first processor and the like in the interconnected device JBOM1.

[0070] During the period when the interconnected device JBOM2 and the interconnected device JBOM3 provide backup power for the interconnected device JBOM1, the interconnected device JBOM2 and the interconnected device JBOM3 can write the cache data recorded in the interconnected device JBOM1 into the memory modules of the interconnected device JBOM2 and the interconnected device JBOM3, respectively, to realize backup of the cache data, thereby effectively improving the security of the cache data.

[0071] In some embodiments, a backup power module can be provided in the interconnected device, which can be used to provide backup power for the interconnected device, i.e., in the case that the main power module of the interconnected device works abnormally due to power failure or the like, the backup power module can supply power to the first switching module, the memory module, the first processor and the like of the interconnected device.

[0072] Figure 5 A schematic diagram of a storage system according to another embodiment of the application is shown.

[0073] As Figure 5As shown, in the storage system, the interconnection device 20 can further comprise a backup power module 25, which can be used to supply power to various components of the interconnection device 20. For example, the backup power module 25 can form a power channel with the first switching module 21, the memory module 22 and the first processor 23 respectively, through which the main power module 24 can supply power to the first switching module 21, the memory module 22 and the first processor 23 respectively.

[0074] The backup power module 25 can be a BBU of the interconnection device 20.

[0075] Similar to the main power module 24, the backup power module 25 can also implement multiple power level grades and multiple types of power supply, such as 220V AC, 12V DC, 5V DC and 3.3V DC, which are not limited herein. Compared with the main power module 24, the backup power module 25 can accommodate less power.

[0076] Optionally, the power channels through which the backup power module 25 and the main power module 24 supply power to various components of the interconnection device 20 can be independent of each other; or, the backup power module 25 and the main power module 24 can multiplex the power channels through which they supply power to various components of the interconnection device 20, i.e., the backup power module 25 and the main power module 24 can supply power to various components of the interconnection device 20 through the same power channel, which is not limited herein.

[0077] Optionally, the backup power module 25 and the main power module 24 can form an interlocking circuit, in which the backup power module 25 does not output power when the main power module 24 normally outputs power, and vice versa.

[0078] Optionally, in the case of further comprising a backup power module in the interconnection device, when the main power module of an interconnection device fails, the backup power implementation of the interconnection device can be not limited. For example, the backup power module of the interconnection device can be used to preferentially back up the interconnection device; for another example, the main power module of another interconnection device can be used to preferentially back up the interconnection device; for another example, the backup power module of the interconnection device and the main power module of another interconnection device can simultaneously back up the interconnection device, and so on.

[0079] According to the embodiment of the present application, by setting the main power module and the standby power module in the interconnected device, and using the standby power module of the interconnected device and / or the main power module of other interconnected device to provide backup power for the interconnected device when the main power module of the interconnected device is abnormal, the multiple backup power setting of the interconnected device can be realized, thereby effectively improving the working stability of the interconnected device, reducing the loss probability of the cache data not stored persistently in the interconnected device, and ensuring the security of the cache data.

[0080] Optionally, in order to further improve the security of the cache data, when the interconnected device triggers the backup power event, the interconnected device can also perform the disk writing processing on the cache data, so as to realize the persistent processing on the cache data in the memory module.

[0081] Figure 6 A schematic diagram of a data disk writing scheme according to an embodiment of the present application is shown.

[0082] As shown in Figure 6 The interconnected device can also be provided with a storage module 26, which can be electrically connected with the first processor 23, and the storage module 26 can be used to store the cache data.

[0083] The storage module 26 can be any type of non-volatile memory, such as a solid state disk, a mechanical hard disk, etc., which is not limited herein. The main power module and the standby power module can be used to supply power to the storage module 26.

[0084] Specifically, when the main power module in the interconnected device is abnormal, the interconnected device triggers the backup power event, and the power supply of the first processor 23, the storage module 26, etc. in the interconnected device is provided by other interconnected device or by the standby power module 25 in the interconnected device. At this time, the first processor 23 can read the cache data in the memory module 22 via the first switching module 21, and write the cache data into the storage module 26, so as to realize the disk writing of the cache data.

[0085] During the backup power, the interconnected device can realize the storage of all cache data, so that the stop of the interconnected device will not cause the loss of the cache data. After the main power module of the interconnected device is restored to normal, the first processor 23 can read the cache data from the storage module 26, and write the cache data into the memory module 22 according to the original path, so as to read and use the corresponding cache data from the memory module 22 by the plurality of control nodes.

[0086] Optionally, the storage module configured in the interconnection device can also be used for backup power of the control nodes. For example, when any control node is powered off, the first processor can write the cache data related to the control node to the storage module to avoid loss of the cache data related to the control node. At this time, since the cache data of the control node has been pre-synchronously recorded in the memory module, the control node itself does not need to perform backup power operation, that is, the backup power module on the control node can be removed, thereby saving the hardware cost of the storage system.

[0087] Figure 7 A schematic diagram of a storage system according to another embodiment of the application is shown.

[0088] As shown in Figure 7 , the storage system can be provided with only one interconnection device, which can also include a controller 27, which can be electrically connected with the first processor 23 and the memory module 22.

[0089] The controller 27 can be a CPLD (Complex Programmable Logic Device). Both the main power module and the backup power module can be used to supply power to the controller 27.

[0090] The controller 27 can be electrically connected with a plurality of control nodes 10 respectively, and be used to receive identification information from the control nodes 10, which can be used to indicate whether the corresponding control node 10 is powered off.

[0091] After receiving the identification information from the control nodes 10, the controller 27 can determine whether the identification information indicates that the control node 10 is powered off, and send a backup signal to the first processor 23 in the case that it is determined that the identification information indicates that the control node is powered off. The backup signal can be used to indicate the control node 10.

[0092] The first processor 23 can be used to read fourth cache data related to the control node 10 from the memory module 22 based on the backup signal, and write the fourth cache data to the storage module 26.

[0093] Specifically, after receiving the backup signal, the first processor 23 can determine the control node 10 indicated by the backup signal, and determine the cache partition corresponding to the indicated control node 10 from the memory module 22, read all cache data in the cache partition to obtain the fourth cache data related to the indicated control node 10, and then write the fourth cache data to the storage module 26 to implement the write-to-disk processing of the cache data of the indicated control node 10.

[0094] According to the embodiment of the present application, by setting the backup power module and the storage module on the interconnection device, the data disk process can be implemented on the interconnection device without the participation of the control node. Specifically, after the AC power supply of the control node is powered off, the control node can provide the identification information indicating the power-off of the AC power supply to the controller of the interconnection device; the controller receives the identification information and processes it to obtain a backup signal and send the backup signal to the first processor; the first processor can send a preparation signal after a certain time after receiving the backup signal to inform the interconnection device that the cache data needs to be saved at this time; at this time, the first processor can write the corresponding cache data into the storage module. Therefore, the entire data disk process only needs the control node to provide the identification information to the interconnection device, without the participation of the control node, realizing the decoupling of the data disk process and the control node, so that the control node does not need to maintain power supply during the data disk process, thereby the backup power module on each control node can be removed to reduce the hardware cost of the control node.

[0095] Optionally, in the interconnection device, the PCIe protocol used by the first switching module can support the PCIe hot plug function. For components connected to the first switching module through the PCIe link, including the memory module, the control node, etc., when the PCIe link fails, such as the bandwidth of the PCIe link is reduced, the transmission speed of the PCIe link is reduced, or the PCIe link is disconnected, the first processor provided in the interconnection device can be used for hot plug repair.

[0096] Figure 8A A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0097] As shown in Figure 8A In the storage system, the memory module 22 can include a plurality of memory units 221, each of which can be electrically connected to the controller 27, and the first processor 23 can be electrically connected to the controller 27.

[0098] Each memory unit 221 can be electrically connected to the first switching module 21 through an 8-channel PCIe link. According to the number of PCIe channels of the first switching module 21, the number of memory units 221 can be increased as needed, which is not limited here.

[0099] The memory unit 221 can support the hot plug function in structure and hardware design, and when a certain memory unit 221 fails, the memory unit 221 can be replaced online.

[0100] To increase the reliability of the storage system, when a memory unit 221 fails, online repair can be performed by cooperation of the controller 27 and the first processor 23. Specifically, the first in-place signal, the power control signal of each memory unit 221, and the reset signal of the corresponding PCIe link can be connected to the controller 27, and the controller 27 forwards the processed signals to the first processor 23, and the first processor 23 performs online repair operations as needed.

[0101] In this online repair operation, the reset operation for the memory unit 221 can be performed first, which only needs to restart part of the circuit in the memory unit 221, so the time-consuming of the reset operation is shorter.

[0102] The memory unit 221 can be configured to provide the first in-place signal to the controller 27. The first processor 23 can be configured to poll and detect each memory unit 221, and in the case where it is determined that one memory unit 221 fails, the first processor 23 can send failure information to the controller 27.

[0103] After receiving the failure information, the controller 27 can first determine whether the failed memory unit is suitable for online repair, that is, the controller 27 can determine whether the failed memory unit is in place based on the received first in-place signal of the failed memory unit. If it is determined that the failed memory unit is off-site, it can be determined that the current memory unit has fallen off from the slot or connection interface, and thus is not suitable for the online repair process. At this time, the controller 27 can convey the determination result that the memory unit is off-site to the first processor 23, so that the first processor 23 sends warning information to the maintenance personnel of the storage system based on the determination result, so that the maintenance personnel manually repair the memory unit. If it is determined that the failed memory unit is in place, the failed memory unit can be repaired using the online repair method first. At this time, the controller 27 can send a repair signal to the first processor 23, and the repair signal can be used to indicate the failed memory unit.

[0104] The first processor 23 can determine the indicated failed memory unit based on the repair signal, and send a reset instruction to the failed memory unit to control the failed memory unit to perform a reset operation.

[0105] Alternatively, the controller 27 can connect the reset signal interface of each memory unit 221, and the first processor 23 can send a reset instruction to the failed memory unit via the corresponding reset signal interface in the controller 27, so that the failed memory unit performs a reset operation.

[0106] Optionally, after sending the reset command, the first processor 23 can continue to poll the status of multiple memory units 221. Based on the polling results, if it is still determined that the faulty memory unit has not completed the fault repair, the first processor 23 can perform a restart operation for the faulty memory unit.

[0107] Optionally, the controller 27 can be connected to the power control interface of each memory cell 221. The first processor 23 can send a restart command to the faulty memory cell through the corresponding power control interface in the controller 27 so that the faulty memory cell can perform a restart operation.

[0108] Alternatively, the restart operation can also be achieved by powering on and off the faulty memory cell. Specifically, the first processor 23 can control the main power module to disconnect and reconnect the power supply link with the faulty memory cell to perform power-on / off operations on the faulty memory cell.

[0109] Optionally, if the restart operation still fails to repair the faulty memory unit, the first processor 23 can send a warning message to the storage system's maintenance personnel so that the maintenance personnel can manually repair the memory unit.

[0110] Figure 8B A schematic diagram of a storage system according to another embodiment of the present invention is shown.

[0111] like Figure 8B As shown, in the storage system, the interconnect device may also include multiple first connectors 28, which can be electrically connected to the first switching module 21 and the control node 10 respectively to form a connection link between the control node 10 and the first switching module 21.

[0112] The first connector 28 can be a CDFP (Centum Dual-Fiber Push-On) connector.

[0113] The control node 10 may be equipped with a signal compensation card 11, a second processor 12, and a node power supply module 13.

[0114] The signal compensation card 11 can be a retimer (signal shaper) card of the control node 10. The signal compensation card 11 can restore, clean, and reconstruct high-speed digital signals to overcome the distortion problems caused by distance, loss, noise, and jitter during signal transmission. It can compensate for channel loss, eliminate signal jitter, improve signal integrity, reduce bit error rate, and thus extend the effective transmission distance of high-speed signals.

[0115] The control node 10 can be electrically connected with the signal compensation card 11 through the signal, and thus the connection link between the control node 10 and the first switching module 21 can include a sub-link between the signal compensation card 11 and the first connector 28, and a sub-link between the first connector 28 and the first switching module 21.

[0116] The second processor 12 can be a CPU of the control node 10. The second processor 12 can be connected with the signal compensation card 11, and the cache data generated by the second processor 12 can be sent to the first switching module 21 through the signal compensation card 11 and the first connector 28 in sequence.

[0117] The node power supply module 13 can be a PSU of the control node 10. The node power supply module 13 can be used to supply power to various components on the control node 10, such as the signal compensation card 11 and the second processor 12. Similar to the main power supply module on the interconnection device, the node power supply module 13 can also provide 220V AC power, 12V DC power, etc. to the signal compensation card 11, the second processor 12, etc., which is not limited herein. Alternatively, when the node power supply module 13 cannot provide 220V AC power to the various components on the control node 10, it can be considered that the control node 10 is powered off.

[0118] Alternatively, when the connection link of one control node 10 and the first switching module 21 is abnormal, the first processor 23 and the second processor 12 can synchronously perform an online repair operation on the connection link.

[0119] For the first processor 23, the first processor 23 can access the second presence signal of each first connector 28; or the controller 27 can access the second presence signal of each first connector 28, and the controller 27 can feed back the presence discrimination result of each first connector 28 to the first processor 23.

[0120] The first processor 23 can perform polling detection on multiple connection links, in the case that one connection link is detected to be abnormal based on the polling result, the first processor 23 can determine a target connector associated with the abnormal connection link, and obtain the second presence signal of the target connector, or the presence discrimination result of the target connector. In the case that the target connector is determined to be off based on the second presence signal or the presence discrimination result of the target connector, the first processor 23 can send warning information to the operation and maintenance personnel of the storage system, so that the operation and maintenance personnel manually repair the memory unit. In the case that the target connector is determined to be on based on the second presence signal or the presence discrimination result of the target connector, the first processor 23 can sequentially issue a disable instruction and a start instruction to the target connector to perform in-band repair on the target connector.

[0121] For the second processor 12, similar to the first processor 23, the second processor 12 can access the second in-situ signal of each first connector 28. And, the second processor 12 can perform polling detection on the plurality of connection links, in the case that an abnormal connection link is detected based on the polling result, the second processor 12 can determine the target connector associated with the abnormal connection link, and obtain the second in-situ signal of the target connector. In the case that the target connector is determined to be in-situ based on the second in-situ signal of the target connector, the second processor 12 can determine the target signal compensation card associated with the abnormal connection link, and control the node power supply module 13 to disconnect and reconnect the power supply link with the target signal compensation card, to perform power-on and power-off operations on the target signal compensation card.

[0122] Optionally, the repair operations performed by the first processor 23 and the repair operations processed by the second processor 12 can be executed in sequence in time, for example, the in-band repair operation can be preferentially executed by the first processor 23, and after it is determined that the online repair of the connection link cannot be completed, the power-on and power-off operation on the signal compensation card is executed by the second processor 12. Alternatively, the repair operations performed by the first processor 23 and the repair operations processed by the second processor 12 can be executed synchronously in time, which is not limited herein.

[0123] According to the embodiments of the present application, through the structure and hardware design, the PCIe link of the first switching module can support online repair, when the conditions for online repair are met, the first processor, the second processor, the controller and the like components can cooperate to control the online repair of the connection link between the control node and the first switching module and the connection link between the memory unit and the first switching module, thereby saving the operation and maintenance cost and improving the operation and maintenance efficiency.

[0124] Optionally, the interconnection device can also support decoupling of the data mirroring channel and the cluster management channel.

[0125] Figure 9 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0126] As shown in Figure 9 In the storage system, a second switching module 29 can also be arranged in the interconnection device. The second switching module 29 can be electrically connected with the plurality of control nodes 10 respectively, and electrically connected with the first processor 23.

[0127] The second switching module 29 can be a Switch chip supporting CXL protocol, which can realize high-speed interconnection of the plurality of control nodes 10 and the first processor 23.

[0128] Optionally, the second switching module 29 can serve as the hub of the cluster management channel in the storage system, that is, the signals transmitted in the second switching module 29 can be network signals.

[0129] Optionally, the control node 10 can be provided with an optical interface card 14. The optical interface card 14 can be electrically connected with the second processor 12, and the second processor 12 can send network signals in the form of optical signals via the optical interface card 14.

[0130] Correspondingly, the interconnection device can be provided with an interface or connector for receiving network signals in the form of optical signals. For example, the interconnection device can further include a plurality of second connectors 210, which can be electrically connected with the second switching module 29 and the control node 10, specifically, can be electrically connected with the optical interface card 14 on the control node 10 through an optical fiber, so that the plurality of control nodes 10 are interconnected through at least one interconnection device.

[0131] The second connector 210 can be an SFP (Small Form-factor Pluggable) optical module, which can realize optical-electric conversion. At its sending end, i.e. the connection end of the second connector 210 and the optical interface card 14, the second connector 210 can provide electrical signals to a laser driver, drive a laser diode to emit light through the laser driver, and convert the electrical signals into optical signals. At its receiving end, i.e. the connection end of the second connector 210 and the second switching module 29, the second connector can convert optical signals into electrical signals through a photoelectric detector by photoelectric effect, and through shaping and amplification processing to obtain the original input electrical signals and provide them to the second switching module 29.

[0132] The second processor 12 can be configured to generate management signals and provide the management signals to the second switching module 29 via the optical interface card 14 and the second connector 210, so that the first processor 23 performs out-of-band management on the plurality of control nodes 10 based on the management signals.

[0133] In some embodiments, the first processor 23 cannot directly process the management signals provided by the second switching module 29. At this time, the interconnection device can further be provided with a conversion module 211. The conversion module 211 can be electrically connected with the second switching module 29 and the first processor 23 respectively, and can convert the received management signals into management signals suitable for processing by the first processor 23.

[0134] The second switching module 29 can also be configured to provide the management signals from the plurality of control nodes 10 to the first processor 23 via the conversion module 211. The first processor 23 can be configured to perform out-of-band management on the plurality of control nodes 10 based on the plurality of management signals.

[0135] According to the embodiment of the present application, by arranging the second switching module in the interconnection device, the interconnection device can be used to realize the network interconnection of multiple control nodes and the out-of-band management, meet the inter-cluster network communication requirement, and save the cost and the cabinet space without arranging additional switches in the storage system, so as to facilitate the expansion of the storage system.

[0136] Optionally, the interconnection device can use a BMC (Baseboard Management Controller) to realize the case management, and the BMC can realize the functions of fan control, temperature acquisition, abnormal alarm monitoring, etc. In addition, the interconnection device can also use a controller to realize the fan control in the startup phase, the BBU battery standby power phase, and the BMC abnormality phase, so as to improve the stability of the overall operation phase of the interconnection device.

[0137] Figure 10 A schematic diagram of a storage system according to another embodiment of the present application is shown.

[0138] As shown in Figure 10 In the storage system, the interconnection device can further include a fan module 212 and a baseboard management controller 213. The baseboard management controller 213 can be electrically connected with the fan module 212 and be configured to control the rotation of the fan module 212.

[0139] For example, each heat generating component of the interconnection device can be configured with a temperature sensor, and correspondingly, each fan of the fan module 212 can also face each heat generating component. The baseboard management controller 213 can acquire the temperature data fed back by each temperature sensor, and based on the temperature data, adjust the rotation speed of each fan through a set fan modulation strategy, so as to realize the rotation control of the fan module.

[0140] Optionally, the controller 27 can also be electrically connected with the fan module 212. The controller 27 can be configured to control the rotation of the fan module 212 in the case that the interconnection device is in the startup phase or the baseboard management controller 213 is faulty.

[0141] Specifically, in the startup phase of the interconnection device, the controller 27 is generally responsible for the startup timing of each component in the interconnection device, so the controller 27 is generally started before the baseboard management controller 213. Therefore, in the case that the interconnection device is in the startup phase, the controller 27 can control each fan of the fan module 212 to rotate based on a preset fan modulation strategy. Similarly, in the case that the baseboard management controller 213 is faulty, the controller 27 needs to take over the rotation control of the fan module 212 in order to prevent the heat generating components in the interconnection device from being burned out due to high temperature.

[0142] Optionally, when the interconnection device is in the BBU standby power stage, due to the low power of the BBU and the large power consumption of the baseboard management controller 213, the baseboard management controller 213 can be first turned off at this time, and the rotation control of the fan module 212 is replaced by the controller 27 at this stage, so as to reduce the power consumption of the interconnection device under the premise of ensuring the safe operation of the interconnection device.

[0143] Figure 11 A schematic diagram of a storage system cluster according to an embodiment of the application is shown.

[0144] As shown in Figure 11 , the storage system cluster can include two storage systems.

[0145] Optionally, the interconnection device of the storage system includes a first expansion interface Scale-out1, the first expansion interface Scale-out1 is electrically connected with the first switching module included in the interconnection device of the storage system, and is electrically connected with the first expansion interface Scale-out1 of other storage systems, so as to realize the cascade of two storage systems.

[0146] Optionally, the interconnection device of the storage system includes a second expansion interface Scale-out2, the second expansion interface Scale-out2 is electrically connected with the second switching module included in the interconnection device of the storage system, and is electrically connected with the second expansion interface Scale-out2 of other storage systems, so as to realize the cascade of two storage systems.

[0147] Optionally, in another embodiment, the storage system cluster can include more than two storage systems, and the more than two storage systems can be interconnected based on a ring topology to form the storage system cluster.

[0148] Optionally, the interconnection device of the storage system includes two first expansion interfaces Scale-out1, the first expansion interfaces Scale-out1 are electrically connected with the first switching module included in the interconnection device of the storage system, one of the first expansion interfaces Scale-out1 can be electrically connected with the first expansion interface Scale-out1 of one other storage system, and the other first expansion interface Scale-out1 can be electrically connected with the first expansion interface Scale-out1 of another other storage system, so as to realize the cascade of more than two storage systems.

[0149] Optionally, the interconnection device of the storage system comprises two second expansion interfaces Scale-out2, the second expansion interfaces Scale-out2 are electrically connected with the second switch modules comprised by the interconnection device of the storage system, one of the second expansion interfaces Scale-out2 can be electrically connected with one of the second expansion interfaces Scale-out2 of another storage system, and the other of the second expansion interfaces Scale-out2 can be electrically connected with the other of the second expansion interfaces Scale-out2 of another storage system, so as to realize cascade connection of more than two storage systems.

[0150] According to the embodiments of the present application, the cascade connection of multiple storage systems can be realized through the first expansion interface and the second expansion interface reserved on the interconnection device, the interconnection between more control nodes can be realized, and thus the flexibility and expandability of the storage system are effectively improved, and the cost of the multi-control shared storage architecture is reduced.

[0151] Those skilled in the art can understand that the features described in various embodiments of the present application can be combined and / or integrated in various ways, even if such combinations or integrations are not explicitly described in the present application. In particular, the features described in various embodiments of the present application can be combined and / or integrated in various ways without departing from the spirit and teachings of the present application. All these combinations and / or integrations fall within the scope of the present application.

[0152] The embodiments of the present application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present application, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A storage system, characterized by, The storage system comprises: a plurality of control nodes; and at least one interconnection device, the interconnection device comprising a first switching module and a memory module, the first switching module being electrically connected to the plurality of control nodes respectively and electrically connected to the memory module, and the first switching modules of at least one interconnection device being connected to each other; wherein the first switching module is configured to write first cache data provided by the control nodes to the memory module, or configured to provide second cache data stored in the memory module to the control nodes, so that the plurality of control nodes realize cache sharing through the at least one interconnection device; wherein the interconnection device further comprises: a first processor; a controller electrically connected to the first processor and electrically connected to the memory module; and a storage module electrically connected to the first processor, the storage module being configured to store cache data; the controller is configured to receive identification information from the control nodes, and send a backup signal to the first processor in a case where it is determined that the identification information indicates that the control node is powered off; the first processor is configured to read fourth cache data related to the control node from the memory module based on the backup signal, and write the fourth cache data to the storage module.

2. The storage system of claim 1, wherein, The first processors of at least one interconnection device are connected to each other.

3. The storage system of claim 2, wherein, In a case where one interconnection device fails, the other interconnection devices are configured to read third cache data from the memory module of the failed interconnection device via the first processor of the failed interconnection device, and write the third cache data to the memory module of the other interconnection devices.

4. The storage system of claim 2, wherein, The memory module comprises a plurality of memory units, the memory units being configured to provide first in-place signals to the controller; wherein the first processor is configured to send failure information to the controller in a case where it is detected that one memory unit fails; the controller is configured to send a repair signal to the first processor in response to receiving the failure information, in a case where it is determined that the first in-place signal of the failed memory unit indicates that it is in place; the first processor is further configured to send a reset instruction to the failed memory unit based on the repair signal, to control the failed memory unit to perform a reset operation.

5. The storage system of claim 4, wherein, The interconnection device further comprises a main power module, the main power module being configured to supply power to the first switching module, the memory module, the first processor, the controller and the storage module; wherein the first processor is further configured to control the main power module to disconnect and reconnect the power supply link of the failed memory unit in a case where it is determined that the failed memory unit has not completed failure repair, to perform power-on and power-off operations on the failed memory unit.

6. The storage system of claim 5, wherein, The interconnection device further comprises: a backup power module, configured to supply power to the first switching module, the memory module, the first processor, the controller and the storage module in a case where the main power module works abnormally.

7. The storage system of claim 5, wherein, In a case where one interconnection device fails, the main power module of the other interconnection devices is further configured to supply power to the failed interconnection device.

8. The storage system of claim 2, wherein, The interconnection device further comprises a plurality of first connectors, each of which is electrically connected with the first switching module and the control node to form a connection link between the control node and the first switching module.

9. The storage system of claim 8, wherein, the first connector is configured to provide a second in-situ signal to the first processor; the first processor is configured to, in a case where an abnormal connection link is detected, determine a target connector associated with the abnormal connection link, and in a case where the second in-situ signal provided by the target connector indicates that it is in-situ, sequentially issue a disable instruction and a start instruction to the target connector to perform in-band repair on the target connector.

10. The storage system of claim 9, wherein, The control node comprises: a signal compensation card electrically connected with the first connector; a second processor electrically connected with the signal compensation card; and a node power supply module configured to supply power to the signal compensation card and the second processor, respectively; wherein the second processor is configured to, in a case where an abnormal connection link is detected, determine a target signal compensation card associated with the abnormal connection link, and control the node power supply module to disconnect and reconnect the power supply link between the node power supply module and the target signal compensation card to perform power-on and power-off operations on the target signal compensation card.

11. The storage system of claim 2, wherein, The interconnection device further comprises: a second switching module; and a plurality of second connectors electrically connected with the second switching module and the control node, so that a plurality of the control nodes are interconnected through at least one of the interconnection devices.

12. The storage system of claim 11, wherein, The interconnection device further comprises: a switching module electrically connected with the second switching module and the first processor; wherein the second switching module is further configured to provide management signals from a plurality of the control nodes to the first processor through the switching module; the first processor is configured to perform out-of-band management on a plurality of the control nodes based on a plurality of the management signals.

13. The storage system of claim 12, wherein, The control node further comprises: an optical network card electrically connected with the second connector; a second processor electrically connected with the optical network card; wherein the second processor is configured to generate the management signals and provide the management signals to the second switching module through the optical network card and the second connector, so that the first processor performs out-of-band management on the control node based on the management signals.

14. The storage system of claim 1, wherein, The interconnection device further comprises: a fan module; and a baseboard management controller electrically connected with the fan module, the baseboard management controller being configured to control rotation of the fan module.

15. The storage system of claim 14, wherein, The interconnection device further comprises: a controller electrically connected with the fan module, the controller being configured to control rotation of the fan module in a case where the interconnection device is in a start-up stage or the baseboard management controller fails.

16. A storage system cluster, comprising: The storage system cluster comprises at least two storage systems as claimed in any one of claims 1-15.

17. The storage system cluster of claim 16, wherein, The interconnection device of the storage system comprises at least one first expansion interface, which is electrically connected with a first switching module comprised in the interconnection device of the storage system and electrically connected with a first expansion interface of another storage system to realize cascade of at least two storage systems.

18. The storage system cluster of claim 16, wherein, The interconnection device of the storage system comprises at least one second expansion interface, which is electrically connected with a second switching module comprised in the interconnection device of the storage system and electrically connected with a second expansion interface of another storage system to realize cascade of at least two storage systems.

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