RISC-V superscalar processor performance optimization method and system based on Gem5 platform

Abstract

The invention provides an RISC-V superscale processor performance optimization method and system based on a Gem5 platform, and relates to the technical field of processor structure optimization. An instruction set architecture and an RISC-V superscale processor overall architecture are set on the Gem5 platform; according to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor, each pipeline stage is divided into a front-end module, a middle-end module and a rear-end module; setting performance test parameters for the front end, the middle end and the rear end respectively, performing performance test on the front end, the middle end and the rear end based on the performance test parameters, and positioning a performance bottleneck and a bottleneck part of the processor according to a test result; according to the performance bottleneck and the specific bottleneck part, local architecture optimization adjustment is carried out, a progressive multi-level optimization process is set, the performance bottleneck and the bottleneck part of the RISC-V superscale processor are subjected to modular and overall optimization work, and the optimization modeling process of the RISC-V superscale processor is completed.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of processor structure optimization, in particular to a RISC-V superscalar processor performance optimization method and system based on a Gem5 platform. BACKGROUND

[0002] The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute the prior art.

[0003] In the face of expanding application scenarios and increasing performance requirements, RISC-V processors also face new challenges. The key to improving the performance of RISC-V processors lies in the rapid identification of performance bottlenecks. However, the development cycle of processors is relatively long and requires multiple iterations and optimizations. Direct optimization through RTL (Register Transfer Level) hardware design not only consumes time and effort, but also makes it difficult to guarantee the efficiency and accuracy of optimization.

[0004] To solve this problem, existing solutions generally use simulation methods to explore and verify in the early stage before hardware implementation. This method can reduce development costs, improve implementation efficiency, and at the same time guarantee the effectiveness of the solution. In the field of simulation, common techniques include CModel simulation, mathematical model simulation, and architecture simulator simulation. In practice, to effectively improve hardware performance, multiple simulation techniques are often combined. CModel accurately implements algorithms and optimizes algorithms to provide specific algorithm solutions for processor optimization.

[0005] However, due to the high correlation between the internal modules of the processor, CModel has certain limitations in testing and optimizing the overall dynamic performance. Mathematical modeling provides support for performance evaluation by theoretically analyzing the performance peak of the processor architecture, but the results are often abstract and difficult to directly use for architecture optimization. To overcome these problems and optimize the processor architecture, architecture simulators have emerged. They combine the algorithm optimization capabilities of CModel and the more detailed pipeline simulation advantages, providing a new solution for processor architecture optimization. To explore, analyze and optimize the processor architecture in the early stages of hardware implementation, the industry widely adopts the simulator-aided design process. Currently, the mainstream simulators include QEMU, NEMU, and Simics. QEMU is a lightweight, fast emulation full-system simulator, with the main advantages of high emulation speed and good software compatibility. However, its simulation granularity is coarse, making it difficult to provide detailed micro-architecture behavior modeling and performance evaluation, especially in core areas such as out-of-order scheduling, multi-issue, and cache subsystems. NEMU is a lightweight simulator for teaching and research purposes, with a simple structure but lacking strong extensibility and modularization capabilities, making it unable to support complex micro-architecture simulation and detailed performance bottleneck analysis. Simics has strong visualization and industrial-level application support, but its closed-source nature and high cost pose a significant barrier to academic researchers, and its native support for the RISC-V instruction set is not perfect.

[0006] In summary, the existing processor architecture design has the following problems:

[0007] 1) The design is not standardized, which cannot guarantee the correctness of data and control paths.

[0008] 2) The processor is a large and complex system, it is difficult to design a processor with superior performance of each module through pre-design thinking, and it is easy to ignore the correlation between modules. It is difficult to directly and clearly analyze the performance bottleneck of the module in the large system. The simulation granularity is coarse, making it difficult to provide detailed micro-architecture behavior modeling and performance evaluation, especially in core areas such as out-of-order scheduling, multi-issue, and cache subsystems.

[0009] 3) Existing processors need to perform corresponding instruction stress testing when verifying functions, which can only be tested in simple scenarios. The structure is simple but lacks strong extensibility and modularization capabilities, making it unable to support complex micro-architecture simulation and detailed performance bottleneck analysis. SUMMARY

[0010] The RISC-V superscalar processor performance optimization method and system based on the Gem5 platform are proposed to solve the above problems, the method for optimizing the structure of the RISC-V superscalar processor is completed by Gem5, the modeling of the RISC-V superscalar processor is completed, and the design of the local module and the whole module is performed for the key modules of the processor, so that the performance of the processor is significantly improved under various Benchmark tests.

[0011] According to some embodiments, the present disclosure adopts the technical scheme as follows:

[0012] The RISC-V superscalar processor performance optimization method based on the Gem5 platform comprises:

[0013] Setting the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5;

[0014] According to the flow characteristics of the overall architecture of the RISC-V superscalar processor, each flow stage is divided into a front-end module, a middle-end module and a back-end module;

[0015] Setting performance test parameters for the front-end, middle-end and back-end respectively, performing performance tests on the front-end, middle-end and back-end based on the performance test parameters, and positioning the performance bottleneck and bottleneck position of the processor according to the test results;

[0016] According to the performance bottleneck and specific bottleneck position, local architecture optimization adjustment is performed, a progressive multi-level optimization process is set, and optimization work is performed for the performance bottleneck and bottleneck position of the RISC-V superscalar processor in a module-by-module and whole-body manner to complete the optimization modeling process of the RISC-V superscalar processor;

[0017] The progressive multi-level optimization process comprises five progressive levels of optimization, including local parameter fine-tuning, local algorithm optimization, local-to-adjacent module linkage modification, whole pipeline modification and bottom logic modification, and realizes the optimization process of the processor from a local module to a whole architecture.

[0018] According to some embodiments, the present disclosure adopts the technical scheme as follows:

[0019] The RISC-V superscalar processor performance optimization system based on the Gem5 platform comprises:

[0020] The test initialization module is used for setting the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5;

[0021] The module division module is used for dividing each flow stage into a front-end module, a middle-end module and a back-end module according to the flow characteristics of the overall architecture of the RISC-V superscalar processor;

[0022] The bottleneck positioning module is configured to set performance test parameters for the front end, the middle end and the rear end respectively, perform performance tests on the front end, the middle end and the rear end based on the performance test parameters, and locate the performance bottleneck and the bottleneck position of the processor according to the test results.

[0023] The hierarchical optimization module is configured to perform local architecture optimization adjustment according to the performance bottleneck and the specific bottleneck position, set a progressive multi-level optimization process, perform optimization work on a module-by-module and overall basis for the performance bottleneck and the bottleneck position of the RISC-V superscalar processor, and complete the optimization modeling process of the RISC-V superscalar processor.

[0024] The progressive multi-level optimization process includes five progressive levels of optimization, including local parameter fine-tuning, local algorithm optimization, linkage modification from a local module to an adjacent module, modification of an overall pipeline, and modification of a bottom logic, to realize an optimization process of the processor from a local module to an overall architecture.

[0025] According to some embodiments, the present disclosure adopts the following technical solutions:

[0026] A computer program product comprising a computer program, which, when executed by a processor, implements the RISC-V superscalar processor performance optimization method based on the Gem5 platform.

[0027] According to some embodiments, the present disclosure adopts the following technical solutions:

[0028] A non-transitory computer-readable storage medium for storing computer instructions, which, when executed by a processor, implements the RISC-V superscalar processor performance optimization method based on the Gem5 platform.

[0029] According to some embodiments, the present disclosure adopts the following technical solutions:

[0030] An electronic device comprising a processor, a memory and a computer program; wherein the processor is connected to the memory, and the computer program is stored in the memory; when the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device performs the RISC-V superscalar processor performance optimization method based on the Gem5 platform.

[0031] Compared with the prior art, the present disclosure has the following beneficial effects:

[0032] The RISC-V superscalar processor performance optimization method based on the Gem5 platform of the present disclosure sets up a progressive multi-level optimization process, optimizes the performance bottleneck and bottleneck part of the RISC-V superscalar processor in a modular and overall manner, completes the optimization modeling process of the RISC-V superscalar processor, and realizes the optimization process of the processor from the local module to the overall architecture through the progressive multi-level optimization process of local parameter fine-tuning, local algorithm optimization, linkage modification from local module to adjacent module, overall pipeline modification, and bottom logic modification.

[0033] The RISC-V superscalar processor performance optimization method based on the Gem5 platform of the present disclosure can better match the needs of different types of instructions and application scenarios by systematically adjusting the processor pipeline structure (such as increasing the pipeline level, optimizing the pipeline depth, adjusting the stage function division, etc.). The optimized pipeline structure can reduce bubbles and data conflicts, improve the smoothness of instruction flow and execution efficiency. In addition, the optimization of the overall pipeline helps to improve the adaptability of the processor to high concurrency and high load tasks, and realizes higher instruction throughput and lower energy consumption.

[0034] The RISC-V superscalar processor performance optimization method based on the Gem5 platform of the present disclosure can fully tap the performance potential of the existing architecture by fine-tuning the key parameters of each module of the processor (such as cache capacity, queue depth, port number, etc.), without significantly increasing hardware resource consumption. Parameter fine-tuning can effectively alleviate local resource bottlenecks, improve the parallelism and utilization of each module, optimize the throughput capacity of instruction flow, and thus improve the running efficiency and performance of the overall system.

[0035] The RISC-V superscalar processor performance optimization method based on the Gem5 platform of the present disclosure considers the cooperative relationship between adjacent modules, and through linkage adjustment of data paths, control signals and resource allocation strategies, it can further break through the performance bottleneck between modules. For example, by optimizing the interaction mechanism between the transmit queue and the renaming unit and the execution unit, data front-end and resource dynamic scheduling are realized, the critical path delay is effectively shortened, and the overall efficiency of the pipeline is improved. Such linkage optimization helps to systematically improve the parallel execution capability and stability of the processor.

[0036] The disclosed RISC-V superscalar processor performance optimization method based on the Gem5 platform divides the processor architecture into three parts: the pipeline stages before dispatch are considered the front end, the pipeline stages leading to dispatch are considered the middle end, and the execution writeback is considered the back end. Modifications to the front-end value module can leverage Gem5 to verify the accuracy of contemporary branch prediction algorithms, such as Gshare, Bi-Mode, Tournament, and TAGE, for the current processor architecture and select the optimal solution. Gem5 can also simulate optimized branch prediction algorithms and test their performance. Modifications to the middle end can be performed using Gem5 on the transmit module. By optimizing the implementation of the underlying logic, the robustness and fault tolerance of the system can be improved. For example, improvements to the register renaming table and recycling mechanism can effectively avoid resource waste and data conflicts. Improvements to the exception and interrupt handling process can also enhance the system's real-time responsiveness. Optimizing the underlying logic provides a solid foundation for efficient collaboration between upper-level modules, further ensuring overall processor performance and reliability.

[0037] The disclosed RISC-V superscalar processor performance optimization method based on the Gem5 platform achieves systemic performance improvements from local modules to the overall architecture through a multi-layered approach, including parameter fine-tuning, local algorithm optimization, module linkage modification, overall pipeline adjustment, and underlying logic optimization. These optimization measures not only effectively break through single-point performance bottlenecks but also collaboratively improve the data flow efficiency between modules and the overall resource utilization of the system, thereby significantly improving the processor's instruction throughput, response speed, and energy efficiency, meeting the needs of high-performance application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which constitute a part of the present disclosure, are used to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation to the present disclosure.

[0039] Figure 1 This is a diagram of the implementation process of the RISC-V superscalar processor performance optimization method based on the Gem5 platform according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0041] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present disclosure. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs.

[0042] It is to be noted that the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit exemplary embodiments according to the present disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise, and it will be further understood that the terms "comprise" and / or "include" when used in this specification, specify the presence of stated features, steps, operations, devices, components and / or combinations thereof.

[0043] Embodiment 1

[0044] In an embodiment of the present disclosure, a RISC-V superscalar processor performance optimization method based on a Gem5 platform is provided, and the steps include:

[0045] Step 1: Set the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5;

[0046] Step 2: According to the flow characteristics of the overall architecture of the RISC-V superscalar processor, divide each flow stage into a front-end module, a middle-end module, and a back-end module;

[0047] Step 3: Set performance test parameters for the front-end, middle-end, and back-end respectively, perform performance tests on the front-end, middle-end, and back-end based on the performance test parameters, and locate the processor performance bottleneck and bottleneck part according to the test results;

[0048] Step 4: Perform local architecture optimization adjustment according to the performance bottleneck and specific bottleneck part, set a progressive multi-level optimization process, perform module-by-module and overall optimization work for the performance bottleneck and bottleneck part of the RISC-V superscalar processor, and complete the optimization modeling process of the RISC-V superscalar processor;

[0049] The progressive multi-level optimization process includes five levels of optimization in sequence, including local parameter fine-tuning, local algorithm optimization, local-to-adjacent module linkage modification, overall pipeline modification, and bottom logic modification, to realize the optimization process of the processor from the local module to the overall architecture.

[0050] As an embodiment, the RISC-V superscalar processor performance optimization method based on the Gem5 platform of the present disclosure performs performance optimization on the RISC-V architecture superscalar processor based on the Gem5 platform. It includes detecting the correctness of the processor design, using gem5 to count which test information to locate the bottleneck problem, implementing the general process of processor optimization, realizing the overall optimization of the local to the overall architecture of the processor, and improving the performance of the processor. The specific implementation process is as follows:

[0051] Step 1: Set the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5, and perform correctness testing;

[0052] Specifically, in this step 1, the customization of the instruction set architecture and the overall architecture of the RISC-V superscalar processor is included, and the basic architecture of the RISC-V superscalar processor is implemented on Gem5, the overall pipeline design is implemented, and the micro-architecture design of each pipeline is implemented.

[0053] Based on the above instruction set architecture and the design of the pipeline micro-architecture, the correctness of the RISC-V superscalar processor is tested, including the first type of instruction set test and the second type of test, which is the preliminary test of various Benchmark, and the first type of instruction set test tests whether the RISC-V superscalar processor can support all the required instruction sets.

[0054] Further, the second type of test is the preliminary test of various Benchmark, which tests whether the processor can correctly execute various Benchmark, and the first type of test and the second type of test constitute the correctness test of the RISC-V superscalar processor.

[0055] Among them, the tested instruction set is the RISC-V instruction set, and the preliminary test of various Benchmark includes Dhrystone, Linpack, Coremark, SPEC CPU2006, etc.

[0056] Step 2: According to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor, each pipeline stage is divided into a front-end module, a middle-end module and a back-end module;

[0057] Specifically, according to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor, the RISC-V superscalar processor structure is divided into three parts as three modules, the pipeline stage before dispatching is taken as the front-end module of the RISC-V superscalar processor, the pipeline stage dispatched to the emission is taken as the middle-end module of the RISC-V superscalar processor, and the execution write-back is taken as the back-end module of the RISC-V superscalar processor, which is ready for subsequent optimization.

[0058] Further, the pipeline characteristics of the overall architecture of the RISC-V superscalar processor include:

[0059] 1. Highly parallel instruction processing

[0060] Multiple issue / multiple issue width: multiple instructions can be fetched, decoded and emitted simultaneously in each clock cycle (such as 3 issue, 8 issue, etc.), which improves instruction level parallelism (ILP).

[0061] Out-of-order execution (OoO): allows instructions to be out of order in the execution stage, as long as the data dependency is satisfied, and maximizes resource utilization.

[0062] 2. Deep pipeline design

[0063] Multi-stage pipeline: usually contains more than ten stages, each stage is functionally subdivided, reducing the delay of each stage, and increasing the clock frequency.

[0064] Each stage of the pipeline is decoupled: through Buffer, queue and other mechanisms, each stage of the pipeline is relatively independent, reducing the waiting for each other.

[0065] 3. Multi-functional execution unit

[0066] Multi-path execution unit: such as ALU, FPU, LSU, branch unit, etc. work in parallel, support multiple types of instructions to execute at the same time.

[0067] Register renaming, forward mechanism: solve data correlation, reduce pipeline congestion.

[0068] 4. Complex data flow and control flow

[0069] Advanced branch prediction: using high-performance predictors such as TAGE, reducing bubbles caused by branches.

[0070] Complex Load / Store arbitration and writeback: memory instruction and data correlation processing is complex, special queue and conflict processing mechanism is needed.

[0071] 5. High bandwidth front-end and large capacity back-end

[0072] Wide instruction fetch / decode / issue bandwidth: the front-end can handle multiple instructions at a time, and the back-end has large capacity queues (such as ROB, IssueQ, Load / Store Queue) to support high concurrency.

[0073] The front-end is responsible for efficiently, continuously and accurately sending instructions into the pipeline, providing a data basis for subsequent parallel processing. The wide bandwidth, low latency and branch prediction accuracy of the front-end directly affect the overall throughput. The middle-end is the key conversion area from sequential flow to out-of-order / parallel flow, responsible for resource allocation, dependency resolution and efficient scheduling. The queue capacity, arbitration algorithm and renaming efficiency of the middle-end determine the depth and parallelism of out-of-order execution. The back-end is responsible for actual calculation and data operation, which is the "terminal station" of instruction completion. The number of execution units, memory bandwidth, retirement mechanism, etc. of the back-end determine the upper limit of the final performance.

[0074] The pipeline characteristics of the RISC-V superscalar processor determine the functional division and optimization focus of its front-end, mid-end, and back-end components. A reasonable front-end, mid-end, and back-end division facilitates modular design, performance bottleneck analysis, and future-oriented scalability optimization, forming the foundation for high-performance processor architecture design. The pipeline stages before dispatch are considered the front-end modules of the RISC-V superscalar processor, the pipeline stages leading to dispatch are considered the mid-end modules, and the execution write-back is considered the back-end modules, paving the way for subsequent optimization.

[0075] Step 3: setting performance test parameters for the front-end, mid-end, and back-end respectively, performing performance tests on the front-end, mid-end, and back-end based on the performance test parameters, and locating processor performance bottlenecks and bottleneck locations based on the test results;

[0076] Among them, performance testing includes the third and fourth types of tests. The third type of test is the performance test of three modules, and the fourth type of test is the overall test to locate performance bottlenecks. The testing process is to combine various benchmarks with the control variable method to test data, regress various benchmarks on the data to be tested, control variables according to different data requirements, and select appropriate parameters and algorithms.

[0077] Specifically, performance test parameters are set for the front-end module, mid-end module, and back-end module. The test data for the performance test includes the following:

[0078] 1) The test data of the front-end module includes: instruction cache miss rate, branch instruction prediction error rate, average number of valid instructions after passing through the BPU, and average number of instructions decoded per cycle.

[0079] 2) The test data of the mid-range module includes: the number of register rename stalls, the number of instructions in each dispatch queue, the utilization of each dispatch queue, the number of stalls in each dispatch queue, the number of instructions in each emission queue, the utilization of each emission queue, the number of stalls in each emission queue, and the number of instructions of each type of instruction issued per cycle.

[0080] 3) The test data of the back-end module includes: the number of cycles from the issuance of the load instruction to the write-back, the miss rate of the data cache, the number of times the load and store instruction queue is full, the utilization rate of the load and store instruction queue, the number of times the ROB is full, the number of instructions submitted and retired due to bottlenecks per cycle, the number of waiting cycles that cannot be submitted to the ROB head, and the number of cycles that can be retired but do not reach the head.

[0081] As an embodiment, the storage system is further included, and test data of the storage system includes cache miss rate at each level, number of times of cache read / write port shortage, page table miss rate, number of times of uncacheable requests, average time of cache miss backfill at each level, and average time required for each access to the main memory.

[0082] Further, according to the results of the third type of test, RISC-V superscalar processor local refinement is performed, and the fourth type of test is performed, which is an overall test. The overall test is from large to small, and gradually locates the performance bottleneck in which part. The test data obtained by each part is compared with the ideal data (set performance test parameters) to locate the performance bottleneck and the performance bottleneck part.

[0083] The process of locating the performance bottleneck and the performance bottleneck part is as follows: design rich statistical data, compare the data according to the ideal results, and the modules (or front, middle and back ends) that cannot meet the data are the performance bottlenecks. Continue to analyze the internal data of the module, find the problem one by one, and check one by one. Change the parameters and algorithms of the control variable, and finally find the bottleneck part in layer-by-layer testing. After modifying the bottleneck part, the next bottleneck part will appear. After optimizing the bottleneck part, the performance bottleneck is removed.

[0084] Step 4: According to the performance bottleneck and the specific bottleneck part, local architecture optimization adjustment is performed, and a progressive multi-level optimization process is set. The performance bottleneck and the bottleneck part of the RISC-V superscalar processor are optimized in modules and as a whole, and the optimization modeling process of the RISC-V superscalar processor is completed.

[0085] The progressive multi-level optimization process includes five progressive levels of optimization, including local parameter fine-tuning, local algorithm optimization, local-to-adjacent module linkage modification, overall pipeline modification, and bottom logic modification, to realize the optimization process of the processor from local modules to the overall architecture.

[0086] Specifically, when the performance bottleneck is located, the progressive multi-level optimization process is used for performance optimization. The progressive multi-level optimization process corresponds to five progressive levels of optimization methods, which specifically include the following contents:

[0087] 1) The first level of optimization is local architecture parameter fine-tuning. Under the condition of timing and area allowance, the table item capacity and other parameters are appropriately increased, and the performance change is observed.

[0088] 2) The second level of optimization is local algorithm optimization adjustment. When the first level of optimization cannot solve the performance bottleneck problem, the instruction flow characteristics are refined and adjusted, the algorithm is optimized, and the performance change is observed.

[0089] Specifically, when the first level optimization fails to solve the problem, it indicates that the current solution cannot cover the real rules of the entire instruction stream. For example, in a modern superscalar CPU, the branch predictor determines whether the pipeline can be efficiently pushed forward. If the branch prediction accuracy is low, the pipeline will be frequently flushed, resulting in performance degradation. Initially, performance can be improved by increasing the size of the branch prediction table and other parameters, but when the table entries are large enough, the performance improvement becomes limited. In the Benchmark test, it is found that the branch behavior of some programs is complex, and the prediction accuracy of the traditional 2-bit saturating counter is not high, resulting in a large number of branch prediction failures. After increasing the number of PHT (Pattern History Table) table entries, the branch prediction miss rate is still high, and the performance does not improve significantly.

[0090] As an embodiment, the front-end value module modification can verify the prediction accuracy of the current processor structure by means of gem5, such as Gshare, Bi-Mode, Tournament and TAGE algorithm, which are excellent branch prediction algorithms in the current era, and select the best solution. Gem5 can also simulate the optimized branch prediction algorithm and detect its performance.

[0091] Further, the middle-end part modification can modify the emission module by means of gem5. For example, the problem of low emission efficiency can be solved by increasing the capacity and optimizing the arbitration algorithm, or by accelerating the dispatch and shortening the execution process to improve the emission efficiency. For example, the modification of increasing the number of instructions processed by the processor modifies the existing low-emission processor to an 8-emission processor, simulates the pipeline of the target processor according to the purpose, and verifies that the size of the middle-end emission queue can meet the use by means of the information of Benchmark statistics.

[0092] The present disclosure finds that the branch behavior is strongly related to the global history after analyzing the characteristics of the instruction stream. Therefore, the branch prediction algorithm is upgraded from a simple 2-bit counter to a TAGE (TAgged GEometric history length predictor) branch predictor:

[0093] TAGE adopts a multi-level history length table, which can capture complex branch correlations. Each level of table entries has a different history length, so that both short-term branch behavior and long-term branch behavior can be effectively modeled. After implementing the TAGE algorithm with the Gem5 simulator, the branch prediction error rate is reduced by 40%-50% for complex Benchmarks such as SPEC CPU2006, and the IPC is significantly improved.

[0094] Further, the short-term branch behavior and the long-term branch behavior can be effectively modeled by a process that includes several branch history tables (commonly referred to as Tag Table) in the TAGE predictor, each of which corresponds to branch history information of a different length.

[0095] The short history table is used to capture the behavior of the branch instruction in the last few times (short-term correlation) and can quickly adapt to local branch changes in the program.

[0096] The long history table records the branch history of a longer time span (long-term correlation) and is used to capture complex branch dependencies in the program that span a long distance.

[0097] The history length of each level increases in a geometric progression (such as 4, 8, 16, 32, 64, etc.), so that as many history spans as possible can be covered under the condition of limited hardware resources.

[0098] After implementing the TAGE algorithm with the Gem5 simulator, the branch prediction error rate of complex benchmarks such as SPEC CPU2006 is reduced by 40%-50%, and the IPC is significantly improved.

[0099] 3) The third level optimization is a local to adjacent module linkage modification optimization. When the local adjustment algorithm of the second level optimization cannot solve the performance bottleneck problem, the linkage modification of each module of the RISC-V superscalar processor is studied.

[0100] Specifically, the core of the high-performance RISC-V superscalar processor is the high parallelism of instructions, but the interdependence between instructions will limit the parallelism of instructions. If you want to improve the performance of the processor, you need to improve the ability of the processor to handle the dependency chain. In the instruction stream of RISC-V, the top of many instruction dependency chains is a Load instruction, so you need to improve the speed of Load instruction execution and the speed of waking up other instructions. In the actual processor architecture, optimizing the memory emission queue alone or optimizing the memory pipeline alone often cannot break through the performance bottleneck, and both must be designed together. After expanding the emission queue capacity alone, increasing the emission bandwidth, and optimizing the arbitration algorithm, it will be found that the slow execution speed of the memory pipeline Load causes the bandwidth in the emission queue to be unable to be effectively utilized. If the memory pipeline is analyzed alone, it will be found that the process of the Load instruction executing access Cache is difficult to further optimize the architecture and belongs to a relatively stable execution process. If you want to improve the speed of the entire Load from being awakened to execution to waking up other instructions, you need to link the emission and execution parts together. The specific linkage optimization method is:

[0101] Allowing STD (Data Part) to be independently transmitted to LSU (Load / Store Unit) in the transmission queue in advance when the condition is met can no longer be forced to wait for STA; the AG (Addr_gen) process is moved from the memory pipeline to the transmission arbitration stage, and the physical address is obtained in advance, so that the TLB and D-Cache can be accessed in parallel. Through these two optimizations, the AG process of the Load instruction is hidden in the transmission queue, shortening the execution time of one beat, and waking up other instructions can also be advanced by 1 beat, improving the performance of the processor.

[0102] 4) The fourth level optimization is the modification of the pipeline. If the performance bottleneck problem cannot be solved after the module linkage modification of the third level optimization, the bottleneck problem is located according to the front-end, middle-end and back-end classification, and the pipeline is redesigned and optimized.

[0103] Specifically, after the completion of the linkage modification of each module, if the performance still cannot meet the demand, the performance bottleneck point of the entire processor after modification needs to be located first. Of course, the performance demand is generally not met for Benchmark, so the optimization is also carried out for Benchmark. For the front-end, the input finally fed back to the middle-end is the number of valid instructions sent per cycle, which represents the upper limit of the performance of the processor processing this program. For example, in Dhrystone, after the above three optimizations are performed, the IPC of the program is almost equal to the number of valid instructions sent by the front-end of the processor, which means that the efficiency of the front-end limits the performance of the processor, so the front-end needs to be reanalyzed to improve the front-end instruction fetching capability. For Coremark, the number of valid instructions of the front-end is much larger than the IPC, which means that the performance bottleneck is not in the front-end, and the hit rate of the memory instruction accessing the Cache is also above 99%, which means that it is also irrelevant to the back-end, so the performance bottleneck can be located in the middle-end of the processor. After in-depth analysis, it can be found that the instruction flow in Coremark has a strong dependence, and most of them are dependent on the Load instruction flow, so the ability to resolve the dependence chain needs to be improved. The reason why the Load is slow in the dependence chain at the top is that it does not know whether the Load hits, so it cannot be awakened in advance, and it is executed back-to-back, but in Coremark, the Load hit rate is almost 100%, so for this part, try to use speculation to wake up, which can wake up other instructions dependent on Load by 1 beat in advance. If it is found that the Load accesses CacheMiss, it is cancelled and retransmitted.

[0104] 5) The fifth level optimization is the modification optimization of the underlying logic, that is, the modification optimization of the compiler. The performance of the processor is often determined by two parts, one is the hardware architecture, and the other is the compiler capability. When the hardware architecture cannot be solved, the instruction flow needs to be analyzed according to the program characteristics, and the appropriate extension instruction or self-created instruction is selected for corresponding optimization design.

[0105] Specifically, as an embodiment, the specific optimization process is as follows:

[0106] (1) Discovering that there is a matrix loop (continuous Load / Store access) in the hotspot function: the RISC-V basic instruction set is biased towards scalar operations, and the efficiency is limited for large-scale data parallelism (such as matrix operation, image processing, etc.). As in Linpack, SPECINT, and other Benchmark, it is found that a large number of loop matrix multiplication, vector addition, and other operations are compiled into multiple scalar instructions, and the overall number of instructions is large and the efficiency is low. In view of this situation, the Vector extension (V extension) is introduced to optimize matrix / vector operations.

[0107] (2) In Coremark and other embedded Benchmark, a large number of bit operations (such as bit shift, bit mask, cyclic redundancy check CRC, etc.) are commonly used. The RISC-V native basic instruction set is not efficient in processing complex bit operations. Complex bit operations can be completed by one instruction, and the original loop of multiple general instructions is greatly simplified, and the Coremark score is improved. In view of this situation, special bit operation instructions or B extension optimization can be created.

[0108] (3) For some specific random access programs, only a few times are accessed in some address access, but they occupy the cache capacity and replace the remaining effective cache line, so the LoadOnce instruction can be created, LoadOnly but not stored in the cache, and the table entry is temporarily stored in the LSU, discarded after use, and the cache space is purified.

[0109] As an embodiment, for the modification and optimization of the compiler, for example, the RISC-V B extension optimizes Coremark, and the V extension optimizes Linpack and SPECINT, the total number of instructions can be greatly reduced and the performance can be improved under the same function.

[0110] Embodiment 2

[0111] An embodiment of the present disclosure provides a RISC-V super scalar processor structure optimization system based on a Gem5 platform, comprising:

[0112] A test initialization module is configured to set the instruction set architecture and the overall architecture of the RISC-V super scalar processor on Gem5.

[0113] A module division module is configured to divide each pipeline stage into a front-end module, a middle-end module, and a back-end module according to the pipeline characteristics of the overall architecture of the RISC-V super scalar processor.

[0114] The bottleneck positioning module is configured to set performance test parameters for the front end, the middle end and the rear end respectively, perform performance tests on the front end, the middle end and the rear end based on the performance test parameters, and locate the performance bottleneck and the bottleneck position of the processor according to the test results.

[0115] The hierarchical optimization module is configured to perform local architecture optimization adjustment according to the performance bottleneck and the specific bottleneck position, set a progressive multi-level optimization process, perform optimization work on a module-by-module and overall basis for the performance bottleneck and the bottleneck position of the RISC-V superscalar processor, and complete the optimization modeling process of the RISC-V superscalar processor.

[0116] The progressive multi-level optimization process includes five progressive levels of optimization, including local parameter fine-tuning, local algorithm optimization, linkage modification from a local module to an adjacent module, modification of an overall pipeline, and modification of a bottom logic, to realize an optimization process of the processor from a local module to an overall architecture.

[0117] Embodiment 3

[0118] In an embodiment of the present disclosure, a computer program product is provided, which includes a computer program that, when executed by a processor, implements the RISC-V superscalar processor structure optimization method based on the Gem5 platform.

[0119] Embodiment 4

[0120] In an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided, which is configured to store computer instructions that, when executed by a processor, implement the RISC-V superscalar processor structure optimization method based on the Gem5 platform.

[0121] Embodiment 5

[0122] In an embodiment of the present disclosure, an electronic device is provided, which includes a processor, a memory and a computer program. The processor is connected to the memory, and the computer program is stored in the memory. When the electronic device is running, the processor executes the computer program stored in the memory, so that the electronic device performs the RISC-V superscalar processor structure optimization method based on the Gem5 platform.

[0123] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks. Figure 1 one or more flow or blocks.

[0124] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flow or blocks. Figure 1 one or more flow or blocks.

[0125] Although the present disclosure has been described with reference to the embodiments thereof, it is apparent that a variety of modifications or changes can be made thereto without departing from the scope of the present disclosure.

Claims

1. A performance optimization method for a RISC-V superscalar processor based on the Gem5 platform, characterized in that: include: Setting the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5; According to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor, each pipeline stage is divided into front-end modules, mid-end modules and back-end modules; Setting performance test parameters for the front end, the middle end, and the back end respectively, performing performance tests on the front end, the middle end, and the back end based on the performance test parameters, and locating processor performance bottlenecks and bottleneck locations according to the test results; Perform local architecture optimization and adjustments based on performance bottlenecks and specific bottleneck locations, set up a progressive multi-level optimization process, perform modular and overall optimization work on the performance bottlenecks and bottleneck locations of the RISC-V superscalar processor, and complete the optimization modeling process of the RISC-V superscalar processor; Among them, the progressive multi-level optimization process includes progressive five-level optimization, including local parameter fine-tuning, local algorithm optimization, local to adjacent module linkage modification, overall pipeline modification and bottom logic modification, realizing the optimization process of the processor from local modules to the overall architecture.

2. The RISC-V superscalar processor performance optimization method based on the Gem5 platform according to claim 1, characterized in that: Set the instruction set architecture and perform instruction set testing on the RISC-V superscalar processor to test whether the processor can support all required instruction sets; and perform preliminary tests of various benchmarks on the RISC-V superscalar processor to check whether various benchmarks can be executed correctly. The above two types of tests are correctness tests of the RISC-V superscalar processor.

3. The RISC-V superscalar processor performance optimization method based on the Gem5 platform according to claim 1, characterized in that: The testing process starts from the whole and then goes to the part. First, the correctness test of the entire RISC-V superscalar processor is carried out, and then the performance test of the local front-end module, mid-end module and back-end module is carried out. The local performance test is the third type of test, which gradually tests and locates the performance bottleneck and the location of the performance bottleneck. Among them, after the front-end module performance test, the information obtained includes the miss rate of the instruction cache, the branch instruction prediction error rate, the average number of valid instructions after passing through the BPU, and the average number of instructions decoded per cycle.

4. The RISC-V superscalar processor performance optimization method based on the Gem5 platform according to claim 3, characterized in that: After the mid-range module performance test, the information obtained includes the number of register rename stalls, the number of instructions in each dispatch queue, the utilization of each dispatch queue, the number of stalls in each dispatch queue, the number of instructions in each issue queue, the utilization of each issue queue, the number of stalls in each issue queue, and the number of instructions issued per cycle for each instruction type. After the back-end module performance test, the information obtained includes the number of cycles from the issuance of the Load instruction to the write-back, the miss rate of the data cache, the number of times the Load and Store Instruction Queue is full, the utilization rate of the Load and Store Instruction Queue, the number of times the ROB is full, the number of instructions submitted to bottleneck retirement per cycle, the number of waiting cycles that cannot be submitted to the ROB head, and the number of cycles that can be retired but do not reach the head.

5. The RISC-V superscalar processor performance optimization method based on the Gem5 platform according to claim 1, characterized in that: The first level of optimization involves fine-tuning local parameters. When timing and area permit, the table entry capacity parameters are increased to observe performance changes. When parameter tuning fails to resolve the issue, the second level of optimization is used to upgrade the branch prediction algorithm from a simple 2-bit counter to a TAGE branch predictor. TAGE uses a multi-level history length table to capture branch dependencies. Each level of table entry has a different history length to capture both short-term and long-term branch behaviors. The TAGE algorithm is implemented using the Gem5 simulator.

6. The RISC-V superscalar processor performance optimization method based on the Gem5 platform according to claim 1, characterized in that: The third level of optimization involves modifying the linkage between local modules and adjacent modules, optimizing the linkage between emission and execution. In the emission queue, STD is allowed to independently transmit to LSU in advance when conditions are met, eliminating the need to wait for STA. The AG process is moved from the end of the memory access pipeline to the emission arbitration stage, obtaining the physical address in advance and enabling parallel access to the TLB and D-Cache.

7. RISC-V superscalar processor performance optimization system based on Gem5 platform, characterized by: include: Test initialization module, used to set the instruction set architecture and the overall architecture of the RISC-V superscalar processor on Gem5; A module division module is used to divide each pipeline stage into a front-end module, a mid-end module, and a back-end module according to the pipeline characteristics of the overall architecture of the RISC-V superscalar processor; A bottleneck locating module is used to set performance test parameters for the front-end, mid-end and back-end respectively, perform performance tests on the front-end, mid-end and back-end based on the performance test parameters, and locate the processor performance bottleneck and the bottleneck location according to the test results; The hierarchical optimization module is used to optimize and adjust the local architecture according to the performance bottlenecks and specific bottleneck locations, set up a progressive multi-level optimization process, and perform modular and overall optimization work on the performance bottlenecks and bottleneck locations of the RISC-V superscalar processor to complete the optimization modeling process of the RISC-V superscalar processor; wherein, the progressive multi-level optimization process includes progressive five-level optimization, including local parameter fine-tuning, local algorithm optimization, local to adjacent module linkage modification, overall pipeline modification and bottom logic modification, to realize the optimization process of the processor from local modules to the overall architecture.

8. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the RISC-V superscalar processor performance optimization method based on the Gem5 platform according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium is used to store computer instructions. When the computer instructions are executed by the processor, the RISC-V superscalar processor performance optimization method based on the Gem5 platform as described in any one of claims 1 to 6 is implemented.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program; wherein the processor is connected to the memory, the computer program is stored in the memory, and when the electronic device is running, the processor executes the computer program stored in the memory to enable the electronic device to implement the RISC-V superscalar processor performance optimization method based on the Gem5 platform as described in any one of claims 1 to 6.

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