Processor architecture and method based on dynamic override instruction stream

Abstract

A processor architecture and method based on dynamic overwritten instruction stream, relate to the technical field of quantum computing. The processor architecture is used for quantum computing, and the processor architecture comprises a processor core, an instruction storage module, a state detection module, a dynamic instruction modification module and a dynamic scheduling coordination module. The instruction storage module comprises a first port and a second port, the first port is used for loading the main program instruction stream of the processor core; the state detection module acquires the current address of the current instruction stream of the processor core in real time; the dynamic instruction modification module determines the target updated instruction stream of the processor core according to the received quantum computing input signal; the dynamic scheduling coordination module judges whether the current address is less than the starting address of the target updated instruction stream; if yes, the dynamic instruction modification module writes the target updated instruction stream into the target address interval of the instruction storage module through the second port, so that the processor core executes the target updated instruction stream. The processor architecture has high response speed and control accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, in particular, to a processor architecture and method based on dynamic overwrite instruction stream. BACKGROUND

[0002] Quantum computing puts forward high performance requirements on classical electronic control time precision, response timeliness, dynamic instruction scheduling, etc. In particular, in the scenarios of quantum error correction and adaptive feedforward control according to changes in the external environment, the processor needs to directly schedule quantum circuits for execution within the coherence time scale of the quantum bits, and flexibly and efficiently adjust the main program instruction stream according to the real-time changes in the error correction decoding results and the environmental parameters, so as to meet the needs of real-time feedback control and dynamic instruction stream adjustment.

[0003] In view of the two core requirements of quantum computing on the special-purpose processor, one is real-time monitoring and scheduling of instruction execution. The external system needs to have the tracking ability of the processor execution progress, accurately know the current program counter (PC) position, and pause or start the processor instruction execution at a specific instruction position, so as to prevent the execution of outdated instruction sequences.

[0004] The other is to dynamically modify the future instruction stream during the execution of quantum computing. The quantum error correction decoder and the environmental parameter change feedforward module dynamically generate a new instruction stream and load it into the special-purpose processor instruction memory, which covers or inserts the part of the program that has not been executed, so as to realize the dynamic reconstruction of the instruction stream.

[0005] In order to meet the above two core requirements, there are two types of technologies in the prior art. The first type is multi-path program design based on jump logic. All possible instruction paths are written into the instruction memory in advance, and different paths are executed by selecting jump instructions during running. However, in the complex quantum information processing scenario, the processor may face highly dynamic and unpredictable state changes, and the number of possible states increases exponentially with the number of quantum bits, making it difficult to enumerate all possible control paths in advance. This method not only brings a large number of redundant instructions to occupy limited instruction storage resources, but also lacks the ability to generate new instructions flexibly at runtime, making it difficult to achieve truly dynamic instruction stream modification.

[0006] The second type is the partial reconfiguration function based on FPGA. During the running of the processor, the logic of a certain region of the FPGA is reconfigured, so that the processor can dynamically switch the function hardware IP or instruction extension logic for different stages or tasks. In the microarchitecture of the processor, a new instruction implementation module is loaded through partial reconfiguration at runtime. This module acts as the execution path of the customized instruction when the processor is executed, achieving the purpose of extending or modifying the instruction set architecture (ISA).

[0007] However, the method can only reconfigure part or all of the functional IP in the FPGA, and cannot modify the instruction stream in the specific IP. The instruction stream in the reconfigured IP is also predefined and not dynamically generated as the experiment progresses, which is not suitable for real-time insertion, modification or deletion of instructions at the instruction level. At the same time, the reconfiguration process takes a long time and is not suitable for real-time control systems that are sensitive to time. In addition, the method lacks the ability to generate instructions at runtime, and existing hardware reconfiguration mechanisms rely on predefined configuration files and cannot dynamically generate new control logic or instruction streams based on real-time data or feedback generated by the experiment.

[0008] The two types of methods described above do not fully meet the two core requirements of the quantum computing dedicated processor.

[0009] The contents of the background art section only represent the knowledge of the discloser and do not necessarily represent the prior art in the field. SUMMARY

[0010] The present application aims to provide a processor architecture and method based on dynamic overwrite instruction stream to solve the problem that the two core requirements of the quantum computing dedicated processor are not fully met in the prior art.

[0011] According to an aspect of the present application, the present application provides a processor architecture based on dynamic overwrite instruction stream, which is used for quantum computing. The processor architecture can include a processor core, an instruction storage module, a state detection module, a dynamic instruction modification module, and a dynamic scheduling and coordination module. The instruction storage module stores the entire instruction stream of the processor core, and includes a first port and a second port. The first port is used to load the main program instruction stream of the processor core. The state detection module obtains the current address of the current instruction stream of the processor core in real time. The dynamic instruction modification module determines the target updated instruction stream of the processor core according to the received quantum computing input signal. The dynamic scheduling and coordination module determines whether the current address is less than the starting address of the target updated instruction stream. The dynamic instruction modification module writes the target updated instruction stream into the target address interval of the instruction storage module through the second port in the case that the dynamic scheduling and coordination module determines that the current address is less than the starting address of the target updated instruction stream, so that the processor core executes the target updated instruction stream.

[0012] According to some embodiments of the present application, the state detection module obtains the count value of the program counter of the current instruction stream, and the state detection module determines the current address according to the count value of the program counter.

[0013] According to some embodiments of the present application, the quantum computing input signal at least includes: target task data, program count value, and count value of the program counter of the current instruction stream.

[0014] According to some embodiments of the present application, the dynamic scheduling coordination module determines whether a difference between the target write address of the target update instruction stream and the current address satisfies a preset difference condition; the dynamic instruction modification module directly writes the target update instruction stream to the target address interval through the second port to enable the processor core to execute the target update instruction stream, in a case where the dynamic scheduling coordination module determines that the difference satisfies the preset difference condition; and the dynamic instruction modification module writes the target update instruction stream to the target address interval through the second port to enable the processor core to execute the target update instruction stream after suspending the reading of the instruction stream by the processor core, in a case where the dynamic scheduling coordination module determines that the difference does not satisfy the preset difference condition.

[0015] According to some embodiments of the present application, the preset difference condition is that the difference between the target write address of the target update instruction stream and the current address is greater than or equal to 10.

[0016] According to an aspect of the present application, the present application provides an execution method of a processor architecture based on a dynamically overwritten instruction stream, the processor architecture being used for quantum computing, the method comprising: acquiring a current address of a current instruction stream of a processor core in real time; determining a target update instruction stream of the processor core according to a received quantum computing input signal; determining whether the current address is less than a start address of the target update instruction stream; and writing the target update instruction stream to a target address interval to enable the processor core to execute the target update instruction stream, if so.

[0017] According to some embodiments of the present application, the step of acquiring the current address of the current instruction stream of the processor core in real time comprises: acquiring a count value of a program counter of the current instruction stream; and determining the current address according to the count value of the program counter.

[0018] According to some embodiments of the present application, the quantum computing input signal at least comprises: target task data, a program count value and a count value of a program counter of the current instruction stream.

[0019] According to some embodiments of the present application, the step of writing the target update instruction stream to the target address interval to enable the processor core to execute the target update instruction stream comprises: determining whether a difference between a target write address of the target update instruction stream and the current address satisfies a preset difference condition; directly writing the target update instruction stream to the target address interval to enable the processor core to execute the target update instruction stream, if so; and writing the target update instruction stream to the target address interval to enable the processor core to execute the target update instruction stream after suspending the reading of the instruction stream by the processor core, if not.

[0020] According to some embodiments of the present application, the preset difference condition is that the difference between the target write address of the target update instruction stream and the current address is greater than or equal to 10.

[0021] According to another aspect of the present application, the present application further provides a non-volatile computer readable storage medium, having stored thereon a computer program, which, when executed by a processor, enables the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0022] According to another aspect of the present application, the present application further provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, which, when executed by the one or more processors, enable the one or more processors to implement the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0023] According to another aspect of the present application, the present application further provides a computer program product, comprising: a computer program stored on a computer readable storage medium; the computer program comprising program instructions, which, when executed by a computer, cause the computer to perform the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0024] The technical solution of the present application can obtain the current address of the current instruction stream of the processor core in real time, determine the target updated instruction stream of the processor core through the quantum computing input signal, and judge whether the current address is less than the starting address of the target updated instruction stream. In the case that the current address is less than the starting address of the target updated instruction stream, the target updated instruction stream is written to the target address interval, so that the processor core executes the target updated instruction stream.

[0025] The processor architecture of the present application has the dynamic instruction modification module of the hardware to generate and overwrite the instruction segment that has not been executed in real time according to the input signal during the running of the processor core, which realizes the online updating and replacing of the main program instruction stream that the traditional processor architecture cannot complete, is suitable for the control system with strong environmental dynamics, has the flexibility of the traditional software self-repairing code and the high performance of the FPGA hardware partial reconfiguration, and has high response speed and control accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A structural schematic diagram of a processor architecture according to an embodiment of the present application is shown;

[0028] Figure 2A flowchart illustrating a method 1000 according to an embodiment of the present application is shown;

[0029] Figure 3 A flowchart illustrating step S100 according to an embodiment of the present application is shown;

[0030] Figure 4 A flowchart illustrating step S400 according to an embodiment of the present application is shown.

[0031] BRIEF DESCRIPTION OF DRAWINGS

[0032] Processor architecture 20; processor core 21; instruction storage module 22; state detection module 23; dynamic instruction modification module 24; dynamic scheduling coordination module 25. DETAILED DESCRIPTION

[0033] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will not be repeated.

[0034] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, methods, devices, implementations, materials, and so forth have not been described in detail in order to avoid obscuring aspects of the present disclosure.

[0035] Furthermore, the term "comprising" and "including" and their variants are intended to cover both the case where only the stated elements are present and the case where additional elements are present. For example, a process, method, system, product, or apparatus that comprises or includes one or more steps or units is not limited to only those steps or units, but can also include additional steps or units that are not listed.

[0036] The terms "first", "second", and the like, in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms "first", "second", etc., are to be interpreted, by those skilled in the art, as a structural or functional pertinence but not a chronological or sequential pertinence.

[0037] With reference to the drawings, the technical solutions of the present application will be described clearly and completely in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0038] The following are the English and its English full name and corresponding Chinese interpretation involved in the present application.

[0039] PC, Program Counter, program counter.

[0040] FPGA, Field-Programmable Gate Array, field-programmable gate array.

[0041] IP, Intellectual Property, IP core.

[0042] ISA, Instruction Set Architecture, instruction set architecture.

[0043] BRAM, Block Random-Access Memory, block random access memory.

[0044] RISC-V, Reduced Instruction Set Computer V, fifth generation reduced instruction set.

[0045] Referring to Figure 1 The processor architecture 20 based on dynamic overwritten instruction stream provided by the present application can include a processor core 21, an instruction storage module 22, a state detection module 23, a dynamic instruction modification module 24 and a dynamic scheduling coordination module 25. The processor architecture 20 can be used in the application scenario of quantum computing.

[0046] With reference to Figure 1 The execution method 1000 of the processor architecture based on dynamic overwritten instruction stream provided by the present application is described below.

[0047] Referring to Figure 2 The method 1000 can include steps S100-S400.

[0048] In step S100, the current address of the current instruction stream of the processor core is acquired in real time.

[0049] According to an example embodiment, the instruction storage module 22 stores the entire instruction stream of the processor core 21, and the instruction storage module 22 includes at least a first port and a second port, the first port is used to load the main program instruction stream of the processor core 21. The second port can be used for the processor core 21 to read the instruction stream and overwrite the instruction stream by the dynamic instruction modification module.

[0050] For example, the instruction storage module 22 can be a dual-port BRAM resource inside the FPGA. The first port is an initialization loading port, which is used for the external processing system to load the main program instruction stream. The second port is a runtime access port, which is used for the processor core 21 to read the instruction stream and overwrite the instruction stream by the dynamic instruction modification module.

[0051] The second port can also be provided with two, one second port is a read port, which is used for the processor core 21 to read the instruction stream, and the other second port is a write port, which is used for the dynamic instruction modification module 24 to overwrite the instruction stream. The two second ports can be accessed at the same time.

[0052] The processor core 21 can be a physical unit that independently executes an instruction sequence (thread). The processor core 21 can be based on a custom instruction set architecture, and adopts a five-stage pipeline structure to achieve efficient instruction execution and peripheral control, and meet the timing control requirements in quantum computing experiments. For example, the processor core 21 can be based on the RISC-V basic instruction set, and extend a special instruction set subset optimized for control tasks. The processor core 21 can adopt a five-stage pipeline structure to improve the processing efficiency and throughput capacity of the instruction stream. The internal pipeline structure does not use a cache mechanism, simplifies the execution model, and is suitable for real-time applications with high requirements for determinism and controllability.

[0053] The current instruction stream can be a dynamic instruction sequence that the processor core fetches, decodes, and executes at a runtime. The current address can be an address corresponding to the current instruction stream.

[0054] For example, in step S100, the state detection module 23 can obtain the current address of the current instruction stream of the processor core in real time.

[0055] The state detection module 23 can determine the current address by obtaining the count value of the program counter of the current instruction stream.

[0056] In step S200, according to the received quantum computing input signal, the target updated instruction stream of the processor core is determined.

[0057] According to an example embodiment, the quantum computing input signal can be quantum information sent by an external device for the processor core to operate.

[0058] Optionally, the quantum computing input signal can include target task data, a program count value, and a count value of the program counter of the current instruction stream.

[0059] Target task data can be target processing data for a specific quantum computing task. Program counter value can be a counter value (timestamp). The count value of the program counter of the current instruction stream can be the current control program execution location (PC) of the processor core.

[0060] Target update instruction stream can be the instruction sequence to be executed by the processor core generated according to the quantum computing input signal.

[0061] For example, in step S200, the dynamic instruction modification module 24 determines the target update instruction stream of the processor core according to the received quantum computing input signal. The dynamic instruction modification module can generate the target update instruction stream according to the quantum computing input signal and the preset signal generation rule.

[0062] For example, in the mid-circuit feedback scenario, the target task data can be the result of the intermediate circuit measurement (0 or 1, detected and analyzed by an external quantum state detection module). The quantum computing input signal can include the result of the intermediate circuit measurement 0 or 1, the counter value (timestamp) and the current control program execution location (PC). The dynamic instruction modification module 24 can generate the target update instruction stream to be executed according to the preset feedback rule according to the result of the intermediate circuit measurement 0 or 1. For example, the result of the intermediate circuit measurement is 1, and the target update instruction stream is to insert an X gate; the result of the intermediate circuit measurement is 0, and the target update instruction stream is to insert an I gate. The generation method of the target update instruction stream can include lookup table and conditional instruction template, etc.

[0063] For another example, in the quantum error correction scenario, the target task data can be the measurement result of the syndrome in the quantum error correction code. The quantum computing input signal can include the measurement result of the syndrome in the quantum error correction code, the counter value (timestamp) and the current control program execution location (PC), and the quantum computing input signal can also include error model parameters, encoding scheme information and quantum error correction round information. The dynamic instruction modification module 24 can determine which Pauli error correction operation needs to be executed according to the syndrome, and the implementation method includes fast decoding algorithm and neural network inference method, etc. The dynamic instruction modification module 24 can further combine other information in the quantum computing input signal to construct a legal target update instruction stream.

[0064] In step S300, it is judged whether the current address is less than the start address of the target update instruction stream.

[0065] According to an example embodiment, the start address of the target update instruction stream can be the start storage address of the target update instruction stream in the instruction storage module 22. The dynamic scheduling coordination module 25 can determine whether the current address is less than the start address of the target update instruction stream, so that the target update instruction stream can be written into the instruction address of the instruction storage module that has not been executed.

[0066] In a case where it is determined that the current address is greater than or equal to the start address of the target update instruction stream, it indicates that the target update instruction stream has been executed or entered the pipeline, at this time, for safety consideration, the dynamic modification operation should be stopped.

[0067] In a case where it is determined that the current address is less than the start address of the target update instruction stream, step S400 is executed.

[0068] In step S400, the target update instruction stream is written into the target address interval, so that the processor core executes the target update instruction stream.

[0069] According to an example embodiment, the target address interval can be the address interval in which the target update instruction stream is written into the instruction storage module. The target address interval is within the instruction address of the instruction storage module that has not been executed.

[0070] For example, in step S400, the dynamic instruction modification module 24 writes the target update instruction stream into the target address interval of the instruction storage module through the second port. The processor core 21 can execute the target update instruction stream to complete the operation (such as insertion, replacement or deletion operation, etc.) of the target update instruction stream.

[0071] Through the above embodiment, the technical scheme of the present application can obtain the current address of the current instruction stream of the processor core in real time, determine the target update instruction stream of the processor core through the quantum computing input signal, determine whether the current address is less than the start address of the target update instruction stream, and in a case where the current address is less than the start address of the target update instruction stream, write the target update instruction stream into the target address interval, so that the processor core executes the target update instruction stream.

[0072] The processor architecture of the present application has the instruction flow dynamic modification capability, through the dynamic instruction modification module of the hardware, generates and overwrites the instruction segment that has not been executed in real time according to the input signal when the processor core is running, realizes the online update and replacement of the main program instruction flow that the traditional processor architecture cannot complete, and is suitable for the control system with strong environmental dynamics. At the same time, the processor architecture has the flexibility of traditional software self-repairing code and the high performance characteristics of FPGA hardware partial reconfiguration, and has high response speed and control precision.

[0073] The processor architecture of the present application avoids the high overhead and low timeliness problem of partial reconfiguration, and does not need to reload the logic area, thereby improving the response speed and control accuracy of the processor architecture.

[0074] The processor architecture of the present application can enhance the processing capability of abnormal conditions and unexpected events. In the face of sudden state changes in experiments or dynamic instruction flow requirements, the processor architecture can switch execution strategies and inject target update instruction flow in real time, thereby enhancing the self-recovery and robustness of the processor architecture.

[0075] The processor architecture of the present application can provide efficient computing support for precision experiment control and dynamic feedback systems. The architecture is particularly suitable for scenarios such as quantum experiment control and programmable triggering, and can respond to experiment state changes at the processor level precision, effectively making up for the bottleneck of insufficient control accuracy of general architecture.

[0076] Optionally, referring to Figure 3 , step S100 can include steps S110-S120.

[0077] In step S110, the count value of the program counter of the current instruction flow is obtained.

[0078] According to an example embodiment, the count value of the program counter can be a register value of a memory address in an instruction storage module corresponding to the current instruction flow.

[0079] For example, in step S110, the state detection module 23 obtains the count value of the program counter of the current instruction flow. The state detection module 23 can read the count value of the program counter of the current instruction flow of the processor core.

[0080] In step S120, the current address is determined according to the count value of the program counter.

[0081] According to an example embodiment, the state detection module 23 can determine the current address according to the count value of the program counter. For example, the state detection module 23 can directly take the read count value of the program counter as the current address of the current instruction flow in the BRAM.

[0082] Through the above embodiment, the technical solution of the present application can obtain the count value of the program counter of the current instruction flow, and determine the current address through the program count value.

[0083] The processor architecture of the present application can determine the current address by monitoring the count value of the program counter of the current instruction flow in real time, so as to determine whether the initial address of the target update instruction has entered the pipeline.

[0084] Optionally, referring to Figure 4Step S400 can include steps S410-S430.

[0085] In step S410, it is determined whether a difference between the target write address of the target update instruction stream and the current address satisfies a preset difference condition.

[0086] According to an example embodiment, the target write address can be an instruction address being written of the target update instruction stream. The preset difference condition can be a preset difference threshold between the target write address of the target update instruction stream and the current address.

[0087] Optionally, the preset difference condition can be that the difference between the target write address of the target update instruction stream and the current address is greater than or equal to 10.

[0088] For example, in step S410, the dynamic scheduling coordination module 25 determines whether the difference between the target write address of the target update instruction stream and the current address satisfies the preset difference condition. The dynamic instruction modification module 24 takes a certain time to write the instruction stream to the instruction storage module 22, and the dynamic scheduling coordination module 25 can determine whether to suspend the work of the processor core 21 by the writing of the target update instruction stream, so as to avoid that the processor core 21 reads the un-updated instruction stream.

[0089] In a case where it is determined that the difference between the target write address of the target update instruction stream and the current address satisfies the preset difference condition, step S420 is performed.

[0090] In step S420, the target update instruction stream is directly written to the target address interval, so that the processor core executes the target update instruction stream.

[0091] According to an example embodiment, in a case where it is determined that the difference between the target write address of the target update instruction stream and the current address satisfies the preset difference condition, it indicates that the address distance between the target write address and the current address is far, and the dynamic instruction modification module 24 can directly write the target update instruction stream to the target address interval of the instruction storage module 22 through the second port.

[0092] In a case where it is determined that the difference between the target write address of the target update instruction stream and the current address does not satisfy the preset difference condition, step S430 is performed.

[0093] In step S430, after suspending the reading of the instruction stream by the processor core, the target update instruction stream is written to the target address interval, so that the processor core executes the target update instruction stream.

[0094] According to the example embodiment, when the difference between the target write address of the target update instruction stream and the current address does not satisfy the preset difference condition, it indicates that the address distance between the target write address and the current address is relatively small, and the dynamic instruction modification module 24 writes the target update instruction stream into the target address interval of the instruction storage module 22 through the second port after suspending the work of the processor core 21.

[0095] Through the above embodiments, the technical scheme of the present application can determine whether the work of the processor core needs to be suspended by judging whether the difference between the current address and the target write address of the target update instruction stream satisfies the preset difference condition. In the case that the difference between the current address and the target write address of the target update instruction stream satisfies the preset difference condition, the program behavior can be quickly updated without suspending the entire processor architecture, which significantly improves the response speed and control accuracy of the processor architecture.

[0096] According to another aspect of the present application, the present application also provides a non-volatile computer readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0097] According to another aspect of the present application, the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, which, when executed by the one or more processors, enable the one or more processors to implement the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0098] According to another aspect of the present application, the present application also provides a computer program product, comprising: a computer program stored on a computer readable storage medium; the computer program comprising program instructions, which, when executed by a computer, cause the computer to execute the execution method of the processor architecture based on the dynamic overwritten instruction stream as described above.

[0099] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the above describes the present application in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions of the foregoing embodiments or make equivalent replacements to some technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A processor architecture based on dynamically overwriting instruction streams, the processor architecture for quantum computing, characterized in that, The processor architecture comprises: a processor core; an instruction storage module storing a complete instruction stream of the processor core, the instruction storage module comprising a first port and a second port, the first port being used to load a main program instruction stream of the processor core; a state detection module acquiring a current address of a current instruction stream of the processor core in real time; a dynamic instruction modification module determining a target updated instruction stream of the processor core according to a received quantum computing input signal; a dynamic scheduling coordination module judging whether the current address is less than a start address of the target updated instruction stream; the dynamic instruction modification module, in a case where the dynamic scheduling coordination module judges that the current address is less than the start address of the target updated instruction stream, writing the target updated instruction stream into a target address interval of the instruction storage module through the second port, so that the processor core executes the target updated instruction stream.

2. The architecture of claim 1, wherein, The state detection module acquires a count value of a program counter of the current instruction stream, and the state detection module determines the current address according to the count value of the program counter.

3. The architecture of claim 1, wherein, The quantum computing input signal at least comprises: target task data, a program count value and a count value of a program counter of the current instruction stream.

4. The architecture of claim 1, wherein, The dynamic scheduling coordination module judges whether a difference between a target write address of the target updated instruction stream and the current address satisfies a preset difference condition. The dynamic instruction modification module, in a case where the dynamic scheduling coordination module judges that the difference satisfies the preset difference condition, directly writes the target updated instruction stream into the target address interval through the second port, so that the processor core executes the target updated instruction stream. The dynamic instruction modification module, in a case where the dynamic scheduling coordination module judges that the difference does not satisfy the preset difference condition, after suspending a read instruction stream of the processor core, writes the target updated instruction stream into the target address interval through the second port, so that the processor core executes the target updated instruction stream.

5. The architecture of claim 4, wherein, The preset difference condition is that the difference between the target write address of the target updated instruction stream and the current address is greater than or equal to 10.

6. An execution method of a processor architecture based on dynamically overwriting instruction streams, the processor architecture being used for quantum computing, characterized in that, The method is executed by the processor architecture based on dynamic overwritten instruction stream according to any one of claims 1-5, and the method comprises: acquiring a current address of a current instruction stream of a processor core in real time; determining a target updated instruction stream of the processor core according to a received quantum computing input signal; judging whether the current address is less than a start address of the target updated instruction stream; if yes, writing the target updated instruction stream into a target address interval, so that the processor core executes the target updated instruction stream.

7. The method of claim 6, wherein, The acquiring a current address of a current instruction stream of a processor core in real time comprises: acquiring a count value of a program counter of the current instruction stream; determining the current address according to the count value of the program counter.

8. The method of claim 6, wherein, The quantum computing input signal at least comprises: target task data, a program count value and a count value of a program counter of the current instruction stream.

9. The method of claim 6, wherein, The writing of the target update instruction stream to the target address interval, so that the processor core executes the target update instruction stream, comprises: determining whether a difference between a target write address of the target update instruction stream and the current address satisfies a preset difference condition; if yes, directly writing the target update instruction stream to the target address interval, so that the processor core executes the target update instruction stream; if no, after suspending a read instruction stream of the processor core, writing the target update instruction stream to the target address interval, so that the processor core executes the target update instruction stream.

10. The method of claim 9, wherein, The preset difference condition is that the difference between the target write address of the target update instruction stream and the current address is greater than or equal to 10.

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