Layout design rule checking method, system, device, medium and product

Abstract

The application relates to an application method of a GPU in a design rule check in the field of integrated circuits, in particular to a layout design rule check method, system, device, medium and product. The steps of the layout design rule check method are as follows: inputting initial layout data, analyzing a design rule check task to be executed, and marking the priority and complexity level of the task. Based on the region characteristics of the layout data, the layout data is divided into multiple data blocks according to regions, and the task and the corresponding data block are distributed to GPU computing cores according to the task priority and complexity level. After the GPU computing cores complete the data block processing, new data blocks are distributed according to the overall load of the GPU computing cores, the above steps are repeated until all tasks are executed, and the layout design rule check result is output. The system, computer device, computer readable storage medium and computer program product of the application have the same beneficial effects as the layout design rule check method.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a layout design rule checking method, system, device, medium and product. BACKGROUND

[0002] In the field of integrated circuit design, design rule checking is a key link to ensure the yield of chip manufacturing. With the evolution of semiconductor technology to advanced processes, the scale and complexity of integrated circuit layout grow exponentially, and traditional design rule checking methods are difficult to meet the demand in efficiency and accuracy. Graphics Processing Unit (GPU) provides a new way to accelerate design rule checking with its powerful parallel computing capability. By processing a large amount of data in parallel, the checking time can be significantly shortened.

[0003] However, in practical applications, there is a serious problem of uneven load when applying GPU to design rule checking. On the one hand, design rule checking tasks are diverse, such as geometry size checking, spacing checking, and interlayer connection checking, with significant differences in computational complexity. The layout area with simple rule shapes has small computational load, while the complex irregular structure requires a large number of geometric operations and Boolean operations, resulting in uneven load of GPU computing cores. On the other hand, the density and scale of integrated circuit layout data are different in different areas, with large and complex data volume in key functional modules and small and simple data volume in auxiliary modules, which easily causes load imbalance of GPU computing cores when distributing tasks according to physical distribution.

[0004] In addition, traditional static task allocation strategies only divide computing tasks according to task types or data areas, which cannot adapt to dynamic changes in task execution and cannot meet the needs of design rule checking task diversity and complexity, seriously affecting the utilization of GPU computing resources and the processing efficiency of design rule checking tasks. SUMMARY

[0005] To solve the technical problem of uneven load of GPU computing cores caused by differences in task complexity, unevenness in data scale, and limitations of traditional static allocation strategies in the process of applying existing GPU to design rule checking, the present application provides a layout design rule checking method, system, device, medium and product.

[0006] The present invention provides a layout design rule checking method, comprising the following steps: inputting initial layout data and a design rule file; parsing the design rule file to obtain all design rule checking tasks to be executed; marking each design rule checking task with priority and complexity level according to the task type and characteristics of the layout area involved; dividing the layout data into multiple data blocks according to the region characteristics of the initial layout data; monitoring the load of the GPU computing core in real time, and allocating the design rule checking tasks and their corresponding data blocks to the GPU computing core according to the priority and complexity level of the design rule checking tasks; after the GPU computing core completes the data block processing, it processes the data blocks according to the GPU computing core's performance. Assign new design rule check tasks and their corresponding data blocks based on the overall load of the computing core; repeat the above task assignment steps until all design rule check tasks are completed, and output the layout design rule check results; wherein, the priority of the design rule check tasks is marked according to at least one of the following information: the dependency relationship between tasks, whether the layout data area involved in the task belongs to the routing part or the fixed cell layout part, whether the task belongs to the basic rule check or the complex rule check; and / or, the complexity level of the design rule check tasks is marked according to at least one of the following information: the size of the layout data area involved in the task, the routing density of the layout data area involved in the task, and the complexity of the rules checked by the task.

[0007] Preferably, the characteristics of the layout data region include the computational complexity of the layout data, and the data block size of the layout data region with high computational complexity is smaller than the data block size of the region with low computational complexity.

[0008] Preferably, when processing the design rule checking task in the GPU computing core, the following steps are also included: real-time monitoring of the GPU computing core, and when the load of the GPU computing core exceeds a preset threshold, migrating some tasks of the high-load GPU computing core to the low-load GPU computing core.

[0009] Preferably, the priority and complexity level of the design rule tasks are adjusted according to the load of the GPU computing core, and / or the size of the data block in the layout data area is adjusted.

[0010] Preferably, the load status of the GPU computing core includes at least one of the following load information: number of completed tasks, estimated remaining time of the current task, video memory utilization, computing core utilization, task execution queue length, and memory access frequency.

[0011] The application further provides a layout design rule checking system, which comprises a user terminal and a micro-service terminal in communication connection; the micro-service terminal receives a to-be-processed command input by the user terminal and executes the steps of the layout design rule checking method according to the to-be-processed command.

[0012] The application further provides a computer device comprising a storage, a processor and a computer program stored on the storage; the processor executes the computer program to implement the steps of the layout design rule checking method.

[0013] The application further provides a computer readable storage medium, which stores a computer program; the computer program implements the steps of the layout design rule checking method when executed by a processor.

[0014] The application further provides a computer program product, which comprises a computer program; the computer program implements the steps of the layout design rule checking method when executed by a processor.

[0015] Compared with the prior art, the layout design rule checking method, system, device, medium and product provided by the application have the following advantages:

[0016] 1. The layout design rule checking method provided by the application overcomes the technical problem that, in the prior art, the GPU is applied to the design rule checking process, and the GPU computing cores are unbalanced in load due to the difference in task complexity, the imbalance in data size and the limitation of the traditional static allocation strategy. Specifically, the layout design rule checking method divides priorities of all design rule checking tasks based on a dependency relationship, a region feature involved, and a complexity of a rule involved by the task before performing the design rule checking, and determines an execution sequence of each design rule checking task before the task is allocated to the GPU computing core. The complexity level of the task is further divided based on a size of a layout region involved by the task, a wiring density of the layout region, and a rule complexity of the task checking, and the complexity level provides an accurate basis for subsequent dynamic load balancing by being divided in advance.

[0017] Further, the layout data is divided into a plurality of data blocks according to regions, and the data blocks corresponding to the tasks are allocated to the GPU computing cores for processing according to the priorities and the complexity levels of the tasks, so that the computing load in the data blocks allocated to each GPU computing core is relatively balanced, and local task backlog and core idling caused by the difference in complexity of the layout regions are effectively avoided. After the data blocks are processed, new design rule checking tasks are allocated according to the overall load of the GPU computing cores, so that the load of the GPU computing cores is maintained relatively balanced.

[0018] In addition, the layout design rule checking method provided by the application can automatically optimize the task allocation strategy and data processing mode according to the priority, complexity and data size of the task. Whether the data area with simple structure or the layout of the complex key function module is processed, the load of each computing core can be balanced, and the stable operation of the system can be ensured.

[0019] 2. The layout design rule checking method provided by the embodiment of the application is based on the calculation complexity of the layout data, and the data block size of the layout data area with high calculation complexity is smaller than that of the layout data area with low calculation complexity. That is, each data block contains fewer layout units for the layout data area with high calculation complexity, and each data block contains more layout units for the layout data area with low calculation complexity. By dividing the layout data area into data blocks with different sizes based on the calculation complexity, the calculation load is pre-balanced at the data level, and each GPU computing core is provided with task units with similar calculation amounts, thereby laying the foundation for efficient parallelism, effectively eliminating the local performance bottleneck caused by the traditional uniform block division, and significantly improving the overall utilization efficiency of hardware resources. Further, by dynamically allocating data blocks, the amount of data processed by each computing core in a period of time and the calculation complexity are relatively balanced.

[0020] 3. The layout design rule checking method provided by the embodiment of the application further comprises real-time monitoring of the GPU computing core, and when it is confirmed that the load of the GPU computing core exceeds the preset threshold, part of the task of the GPU computing core with high load is migrated to the GPU computing core with low load. By real-time monitoring of the load of the GPU computing core and adjusting the allocation of the task, the long-term accumulation of the task in the GPU computing core with high load and the idle state of the GPU computing core with low load are avoided, so that the load imbalance of the GPU computing core is avoided, and the overall processing speed of the task is seriously slowed down.

[0021] 4. The layout design rule checking method provided by the embodiment of the application adjusts the priority and / or complexity level of the design rule checking task and / or the data block size of the layout data area when the load of the GPU computing core exceeds the preset threshold. Through this adaptive adjustment mechanism, the system can dynamically respond to the runtime load fluctuation, optimize the task scheduling and resource allocation strategy in real time, thereby continuously maintaining the efficient load balance among the GPU computing cores, and significantly improving the adaptability to different layout checking tasks and the overall stability of the system.

[0022] 5. The method for checking layout design rules provided by the embodiment of the present application, by acquiring the load information of the GPU computing core, including the number of completed tasks, the estimated remaining time of the current task, the utilization rate of the display memory, the utilization rate of the computing core, the length of the task execution queue, and the memory access frequency, the overall load of the GPU computing core is judged from multiple aspects, so as to realize more accurate task allocation and data processing.

[0023] 6. The system for checking layout design rules provided by the embodiment of the present application, the system comprises a user terminal and a micro service terminal in communication connection; the micro service terminal receives the inputted processing command of the user terminal, and executes the steps of the above-mentioned method for checking layout design rules according to the processing command.

[0024] It should be noted that the system for checking layout design rules provided by the present application has the same beneficial effects as the above-mentioned method for checking layout design rules, which will not be repeated here.

[0025] 7. The computer device provided by the embodiment of the present application comprises a storage, a processor, and a computer program stored on the storage, the processor executes the computer program to realize the steps of the above-mentioned method for checking layout design rules.

[0026] It should be noted that the computer device provided by the present application has the same beneficial effects as the above-mentioned method for checking layout design rules, which will not be repeated here.

[0027] 8. The computer readable storage medium provided by the embodiment of the present application has a computer program stored thereon, the computer program realizes the steps of the above-mentioned method for checking layout design rules when executed by the processor.

[0028] It should be noted that the computer readable storage medium provided by the present application has the same beneficial effects as the above-mentioned method for checking layout design rules, which will not be repeated here.

[0029] 9. The computer program product provided by the embodiment of the present application comprises a computer program, the computer program realizes the steps of the above-mentioned method for checking layout design rules when executed by the processor.

[0030] It should be noted that the computer program product provided by the present application has the same beneficial effects as the above-mentioned method for checking layout design rules, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0032] Figure 1 is a flowchart of steps S1 to S5 in a layout design rule checking method provided by an embodiment of the present application.

[0033] Figure 2 is a layout data block diagram of a layout design rule checking method provided by an embodiment of the present application.

[0034] Figure 3 is a flowchart of judging whether a GPU exceeds a preset threshold in a layout design checking method provided by an embodiment of the present application.

[0035] Figure 4 is a framework diagram of a layout design rule checking system provided by an embodiment of the present application.

[0036] Figure 5 is a framework diagram of a computer device provided by an embodiment of the present application.

[0037] Figure 6 is a framework diagram of a computer readable storage medium provided by an embodiment of the present application.

[0038] Figure 7 is a framework diagram of a computer program product provided by an embodiment of the present application.

[0039] Explanation of the attached drawings:

[0040] 1. A layout design rule checking system; 11. A user end; 12. A micro-service end;

[0041] 2. A computer device; 21. A storage; 22. A processor;

[0042] 3. A computer readable storage medium;

[0043] 4. A computer program product;

[0044] 100. A computer program;

[0045] A. Layout data; A1. Layout data area with high calculation complexity; A2. Layout data area with low calculation complexity. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the attached drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0047] In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that the determination of B according to A does not mean that B is determined only according to A, but B can also be determined according to A and / or other information.

[0048] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. Those skilled in the art should also know that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0049] In various embodiments of the present application, it should be understood that the size of the sequence number of the above-mentioned processes does not mean the inevitable sequence of execution, and the execution sequence of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0050] In the flowcharts and block diagrams in the drawings of the present application, the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present application are illustrated. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code containing one or more executable instructions for implementing the specified logic function. It should also be noted that in some alternative implementations, the functions marked in the blocks can also occur in a different order from that marked in the drawings. For example, two blocks represented in succession can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, based on the functions involved. It should be particularly noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a special hardware-based system that performs the specified function or operation, or can be implemented by a combination of special hardware and computer instructions.

[0051] In the field of integrated circuit design, when GPU is applied in design rule checking, the tasks are usually allocated according to physical distribution, ignoring the diversity of design rule checking task types and the difference between different task computing complexities. Further, the density and scale of integrated circuit layout data are different in different areas, the data amount of key function modules is large and complex, and the data amount of auxiliary modules is small and simple. Task allocation according to physical distribution is easy to cause load imbalance of GPU computing cores.

[0052] To solve the technical problem that GPU is applied to the design rule checking process, and due to the difference in task complexity, the imbalance in data size, and the limitation of the traditional static allocation strategy, the load of the GPU computing core is unbalanced, the present application provides a layout design rule checking method, system, device, medium and product.

[0053] First, please refer to Figure 1 The embodiment of the present application provides a layout design rule checking method, comprising the following steps:

[0054] S1: input initial layout data and design rule file, parse the design rule file to obtain all design rule checking tasks to be executed, and mark the priority and complexity level of each design rule checking task according to the task type and the features of the involved layout area;

[0055] S2: based on the area features of the initial layout data, the layout data is divided into multiple data blocks according to the area;

[0056] S3: real-time monitoring of the load of the GPU computing core, and distributing the design rule checking task and its corresponding data block to the GPU computing core according to the priority and complexity level of the design rule checking task;

[0057] S4: after the GPU computing core completes the data block processing, the new design rule checking task and its corresponding data block are distributed according to the overall load of the GPU computing core;

[0058] S5: repeat the above steps S3-S4 until all design rule checking tasks are executed, and output the layout design rule checking result.

[0059] It can be understood that the layout design rule checking method provided by the embodiment of the present application overcomes the technical problem that the GPU is applied to the design rule checking process, and due to the difference in task complexity, the imbalance in data size, and the limitation of the traditional static allocation strategy, the load of the GPU computing core is unbalanced.

[0060] Specifically, before performing the design rule checking, the layout design rule checking method divides the priority of all design rule checking tasks based on the dependency relationship, the involved area features, and the complexity of the rules involved by the task, and determines the execution order of each design rule checking task before the task is allocated to the GPU computing core. The complexity level of the task is divided based on the size of the layout area involved by the task, the wiring density of the layout area, and the complexity of the rules checked by the task; by pre-dividing the complexity level, accurate basis is provided for subsequent dynamic load balancing.

[0061] Further, the layout data is divided into multiple data blocks according to regions, and the data blocks corresponding to the tasks are allocated to the GPU computing cores for processing according to the priority and complexity level of the tasks, so that the calculation load in the data blocks allocated to each GPU computing core is relatively balanced, effectively avoiding local task backlog and core idling caused by differences in complexity of the layout regions. After processing the data blocks, new design rule checking tasks are allocated according to the overall load of the GPU computing cores, maintaining the relative balance of the load of the GPU computing cores.

[0062] In addition, the layout design rule checking method provided by the present application can automatically optimize the task allocation strategy and data processing mode according to the changes in the priority, complexity and data size of the tasks. Whether it is processing a simple data region or dealing with a complex key function module layout, the load of each computing core can be balanced to ensure stable operation of the system.

[0063] The specific steps S1 to S5 of the layout design rule checking method will be described below.

[0064] First, in step S1, the initial layout data is input, and all design rule checking tasks to be executed are parsed, and the priority and complexity level of each design rule checking task are marked according to the task type and the characteristics of the design layout region.

[0065] The priority of the design rule checking task is marked according to at least one of the following information: the dependency relationship between tasks, whether the task involves a layout data region belonging to a wiring part or a fixed cell layout part, whether the task belongs to a basic rule check or a complex rule check.

[0066] When checking the design rules of an integrated circuit, the dependency relationship between the design rule checking tasks mainly reflects the mandatory constraints of the execution order. For example, some set rule checking must be based on the completion of the geometric Boolean operation of the related layer; for example, the preparation work for the data after the layout is divided is superior to the checking work of the design rules. This dependency relationship ensures the logical correctness of the checking process and avoids task blocking or errors due to unmet dependencies.

[0067] That is, the priority of the design rule checking task that depends on the previous task is lower than that of the previous task it depends on.

[0068] When the task involves a layout data region belonging to a wiring part, since the wiring part is a part that involves frequent changes later, it has a greater impact on timing, signal integrity, etc., so it is necessary to perform the related design rule checking task as soon as possible to find and repair problems. The layout of the fixed cell part is relatively stable, and the change cost is also high, so the design checking for this area can be performed later.

[0069] Therefore, if the region of the layout data involved in the design rule checking task is a routing portion, the priority of the task is higher than that of a task in which the region of the layout data is a fixed cell layout portion.

[0070] When the design rule checking task involves the checking of basic rules, such as the checking of minimum line width, minimum spacing, etc., the task of this type is simple and fast, and can quickly find obvious errors. When the design rule checking task involves the checking of complex rules, such as the checking of layer-to-layer alignment, electrical rules, etc., the task of this type is time-consuming and may require more computing resources. The priority of the checking task of the basic rules is higher than that of the checking task of the complex rules, which can quickly exclude obvious errors first, and then deeply check complex problems, improve the overall checking efficiency, and avoid wasting resources on the layout with basic errors.

[0071] Based on the dependency relationship between tasks, the region of the layout data involved in the task is a routing portion or a fixed cell layout portion, and finally the priority can be divided into three levels of high, medium and low, combined with the checking of the task rules belonging to basic or complex rules.

[0072] Based on the priority determination mechanism, an efficient and orderly execution sequence can be constructed before the design rule checking task is started, which ensures that critical tasks occupy computing resources first, significantly reduces the delay caused by dependency waiting or error accumulation, optimizes the load distribution of GPU computing cores from the source, and improves the overall checking efficiency and iteration speed.

[0073] The complexity level of the design rule checking task is marked according to at least one of the following information:

[0074] The size of the region of the layout data involved in the task, the routing density of the region of the layout data involved in the task, and the complexity of the rules checked by the task.

[0075] It can be understood that the complexity level of the task involving a large region of layout data is higher than that of the task involving a small region of layout data; the complexity level of the task involving a dense routing region is higher than that of the task involving a simple routing region; the more complex the rules checked by the task, the higher the complexity level.

[0076] The complexity level of the design rule checking task is comprehensively evaluated by the above three aspects, and the complexity level can be divided into three levels of high, medium and low.

[0077] In some preferred embodiments, the system quantifies the final complexity level estimate (Estimated Complexity, EC) of a task by a product model: EC = A × D × R. Wherein A represents the normalized estimate of the size of the layout area involved in the task, D represents the normalized estimate of the wiring density of the area, and R represents the normalized estimate of the complexity of the rule being checked. The system divides the EC values of all tasks into three complexity levels, high, medium and low, according to their distribution. This comprehensive evaluation method avoids the limitations of a single dimension and can more accurately predict the computational load of the task.

[0078] By classifying the complexity level of the task, the computational intensity of each design rule checking task can be predicted, providing a key basis for subsequent GPU resource allocation and dynamic scheduling, thereby fundamentally avoiding the risk of load imbalance and maximizing parallel computing efficiency.

[0079] Based on the analysis of the design rule checking task, the task is divided into different priority and complexity levels before the design rule checking task is executed. For example, high-precision transistor size checking is marked as high priority and high complexity because it directly determines the electrical properties of the device and the calculation involves precise geometric measurement. While the regular interlayer insulation spacing rule is simple and has a relatively minor impact on performance, it is marked as low priority and low complexity. Classifying design rule checking tasks provides basic information for subsequent load balancing allocation.

[0080] Based on the classification of the design rule checking task, a task priority list, a task complexity level label, and a task dependency graph are generated.

[0081] In step S2, the features of the layout data area corresponding to the design rule checking task are obtained, and the layout data is divided into multiple data blocks according to the features.

[0082] The features of the layout data area include the features obtained when classifying the priority and complexity level of the task. By obtaining the associated features of the layout data area and the task, the computational complexity of the layout data area is measured.

[0083] According to the computational complexity of each region of the layout data, the layout data is divided into data blocks of appropriate size to generate a data block list. The data block list includes the layout data area to which the data block belongs, the estimated computational amount, and the associated task ID.

[0084] In some embodiments, when the layout data is divided into blocks, the data block size of a region with high computational complexity is smaller than that of a region with low computational complexity. For example, for a region with high complexity such as a processor core, the division size of the data block is small, and each data block contains fewer layout units; for example, for a simple region such as a power routing, the division size of the data block is large, and each data block contains more layout units.

[0085] Referring to Figure 2 For example, in layout data A, A1 is a region of layout data with high computational complexity, and A2 is a region of layout data with low computational complexity, wherein the data block size of the A1 region is smaller than that of the A2 region.

[0086] By dividing the layout data regions into data blocks of different sizes based on computational complexity, the computational load is pre-balanced at the data level, providing each GPU computing core with task units of similar computational amount, thereby laying the foundation for efficient parallelism, effectively eliminating the local performance bottleneck caused by traditional uniform blocking, and significantly improving the overall utilization efficiency of hardware resources. Further, by dynamically allocating data blocks, the amount of data processed by each computing core is relatively balanced over time.

[0087] In some embodiments, the blocking of the layout data also takes into account its physical continuity, i.e., when dividing the data blocks, layout units that are adjacent in physical location and need to be processed simultaneously by the same design rule check are preferentially divided into the same data block. This effectively ensures that most of the data required for geometric rule checking is completed within a single data block, minimizing cross-block data access, transmission, and synchronization operations caused by processing boundary graphics, thereby significantly reducing communication overhead, improving the actual data processing throughput of the GPU computing core, and reducing cross-block data interaction.

[0088] In step S3, the load of the GPU computing core is monitored in real time, and the design rule check tasks corresponding to the data blocks are allocated to the GPU computing core according to the priority and complexity level of the design rule check tasks.

[0089] By monitoring the load of the GPU computing core in real time, the load information of the GPU computing core is obtained, including but not limited to: the number of completed tasks, the estimated remaining time of the current task, the utilization rate of the video memory, the utilization rate of the computing core, the length of the task execution queue, the memory access frequency, and other key indicators. The overall load of the GPU computing core is determined from multiple aspects to achieve more accurate task allocation and data processing.

[0090] At the beginning of the design rule checking task execution, based on the task priority list, task complexity level label and task dependency graph generated in step S1, the data blocks corresponding to the tasks of high priority and medium complexity level are preferentially allocated to the low-load GPU computing cores. According to the real-time feedback of the load of the GPU computing core, the data blocks corresponding to the tasks allocated to the high-load GPU computing core and the data blocks of the tasks not bound to the GPU computing core are allocated to the low-load GPU computing core.

[0091] It can be understood that the initial state of the low-load GPU computing core is "idle and light load", and the utilization rate of the computing unit, the memory surplus, the cache occupation and other computing resources are in a relatively relaxed state. If the data blocks corresponding to the tasks of high priority and high complexity are directly allocated, the following two problems may occur.

[0092] First, the computing resources are saturated at a moment; high complexity level tasks usually involve a large number of set operations, Boolean operations or high-precision checks, which require continuous occupation of a large number of computing cores and memory resources. The low-load GPU computing core may suddenly undertake the processing of such task data blocks, and directly jump from the "low-load" state to the "high-load" state, and even run out of resources, which may become a new load bottleneck.

[0093] Second, the task execution period is prolonged; the high complexity level task has a long predicted execution time, and additional overhead may be generated during the process due to data dependency or intermediate result interaction. If the low-load GPU computing core is occupied by the high complexity level task for a long time, it will not be able to quickly respond to new task allocation, reducing the flexibility of the overall task scheduling.

[0094] And allocating the data blocks corresponding to the tasks of high priority and medium complexity level to the low-load GPU computing core can control the demand for resources, quickly utilize the idle resources of the low-load GPU computing core, and ensure that the core is in a "high-efficiency and unsaturated" state, maintaining the overall dynamic balance.

[0095] The core of dynamic scheduling is to achieve load balancing by frequently adjusting light tasks. If high complexity level tasks are introduced, it will be difficult to quickly correct the load deviation during task allocation and scheduling, and even cause global load shock.

[0096] In step S4, if the GPU computing core completes the processing of the data block, the data block corresponding to the new design rule checking task is allocated according to the overall load of the GPU computing core.

[0097] When a GPU computing core finishes processing a data block, the data block involved in the task of the high-load core or the data block of the task not yet bound to the core will be allocated to an existing idle low-load GPU computing core in combination with the real-time load of each GPU computing core. The data block involved in the task is allocated to the GPU computing core with efficient data transmission to ensure load balancing of each core.

[0098] In step S5, the above steps S3-S4 are repeated until all design rule checking tasks are executed and the layout design rule checking result is output.

[0099] Referring to Figure 3 In some embodiments, when the above steps S3 and S4 are executed, the following step is also executed synchronously: real-time monitoring of the GPU computing core, and when the load of the GPU computing core exceeds the preset threshold, the data block involved in the task of the high-load GPU computing core is migrated to the low-load GPU computing core.

[0100] The preset threshold can be defined as a multi-dimensional dynamic trigger condition, and the judgment basis includes but is not limited to: a preset upper limit of the utilization rate of the GPU computing core, and / or the number of data blocks to be processed in the task queue of the GPU computing core exceeds the processing capacity of the core, and / or the preset upper limit of the saturation state of the memory bandwidth usage, and can be further combined with the duration of the above load state to make a judgment.

[0101] For example, the preset threshold can be defined as: when the GPU computing core utilization rate is higher than 90% and the duration is more than 5 minutes.

[0102] By setting the preset threshold, an explicit and quantifiable load balancing trigger benchmark is provided for the system, ensuring that the system can timely and accurately identify the core with abnormal load, thereby maintaining the efficient and stable operation of the entire design rule checking process.

[0103] In some embodiments, when the load of the GPU computing core exceeds the preset threshold, the priority and / or complexity level of the design rule checking task are adjusted, and / or the block size of the layout data region data block is adjusted.

[0104] Specifically, when it is detected that the GPU computing core exceeds the preset threshold, the priority weight of some key region checking tasks can be automatically increased to speed up the completion of the task, or the segmentation granularity of the data block in the high-load GPU computing core is temporarily refined to achieve more fine-grained load dispersion.

[0105] Through the dynamic adjustment and adaptive capability, the task scheduling strategy and data distribution can be continuously optimized when the design rule checking task is assigned, and the adaptability to the complex layout data checking scene is significantly improved. Through real-time feedback and detection, the task assignment, data block division and related parameters are dynamically adjusted to adapt to the change of the design rule checking task and data, so that the efficient and stable load balancing level is still maintained under the condition of limited hardware resources.

[0106] The steps of the layout design rule checking method provided by the embodiment of the application solve the technical problem that, in the prior art, the GPU is applied to the design rule checking process, the load of the GPU computing core is unbalanced due to the difference in task complexity, the imbalance in data scale and the limitation of the traditional static allocation strategy.

[0107] Through the above layout design rule checking method, the initial layout data is input, the design rule checking task to be executed is parsed, and the priority and complexity level of the task are marked. Based on the features of the layout data region, the layout data is divided into multiple data blocks according to the region, and the task and the corresponding data block are allocated to the GPU computing core according to the priority and complexity level of the task. After the GPU computing core completes the data block processing, new data blocks are allocated according to the overall load of the GPU computing core, and the above steps are repeated until all the tasks are checked, and the layout design rule checking result is output.

[0108] The layout design rule checking method classifies the design rule checking task according to the priority and complexity level, lays a foundation for the load balancing task allocation of the GPU computing core, avoids wasting GPU computing resources caused by only fixedly dividing the computing task according to the task type or data region, and ignores the priority and complexity difference of the task. Further, the layout region is divided into data blocks, so that the GPU computing core processes each data block, and flexible scheduling of the task is realized. Finally, the subsequent task allocation and scheduling are performed based on the real-time monitored load of the GPU computing core, the utilization rate of the GPU computing resource and the processing efficiency of the design rule checking task are improved, and the load balancing layout design rule checking method is realized.

[0109] Referring to Figure 4 The embodiment of the application also provides a layout design rule checking system, which comprises a user terminal 11 and a micro-service terminal 12 in communication connection; the micro-service terminal 12 receives a to-be-processed command input by the user terminal 11, and executes the steps of the above layout design rule checking method according to the to-be-processed command.

[0110] It can be understood that the micro-service end 12 is responsible for executing the steps of the above-mentioned layout design rule checking method, and outputs a preset command uniquely matched with the to-be-processed command to the user end 11 after executing the related steps, and the user end 11 submits the preset command to the interpreter for checking and parsing after receiving the preset command, and finally executes by the EDA software.

[0111] It should be noted that the layout design rule checking method provided in the foregoing embodiments is implemented by using the micro-service-based layout design rule checking system 1, and the micro-service is specifically to separate the single-function module unit from the original, comprehensive single-body application, so that the original software architecture is more clear and simple, so as to update, maintain and further iterate and improve the function that can be implemented by the single module unit.

[0112] Specifically, the layout design rule checking system 1 of the embodiment of the application separates the layout design rule checking function in the integrated circuit design software to form the micro-service end 12, through this design, the person skilled in the art or the user skilled in the integrated circuit design software only needs to deploy a set of micro-service of the layout design rule checking in advance, and then can request the micro-service on the integrated circuit design software of different versions in the local area network, and then realizes the layout design rule checking through the micro-service end 12, and reduces the occupation of the memory resource.

[0113] In some embodiments, the to-be-processed command is stored in a script file, and when the preset command is not uniquely matched with the to-be-processed command, and / or there is no preset command matched with the to-be-processed command, the execution of the script file is interrupted.

[0114] Please refer to Figure 5 The embodiment of the application also provides a computer device 2, which comprises a storage 21, a processor 22 and a computer program 100 stored in the storage 21, and the processor 22 executes the computer program 100 to realize the steps of the above-mentioned layout design rule checking method.

[0115] It can be understood that the computer device 2 provided in the embodiment of the application has the same beneficial effects as the layout design rule checking method provided in the above-mentioned embodiment when the computer device 2 is running and the processor 22 executes the computer program 100.

[0116] In some embodiments, the computer device 2 is a computer device applied to the field of integrated circuit design technology, including but not limited to obtaining initial layout data, analyzing design rule checking tasks, dividing layout data into multiple data blocks, assigning data blocks to GPU computing cores, obtaining the load conditions of the GPU computing cores, etc., which will not be described here. In theory, the method steps involved in the technical solutions of the present application can be realized by participating in the control of the computer device 2, and the related parameters involved can also be adjusted by the computer device 2. The related parameters include but are not limited to the preset command set and the preset option set.

[0117] In some embodiments, the processor 22 provided by the embodiments of the present application is a general-purpose processor, which is a microprocessor or any conventional processor, such as a central processing unit (CPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, which can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application.

[0118] In some embodiments, the method steps disclosed in the embodiments of the present application can be embodied by a hardware processor for execution or by a combination of hardware and software modules in the processor 22 for execution.

[0119] Please refer to Figure 6 The embodiments of the present application also provide a computer readable storage medium 3 having a computer program 100 stored thereon, which implements the steps of the layout design rule checking method when executed by a processor.

[0120] It can be understood that the computer readable storage medium 3 provided by the embodiments of the present application stores the computer program 100, and the computer program 100 can be called by the processor to execute the layout design rule checking method described in the above embodiments.

[0121] It should be noted that the computer readable storage medium 3 provided by the embodiments of the present application has the same beneficial effects as the layout design rule checking method provided by the above embodiments, which will not be described here.

[0122] Specifically, the computer readable storage medium 3 can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc.

[0123] In some embodiments, the computer readable storage medium 3 comprises a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules.

[0124] In particular, the computer readable storage medium 3 has storage space for computer programs 100 that perform any of the method steps of the above layout design rule checking method, which can be read from or written into one or more computer program products.

[0125] In some embodiments, the computer programs 100 can be compressed in an appropriate form.

[0126] Referring to Figure 7 The embodiments of the present application also provide a computer program product 4 comprising the computer programs 100, which, when executed by a processor, implement the steps of the above layout design rule checking.

[0127] It can be understood that the computer program product 4 provided by the embodiments of the present application comprises the computer programs 100, and the computer programs 100 can be called by a processor to execute the layout design rule checking method described in the above embodiments, which will not be described here.

[0128] The layout design rule checking method, layout design rule checking system, device, medium and product disclosed by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment descriptions are only used to help understand the method of the present application and its core idea.

[0129] At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in specific implementation manners and application ranges, and the above description should not be understood as a limitation of the present application. Any modification, equivalent replacement and improvement within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of layout design rule checking, the method comprising: The method comprises the following steps: inputting initial layout data and a design rule file, parsing the design rule file to obtain all design rule checking tasks to be executed, marking the priority and complexity level of each design rule checking task according to the task type and the features of the layout area involved; dividing the layout data into multiple data blocks according to the features of the area based on the initial layout data; monitoring the load of the GPU computing core in real time, assigning the design rule checking tasks and their corresponding data blocks to the GPU computing core according to the priority and complexity level of the design rule checking tasks; after the GPU computing core completes the data block processing, assigning new design rule checking tasks and their corresponding data blocks according to the overall load of the GPU computing core; repeating the above task assignment steps until all design rule checking tasks are executed, and outputting the layout design rule checking result; wherein the priority of the design rule checking task is marked according to at least one of the following information: the dependency relationship between tasks, whether the layout data area involved in the task belongs to the wiring part or the fixed cell layout part, whether the task belongs to the checking of basic rules or the checking of complex rules; and / or, the complexity level of the design rule checking task is marked according to at least one of the following information: the size of the layout data area involved in the task, the wiring density of the layout data area involved in the task, and the complexity of the rule checked by the task.

2. The layout design rule checking method of claim 1, wherein: the features of the layout data area include the computational complexity of the layout data, and the data block size divided for the layout data area with high computational complexity is smaller than the data block size divided for the layout data area with low computational complexity.

3. The layout design rule checking method of claim 1, wherein: when the GPU computing core performs the design rule checking task processing, the method further comprises the following steps: monitoring the GPU computing core in real time, and when the load of the GPU computing core exceeds a preset threshold, migrating the data blocks involved in the tasks of the GPU computing core with high load to the GPU computing core with low load.

4. The layout design rule checking method of claim 3, wherein: when the load of the GPU computing core exceeds the preset threshold, adjusting the priority and / or complexity level of the design rule checking task, and / or adjusting the data block size of the layout data area.

5. The layout design rule checking method of claim 3, wherein: the load state of the GPU computing core comprises at least one of the following load information: the number of completed tasks, the estimated remaining time of the current task, the utilization rate of the video memory, the utilization rate of the computing core, the length of the task execution queue, and the memory access frequency.

6. A layout design rule checking system, comprising: a user terminal and a micro-service terminal connected in communication; the micro-service terminal receives the processing command input by the user terminal, and executes the steps of the layout design rule checking method of any one of claims 1-5 according to the processing command.

7. A computer device comprising a storage, a processor and a computer program stored on the storage, characterized in that, The processor executes the computer program to implement the steps of the layout design rule checking method of any one of claims 1-5.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the layout design rule checking method of any one of claims 1-5.

9. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the layout design rule checking method of any one of claims 1-5.

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