Satellite task planning computing power dynamic distribution system based on heterogeneous multi-core processor

Abstract

The invention belongs to the technical field of data processing, and provides a satellite task planning calculation power dynamic distribution system based on a heterogeneous multi-core processor, which comprises a plurality of DSPs (Digital Signal Processor) for cooperative work, decomposing and planning a calculation task according to original task planning data, and performing parallel processing to generate a rough planning result; the CPU extracts real-time task planning characteristics of the rough planning result, carries out fine planning, generates a satellite task planning result and outputs the satellite task planning result; the shared memory is connected with the CPU and the DSP through a high-speed bus, and stores original task planning data and a rough planning result; and the heterogeneous task division module dynamically adjusts the calculation load ratio of the DSP and the CPU according to the original task planning data. The working reliability and stability of the satellite computing platform in a complex space environment are enhanced, and the data processing failure risk caused by hardware faults is reduced; the processing efficiency of satellite task planning is greatly improved, meanwhile, the calculation precision is guaranteed, and accurate and reliable task planning data can be provided for all application fields.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of data processing, and specifically relates to a satellite task planning computing power dynamic allocation system based on a heterogeneous multi-core processor. BACKGROUND

[0002] With the continuous development of satellite technology, satellite task planning has been widely used in many fields such as geographic information monitoring, environmental research, and urban planning. Satellite task planning requires processing massive amounts of data, and the performance requirements for the computing platform are extremely high.

[0003] Currently, traditional satellite task planning computing mostly adopts a single-core serial processing mode. This mode has extremely low processing efficiency when dealing with large-scale data due to the limitations of single-core computing power, making it difficult to meet real-time requirements. At the same time, a single computing core cannot fully utilize the advantages of different computing resources when facing complex task planning computing tasks, resulting in difficulties in simultaneously improving computing accuracy and efficiency. In addition, traditional computing platforms lack effective fault tolerance mechanisms, and once a computing core fails, the entire task planning computing process will be forced to interrupt, seriously affecting the reliability and continuity of satellite data processing.

[0004] For example, patent document "Heterogeneous multi-core processor task allocation and scheduling strategy based on genetic algorithm" (CN111061569A) discloses a CPU-GPU heterogeneous multi-core processor task allocation and scheduling strategy based on genetic algorithm. By converting tasks into a directed acyclic graph, using an improved genetic algorithm to optimize task allocation schemes, considering the dependency relationship and communication cost between tasks, and finding a near-optimal task allocation and scheduling scheme, it still uses a linear task allocation logic and mainly solves the problem of energy consumption.

[0005] Patent document "Task scheduling method for cooperative management of heterogeneous multi-core processor computing resources" (CN118916148A) discloses a master core component, a computing core component, and a multi-core communication component. The ARM core deploys a real-time operating system, and through the multi-core communication component, seamless communication and resource management between the ARM core and the DSP core are realized. Tasks are intelligently allocated to the most suitable DSP core, and shared memory and inter-core interrupt mechanisms are used to optimize task execution and resource utilization. However, it is not designed for satellite task planning, and therefore lacks consideration of data processing security and reliability, and there is a risk of data processing failure due to hardware failure.

[0006] In summary, there is a need for a new satellite task planning computing platform system to overcome the shortcomings of existing technology. SUMMARY

[0007] Aiming at the defects in the prior art, the present application aims to provide a satellite task planning computing power dynamic allocation system based on a heterogeneous multi-core processor.

[0008] The satellite task planning computing power dynamic allocation system based on a heterogeneous multi-core processor provided by the present application comprises a planning computing power dynamic allocation module and a heterogeneous task division module. The planning computing power dynamic allocation module comprises a CPU, a DSP and a shared memory. The multiple DSPs work cooperatively, decompose planning computing tasks according to original task planning data and execute in parallel to generate a rough planning result. The CPU extracts real-time task planning features of the rough planning result, performs fine planning processing to generate a satellite task planning result and outputs the satellite task planning result. The shared memory is connected with the CPU and the DSP through a high-speed bus and stores original task planning data and a rough planning result. The heterogeneous task division module dynamically adjusts the computing load ratio of the DSP and the CPU according to original task planning data.

[0009] Preferably, the DSP is 2 to 4 pieces, and the multiple DSPs work simultaneously, back up each other and monitor working states in real time.

[0010] The CPU adopts a model with logical control and task scheduling capability, and the DSP adopts a model with high-speed parallel data processing capability.

[0011] The shared memory is constructed by using a high-speed and large-capacity storage chip.

[0012] The CPU, the multiple DSPs and the shared memory are integrated on the same circuit board, and the interconnection lines between the multiple DSPs are symmetrically arranged.

[0013] Preferably, the DSP adopts a multi-DSP redundant architecture, comprising: The multiple DSPs are configured with the same type and parameters of planning computing tasks and start working simultaneously. The multiple DSPs regularly send heartbeat signals and state information to each other, back up each other and monitor state information.

[0014] When any one of the DSPs fails, the remaining DSPs immediately take over the task of the failed DSP and continue to complete the task planning computing work, while recording fault information.

[0015] Preferably, when any one of the DSPs does not receive heartbeat signals from the remaining DSPs for multiple times continuously or determines that the planning computing result is abnormal, the DSP is marked as a failed DSP and a redundant switching mechanism is triggered immediately. The remaining DSPs immediately take over the task queue of the failed DSP and continue to complete the remaining planning computing tasks.

[0016] Preferably, the heterogeneous task division module allocates more than 50% of the computing load to the DSP and the rest to the CPU when the type of the computing task is a data-intensive task. When the type of the computing task is a logic processing task, the computing load of the CPU is increased.

[0017] Preferably, the heterogeneous task division module comprises: Module MA.1, analyzing and decomposing the computing task to obtain subtasks.

[0018] Module MA.2, monitoring the load of the CPU and the DSP in real time when the subtasks are executed.

[0019] Module MA.3, dynamically adjusting the computing load ratio according to the type of the subtasks and the load of the CPU and the DSP.

[0020] Module MA.4, the scheduler allocating the CPU and the DSP to execute the subtasks according to the set task queue and priority scheduling mechanism.

[0021] Preferably, the type of the subtasks comprises a data-intensive task and a logic processing task.

[0022] The load comprises the computing resource utilization and the task queue length.

[0023] In the module MA.3, for the data-intensive task, 80% of the computing load is allocated to the DSP and 20% to the CPU, and for the logic processing task, 30% of the computing load is allocated to the DSP and 70% to the CPU.

[0024] Preferably, the scheduler comprises: A heterogeneous task identification and dispatching module, distinguishing the type of the subtasks and allocating the subtasks to the corresponding CPU or DSP according to the type.

[0025] A dynamic load balancing module, detecting the real-time load of the DSP and allocating the subtasks to the DSP with the lowest resource utilization or the shortest task queue length.

[0026] A fault-tolerant scheduling integration module, detecting the state information of the DSP, isolating the faulty DSP and allocating the subtasks in the task queue of the faulty DSP to the remaining DSPs.

[0027] A task dependency management module, managing the data dependency relationship between the subtasks executed by the CPU and the DSP.

[0028] According to the satellite task planning computing power dynamic allocation method based on the heterogeneous multi-core processor provided by the application, the following steps are included: Step S1, the satellite receives the task planning requirement, and parses into original task planning data and transmits to the shared memory; Step S2, the DSP accesses the shared memory to read the original task planning data and decomposes into planning calculation tasks, and parallel execution generates a rough planning result and stores in the shared memory; Step S3, the CPU accesses the shared memory to read the rough planning result, extracts real-time task planning features, and generates a satellite task planning result through fine planning processing and outputs.

[0029] Preferably, the CPU adopts a model with logical control and task scheduling capability, and the DSP adopts a model with high-speed parallel data processing capability.

[0030] The shared memory is constructed by using a high-speed and large-capacity storage chip.

[0031] The CPU, multiple DSPs and the shared memory are integrated on the same circuit board, and the interconnection lines between the multiple DSPs are symmetrically arranged.

[0032] The DSP is 2 to 4 pieces, and the multiple DSPs work simultaneously, back up each other, and monitor the working state in real time, and adopt a multi-DSP redundant architecture, which comprises: The multiple DSPs are configured with the same type and parameters of planning calculation tasks, and start working simultaneously; The multiple DSPs periodically send heartbeat signals and state information to each other, back up each other, and monitor the state information; When any one of the DSPs fails, the remaining DSPs immediately take over the task of the failed DSP and continue to complete the task planning calculation work, while recording the fault information.

[0033] Compared with the prior art, the present application has the following beneficial effects: 1. The dual-DSP redundant architecture design adopted by the present application enables the satellite computing platform to have strong fault tolerance capability, ensures uninterrupted task planning calculation process, enhances the reliability and stability of the satellite computing platform in complex space environment, and reduces the risk of data processing failure caused by hardware failure.

[0034] 2. The present application adopts the DSP and CPU to cooperate for task planning calculation, fully utilizes the advantages of both, improves the processing efficiency while ensuring the calculation accuracy, and can provide accurate and reliable task planning data for various application fields.

[0035] 3. The present application dynamically adjusts the calculation load by combining the heterogeneous multi-core processor and algorithm design, which greatly improves the processing efficiency of satellite task planning compared with the traditional single-core serial processing mode, can quickly process massive data, and meets the real-time requirement. BRIEF DESCRIPTION OF DRAWINGS

[0036] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings: Figure 1 A flowchart of a satellite task planning computing power dynamic allocation method based on a heterogeneous multi-core processor. DETAILED DESCRIPTION

[0037] The application will be described in detail below with specific embodiments. The following examples will help those skilled in the art to further understand the application, but do not limit the application in any form. It should be noted that for those skilled in the art, without departing from the concept of the application, a number of changes and improvements can be made. These are within the scope of the present application.

[0038] The satellite task planning computing power dynamic allocation system based on a heterogeneous multi-core processor provided by the application can efficiently and accurately complete satellite task planning computing tasks and has high reliability, meeting the needs of different fields for satellite task planning data processing. Specifically, it includes a planning computing power dynamic allocation module and a heterogeneous task division algorithm. The planning computing power dynamic allocation module includes a CPU (central processing unit), multiple DSPs (digital signal processors), and a shared memory.

[0039] The DSP has strong parallel data processing capability and is particularly suitable for processing intensive tasks in task planning computing. The DSP is used to parallelize processing of intensive tasks in task planning computing to generate a rough planning result.

[0040] Specifically, the multiple DSPs work cooperatively to parallelize processing of intensive tasks in task planning computing, generate a rough planning result through fast data processing and operation.

[0041] The intensive tasks in task planning computing include orbit dynamics simulation, sensor coverage analysis, visible time window calculation, and other tasks.

[0042] The multiple DSPs are in a redundant architecture, which enables the satellite computing platform to have strong fault tolerance and enhances the reliability of the satellite computing platform. In a normal working state, the multiple DSPs work simultaneously, back up each other, and monitor each other's working state in real time.

[0043] The CPU has good logic control and complex task scheduling capability and is used to perform fine planning processing on the rough planning result output by the DSP.

[0044] The DSP is responsible for fast preliminary processing of data to generate a rough planning result, and the CPU performs fine planning on the rough planning result based on real-time task planning features, thereby giving full play to the advantages of both, improving processing efficiency while ensuring calculation accuracy, and providing accurate and reliable task planning data for various application fields.

[0045] In more preferred examples, a CPU and a DSP chip with matched performance are selected.

[0046] The CPU is selected from models with strong logical control and task scheduling capabilities, such as Power PC 460 GTx, Power PC 460SX, PowerPC 405EX, PowerPC 750CL, PowerPC 970GX, etc. The DSP chip is selected from products with high-speed parallel data processing capabilities, such as FT6672, FT6678, TMS320C6678, etc. The number of DSPs is determined according to the calculation requirements, and preferably 2-4 pieces.

[0047] The shared memory serves as a bridge for communication between heterogeneous cores, is used to realize low-latency communication between the CPU and the DSP, ensures fast and accurate transmission and sharing of data, and enables the CPU to process the rough planning result in a timely manner based on real-time task planning features.

[0048] In more preferred examples, a high-speed and high-capacity storage chip is used to construct a shared memory module, ensuring low-latency data communication between the CPU and the DSP. The shared memory is connected to the CPU and the DSP through a high-speed bus, ensuring the stability and efficiency of data transmission.

[0049] The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, the components are reasonably arranged, the circuit design is optimized, signal interference is reduced, and the overall performance and stability of the hardware system are improved.

[0050] Specifically, the following requirements need to be met: high-speed signal integrity layout requirements, heat dissipation design requirements, electromagnetic compatibility and crosstalk control, and synchronization and communication layout requirements between redundant DSPs.

[0051] High-speed signal integrity layout requirements: the high-speed bus (such as DDrx interface) between the CPU, DSP, and shared memory must strictly follow the equal-length wiring and impedance control.

[0052] Heat dissipation design requirements: heat sinks or heat plates should be covered on the CPU and multiple DSP chips; when laying out the PCB, sufficient consideration should be given to the heat dissipation channels to avoid heat accumulation; for high-power chips, sensitive devices (such as crystal oscillators) should be avoided during layout.

[0053] EMC and crosstalk control: sensitive high-speed signal lines (such as memory bus, differential clock line) should be far away from noise sources (such as switching power supply circuit); a spacing of 3W (3 times the line width) should be maintained between different groups of high-speed signal lines; and if necessary, a package ground treatment is performed.

[0054] Synchronization and communication layout requirements between redundant DSPs: interconnection lines (such as SPI, I2C, GPIO) for implementing real-time communication mechanism and heartbeat signal between DSPs, whose wiring delay should be as short as possible and symmetrical.

[0055] The heterogeneous task partitioning algorithm can dynamically adjust the computing load ratio of the DSP and the CPU according to the task planning calculation requirements.

[0056] At the initial stage of task planning calculation, the data volume is large and the calculation tasks are mostly data-intensive tasks, so more computing load is allocated to the DSP to fully exert its parallel processing advantage, quickly complete the preliminary processing of data and the generation of rough planning results. As the calculation progresses, when the results need to be logically analyzed, optimized and finely planned, the computing load of the CPU is correspondingly increased to utilize the logical processing capability of the CPU to perform fine planning on the rough planning results.

[0057] Through this dynamic load adjustment, compared with the traditional single-core serial processing mode, the processing efficiency is greatly improved while ensuring the calculation accuracy.

[0058] Specifically, it includes: Module MA.1, analyzes the planning calculation tasks and decomposes them into a series of more fine-grained subtasks.

[0059] The subtasks are classified as data-intensive tasks or logical processing tasks according to their computing characteristics. The rough planning calculation tasks are mainly composed of data-intensive subtasks, involving a large number of parallel and rule-based calculations. The fine planning calculation tasks are mainly composed of logical processing subtasks.

[0060] In more preferred examples, the fine planning stage also calls some data calculations (but with low complexity), and the rough planning stage also includes simple logical judgments.

[0061] In typical cases, the tasks allocated to the DSP are mainly data-intensive tasks, and its output is the rough planning result; while the tasks allocated to the CPU for processing are mainly logical processing tasks, which are based on the rough planning result for fine planning.

[0062] Module MA.2, real-time monitoring of the load conditions of the CPU and the DSP during the calculation process, including parameters such as computing resource utilization rate and task queue length.

[0063] Running a multi-DSP redundant architecture, specifically including: Module MB.1, multiple DSPs are configured with the same calculation tasks and parameters at initialization and start working at the same time.

[0064] Module MB.2, a real-time communication mechanism is established between DSPs to monitor the working status of each other by sending heartbeat signals and task status information periodically.

[0065] Module MB.3, in normal working state, two DSPs work simultaneously and back up each other, and real-time monitor the working status of each other; when one of the DSPs fails, the other DSP can immediately take over the task of the failed DSP and continue to complete the task planning and calculation.

[0066] Specifically, when any DSP detects that one of the DSPs has failed (such as not receiving a heartbeat signal for a plurality of times, abnormal calculation results, etc.), a redundancy switching mechanism is triggered immediately, and the remaining DSPs can immediately take over the task queue of the failed DSP and continue to complete the remaining task planning and calculation, ensuring that the entire task planning and calculation process is not interrupted, and effectively avoiding the failure of calculation caused by the failure of a single computing unit.

[0067] At the same time, the system records fault information for subsequent fault diagnosis and repair, greatly enhancing the reliability and stability of the satellite computing platform in complex space environment, and reducing the risk of data processing failure caused by hardware failure.

[0068] Module MA.3, according to different stages of task planning and calculation and task requirements, and combining the load conditions of CPU and DSP, the calculation load ratio is dynamically adjusted.

[0069] In more preferred examples, in the data acquisition and preliminary processing stage, 80% of the calculation load is allocated to DSP, and 20% is allocated to CPU; in the result optimization and fine planning stage, the adjustment is that 30% of the load is given to DSP, and 70% is given to CPU.

[0070] Module MA.4, the scheduler uses task queue and priority scheduling mechanism to ensure that tasks can be reasonably allocated and executed between CPU and DSP according to priority order, avoiding task congestion and resource waste.

[0071] Specifically, for the specific hardware environment of CPU and multi-DSP redundant architecture, the conventional scheduling mechanism is deeply adjusted and customized to achieve the core goal of heterogeneous collaboration and fault tolerance, including: Heterogeneous task identification and dispatching: the task type needs to be distinguished, and it is dynamically allocated to the most suitable processing unit (CPU or DSP).

[0072] Multi-DSP dynamic load balancing: real-time monitoring of the load of each DSP is required, and tasks are intelligently allocated to the most idle DSP to achieve efficient parallelism.

[0073] Fault-tolerant scheduling integration: the scheduler is linked with the heartbeat monitoring mechanism, which can isolate the DSP in case of failure and automatically redistribute its tasks to healthy DSPs, which is the core of realizing high reliability of the system.

[0074] Task dependency management: the scheduler needs to manage the data dependency relationship between CPU tasks and DSP tasks to ensure the correctness of the data processing flow.

[0075] Through parallel processing of multiple DSPs to handle task planning computation-intensive tasks, and CPU fine planning processing of coarse planning results, combined with algorithm optimization to dynamically adjust the computing load, compared with the traditional single-core serial processing mode, the processing efficiency is significantly improved while ensuring the calculation accuracy, which can quickly process massive data and meet the real-time requirements. At the same time, the reliability of the satellite computing platform is enhanced to meet the efficient and stable requirements of satellite task planning computation in multiple fields.

[0076] According to the satellite task planning computing power dynamic allocation method based on a heterogeneous multi-core processor provided by the application, Figure 1 For example, it includes: Step S1, the satellite receives the task planning requirement.

[0077] Step S2, data transmission to shared memory; Specifically, the original task planning data collected by the satellite is transmitted to the shared memory.

[0078] The task planning requirement is the user's instruction at the top level, which is the starting point and target of task planning. It is usually a natural language or a high-level descriptive file, for example: "realize a full coverage observation in a certain area within the next 24 hours" or "preferentially process the disaster monitoring request of a certain area".

[0079] The original task planning data is structured input data generated by the satellite system after analyzing and parameterizing the task planning requirement, which can be directly used by the processor, and is transmitted to the shared memory. For example: the latitude and longitude coordinate boundary of the target area, the priority weight of the task, the energy constraint of the satellite platform, the storage constraint; the performance parameters (side swing angle range, resolution) of the load (camera, radar); satellite orbit ephemeris data.

[0080] Step S3, the CPU and DSP access the shared memory to obtain data.

[0081] Step S4, multiple DSPs are used to generate coarse planning results and store them in the shared memory; Specifically, the multi-block DSP reads the original mission planning data from the shared memory, performs the mission planning computationally intensive tasks in parallel, such as data filtering, feature extraction, preliminary modeling, etc., generates a rough planning result, and stores the result back to the shared memory.

[0082] The mission planning computing task refers to a specific data processing process within the system. The heterogeneous task division module decomposes the original mission planning data into a series of specific computing tasks (data-intensive tasks, logical processing tasks, etc.), and dynamically allocates them to DSP or CPU for execution. For example: "Calculate the visible time window of grid A1".

[0083] Step S5, the CPU reads the rough planning result in the shared memory, processes to generate the fine planning result and outputs.

[0084] Specifically, the CPU reads the rough planning result generated by the DSP from the shared memory, based on real-time mission planning features, uses complex logical algorithms and optimization strategies to perform fine planning processing on the rough planning result, including mission planning smoothing, boundary optimization, outlier correction, etc., and finally generates an accurate satellite mission planning.

[0085] The real-time mission planning feature is the key information and decision basis extracted from the rough planning result generated by the DSP by the CPU during the execution of the fine planning process. It is a derivative feature generated after the original mission planning data is preliminarily processed and analyzed. For example: Conflict feature: multiple tasks identified in the rough planning result have conflict points in time or resources.

[0086] Efficiency feature: overall efficiency (such as energy utilization rate, total time consumption) evaluation of different task execution sequences.

[0087] Opportunity feature: discovered unplanned observation opportunities.

[0088] Quality feature: indicators that affect the quality of the final planning, such as the confidence of some data in the rough planning result, cloud coverage ratio, etc.

[0089] In more preferred examples, the CPU uses a model with logical control and task scheduling capabilities, and the DSP uses a model with high-speed parallel data processing capabilities.

[0090] The shared memory is built with high-speed and large-capacity storage chips.

[0091] The CPU, multi-block DSP, and shared memory are integrated on the same circuit board, and the interconnection lines between the multi-block DSPs are symmetrically arranged.

[0092] The DSP is 2 to 4 blocks, and the multi-block DSPs work simultaneously, back up each other, and monitor the working state in real time, adopting a multi-DSP redundant architecture, including: The multi-block DSPs are configured with the same type and parameters of the planning calculation task, and start working at the same time; The multi-block DSPs periodically send heartbeat signals and state information to each other, back up each other, and monitor state information of each other; When any one of the DSPs fails, the remaining DSPs immediately take over the task of the failed DSP, continue to complete the task planning calculation work, and record the failure information.

[0093] The specific embodiments of the application are described above. It should be understood that the application is not limited to the specific implementation described above, and various changes or modifications can be made by those skilled in the art within the scope of the claims, which does not affect the essential content of the application. In the case of no conflict, the embodiments of the application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors, characterized by: include: Planning computing power dynamic allocation module and heterogeneous task partitioning module; The planned computing power dynamic allocation module includes CPU, DSP and shared memory; Multiple DSPs work together to decompose the planning calculation tasks according to the original task planning data, and execute them in parallel to generate rough planning results; The CPU extracts the real-time mission planning features of the rough planning results, and generates and outputs the satellite mission planning results through fine planning processing; The shared memory is connected to the CPU and DSP via a high-speed bus to store original mission planning data and rough planning results; The heterogeneous task partitioning module dynamically adjusts the computing load ratio between DSP and CPU according to the original task planning data.

2. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1 is characterized in that: There are 2 to 4 DSPs, and multiple DSPs work simultaneously, back up each other, and monitor the working status in real time; The CPU adopts a model with logic control and task scheduling capabilities, and the DSP adopts a model with high-speed parallel data processing capabilities; The shared memory is constructed using a high-speed and large-capacity memory chip; The CPU, multiple DSPs and shared memory are integrated on the same circuit board, and the interconnection lines between the multiple DSPs are arranged symmetrically.

3. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1 is characterized in that: The DSP adopts a multi-DSP redundant architecture, including: Multiple DSPs are configured with the same type and parameters of planned computing tasks and start working at the same time; Multiple DSPs regularly send heartbeat signals and status information to each other, back up each other, and monitor each other's status information; When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information at the same time.

4. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 3 is characterized in that: When any of the DSPs fails to receive the heartbeat signal from any other DSP for multiple consecutive times or determines that the planning calculation result is abnormal, it is marked as a faulty DSP and the redundancy switching mechanism is immediately triggered; The remaining DSPs immediately take over the task queue of the failed DSP and continue to complete the remaining planning calculation tasks.

5. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1 is characterized in that: When the type of the planned computing task is a data-intensive task, the heterogeneous task partitioning module allocates more than 50% of the computing load to the DSP and the remaining computing load to the CPU; When the planned computing task type is a logic processing task, the computing load of the CPU is increased.

6. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 5 is characterized in that: The heterogeneous task division module includes: Module MA.1: Analyze and decompose the planning calculation task to obtain subtasks; Module MA.2, real-time monitoring of CPU and DSP loads when executing subtasks; Module MA.3 dynamically adjusts the computing load ratio based on the type of subtask and the CPU and DSP load conditions; Module MA.4, the scheduler assigns the CPU and DSP to execute subtasks according to the set task queue and priority scheduling mechanism.

7. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 6 is characterized in that: The types of subtasks include data-intensive tasks and logic processing tasks; The load condition includes computing resource utilization and task queue length; In the module MA.3, for data-intensive tasks, 80% of the computing load is allocated to the DSP and 20% to the CPU. For logic processing tasks, 30% of the computing load is allocated to the DSP and 70% to the CPU.

8. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 6 is characterized in that: The scheduler includes: Heterogeneous task identification and dispatching module distinguishes the types of subtasks and assigns them to the corresponding CPU or DSP according to the type; Dynamic load balancing module detects the real-time load of DSPs and assigns subtasks to the DSP with the lowest resource utilization or the shortest task queue length; Fault-tolerant scheduling integration module detects DSP status information, isolates the faulty DSP and distributes the subtasks in its task queue to other DSPs; The task dependency management module manages the data dependency between subtasks executed by the CPU and DSP.

9. A method for dynamically allocating computing power for satellite mission planning based on heterogeneous multi-core processors, which uses the system for dynamically allocating computing power for satellite mission planning based on heterogeneous multi-core processors as described in any one of claims 1 to 8 to perform computing power allocation, characterized in that: include: Step S1: The satellite receives the mission planning requirement, parses it into the original mission planning data and transmits it to the shared memory; Step S2: DSP accesses the shared memory to read the original task planning data and decomposes it into planning calculation tasks, executes them in parallel to generate rough planning results and stores them in the shared memory; Step S3: The CPU accesses the shared memory to read the rough planning results, extracts the real-time mission planning features, performs fine planning processing to generate the satellite mission planning results and outputs them.

10. The method for dynamically allocating computing power for satellite mission planning based on heterogeneous multi-core processors according to claim 9, characterized in that: The CPU adopts a model with logic control and task scheduling capabilities, and the DSP adopts a model with high-speed parallel data processing capabilities; The shared memory is constructed using a high-speed and large-capacity memory chip; The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, and the interconnection lines between the multiple DSPs are arranged symmetrically; The number of DSPs is 2 to 4. Multiple DSPs work simultaneously, back up each other, and monitor the working status in real time. A multi-DSP redundant architecture is adopted, including: Multiple DSPs are configured with the same type and parameters of planned computing tasks and start working at the same time; Multiple DSPs regularly send heartbeat signals and status information to each other, back up each other, and monitor each other's status information; When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information at the same time.

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