Satellite task planning computing power dynamic allocation system based on heterogeneous multi-core processor

Abstract

The application belongs to the technical field of data processing, and provides a satellite task planning computing power dynamic allocation system based on a heterogeneous multi-core processor, which comprises: multiple DSPs cooperatively working, decomposing planning calculation tasks according to original task planning data, and generating coarse planning results through parallel processing; a CPU extracting real-time task planning features of the coarse planning results, performing fine planning, generating satellite task planning results and outputting; a shared memory being connected with the CPU and the DSP through a high-speed bus, storing original task planning data and coarse planning results; and a heterogeneous task division module dynamically adjusting the calculation load ratio of the DSP and the CPU according to the original task planning data. The application enhances the reliability and stability of the satellite computing platform working in a complex space environment, reduces the risk of data processing failure caused by hardware failure, greatly improves the processing efficiency of satellite task planning, guarantees the calculation accuracy, and can provide accurate and reliable task planning data for various application fields.

Description

Technical Field

[0001] This invention belongs to the field of data processing technology, specifically, it relates to a dynamic allocation system for satellite mission planning computing power based on heterogeneous multi-core processors. Background Technology

[0002] With the continuous development of satellite technology, satellite mission planning has been widely used in many fields such as geographic information monitoring, environmental research, and urban planning. Satellite mission planning calculations require processing massive amounts of data, placing extremely high demands on the performance of the computing platform.

[0003] Currently, traditional satellite mission planning calculations mostly employ a single-core serial processing approach. This method suffers from extremely low processing efficiency when handling large-scale data due to the limitations of a single core's computing power, making it difficult to meet real-time requirements. Furthermore, a single computing core cannot fully leverage the advantages of different computing resources when facing complex mission planning calculations, resulting in a difficulty in simultaneously improving computational accuracy and efficiency. In addition, traditional computing platforms lack effective fault tolerance mechanisms; if a computing core fails, the entire mission planning calculation process will be forced to stop, severely impacting the reliability and continuity of satellite data processing.

[0004] For example, the patent document "A Task Allocation and Scheduling Strategy for Heterogeneous Multi-core Processors Based on Genetic Algorithm" (CN111061569A) discloses a task allocation and scheduling strategy for CPU-GPU heterogeneous multi-core processors based on genetic algorithm. By converting tasks into directed acyclic graphs, the improved genetic algorithm is used to optimize the task allocation scheme. Considering the dependencies and communication costs between tasks, a near-optimal task allocation and scheduling scheme is found. However, it is still a linear task allocation logic, and its main problem is energy consumption.

[0005] The patent document "Task Scheduling Method for Collaborative Management of Computing Resources in Heterogeneous Multi-core Processors" (CN118916148A) discloses a main control core component, a computing core component, and a multi-core communication component. An ARM core deploys a real-time operating system, and the multi-core communication component enables seamless communication and resource management between the ARM core and the DSP core. It intelligently allocates tasks to the most suitable DSP core and optimizes task execution and resource utilization using shared memory and inter-core interrupt mechanisms. However, it is not designed for satellite missions and therefore lacks consideration for data processing security and reliability, posing a risk of data processing failure due to hardware malfunctions.

[0006] In summary, a new satellite mission planning computing platform system is needed to overcome the shortcomings of existing technologies. Summary of the Invention

[0007] To address the shortcomings of existing technologies, the purpose of this invention is to provide a dynamic computing power allocation system for satellite mission planning based on heterogeneous multi-core processors.

[0008] According to the present invention, a satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors includes: a planning computing power dynamic allocation module and a heterogeneous mission partitioning module;

[0009] The dynamic allocation module for computing power planning includes a CPU, a DSP, and shared memory;

[0010] Multiple DSPs work together to decompose the planning calculation task based on the original task planning data and execute it in parallel to generate coarse planning results.

[0011] The CPU extracts the real-time mission planning features from the coarse planning results, performs fine planning processing to generate satellite mission planning results, and outputs them.

[0012] Shared memory is connected to the CPU and DSP via a high-speed bus to store raw task planning data and coarse planning results.

[0013] The heterogeneous task partitioning module dynamically adjusts the computing load ratio between the DSP and CPU based on the original task planning data.

[0014] Preferably, there are 2 to 4 DSPs, with multiple DSPs working simultaneously, backing up each other, and monitoring their working status in real time.

[0015] The CPU is a model with logic control and task scheduling capabilities, and the DSP is a model with high-speed parallel data processing capabilities.

[0016] The shared memory is constructed using high-speed and high-capacity storage chips.

[0017] The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, with the interconnect lines between the multiple DSPs arranged symmetrically.

[0018] Preferably, the DSP adopts a multi-DSP redundancy architecture, including:

[0019] Multiple DSPs are configured with the same type and parameters for planning calculation tasks and start working simultaneously.

[0020] Multiple DSPs periodically send heartbeat signals and status information to each other, backing up each other and monitoring each other's status information.

[0021] When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information.

[0022] Preferably, if any DSP fails to receive a heartbeat signal from any other DSP for several consecutive times or determines that the planning calculation result is abnormal, it is marked as a faulty DSP, and the redundancy switching mechanism is immediately triggered.

[0023] The remaining DSPs immediately take over the task queue of the faulty DSP and continue to complete the remaining planning calculation tasks.

[0024] Preferably, when the type of the planned computing task is a data-intensive task, the heterogeneous task partitioning module allocates more than 50% of the computing load to the DSP and the remaining computing load to the CPU.

[0025] When the type of computational task planned is a logical processing task, increase the computational load on the CPU.

[0026] Preferably, the heterogeneous task partitioning module includes:

[0027] Module MA.1 analyzes and decomposes the planning calculation task to obtain sub-tasks.

[0028] Module MA.2 monitors the CPU and DSP load in real time when executing subtasks.

[0029] Module MA.3 dynamically adjusts the computational load ratio based on the type of subtask and the load conditions of the CPU and DSP.

[0030] Module MA.4: The scheduler allocates CPU and DSP to execute subtasks according to the set task queue and priority scheduling mechanism.

[0031] Preferably, the types of subtasks include data-intensive tasks and logic processing tasks.

[0032] The load conditions include computing resource utilization and task queue length.

[0033] In module MA.3, for data-intensive tasks, 80% of the computing load is allocated to the DSP and 20% to the CPU; for logic processing tasks, 30% of the computing load is allocated to the DSP and 70% to the CPU.

[0034] Preferably, the scheduler includes:

[0035] The heterogeneous task identification and dispatch module identifies the types of subtasks and assigns them to the corresponding CPUs or DSPs based on their types.

[0036] The dynamic load balancing module detects the real-time load of the DSP and assigns subtasks to the DSP with the lowest resource utilization or the shortest task queue length.

[0037] The fault-tolerant scheduling integration module detects the status information of the DSP, isolates the faulty DSP, and allocates its subtasks in the task queue to the remaining DSPs.

[0038] The task dependency management module manages the data dependencies between subtasks executed by the CPU and DSP.

[0039] A method for dynamic allocation of computing power for satellite mission planning based on heterogeneous multi-core processors, provided by the present invention, includes:

[0040] Step S1: The satellite receives the mission planning requirements, parses them into the original mission planning data, and transmits it to shared memory;

[0041] Step S2: The DSP accesses the shared memory to read the original task planning data and decomposes it into planning calculation tasks. The tasks are executed in parallel to generate coarse planning results and stored in the shared memory.

[0042] Step S3: The CPU accesses shared memory to read the coarse planning results, extracts real-time mission planning features, performs fine planning processing to generate satellite mission planning results, and outputs them.

[0043] Preferably, the CPU is a model with logic control and task scheduling capabilities, and the DSP is a model with high-speed parallel data processing capabilities.

[0044] The shared memory is constructed using high-speed and high-capacity storage chips.

[0045] The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, with the interconnect lines between the multiple DSPs arranged symmetrically.

[0046] The DSP consists of 2 to 4 modules, with multiple DSPs operating simultaneously, providing mutual backup, and monitoring their operational status in real time. A multi-DSP redundancy architecture is employed, including:

[0047] Multiple DSPs are configured with the same type and parameters for planning calculation tasks and start working simultaneously.

[0048] Multiple DSPs periodically send heartbeat signals and status information to each other, backing up each other and monitoring each other's status information;

[0049] When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] 1. This invention adopts a dual-DSP redundant architecture design, which enables the satellite computing platform to have strong fault tolerance, ensures uninterrupted mission planning and calculation, enhances the reliability and stability of the satellite computing platform in complex space environments, and reduces the risk of data processing failure due to hardware failure.

[0052] 2. This invention uses DSP and CPU to perform task planning calculations in collaboration, giving full play to the advantages of both. It improves processing efficiency while ensuring calculation accuracy, and can provide accurate and reliable task planning data for various application fields.

[0053] 3. This invention dynamically adjusts the computing load by combining heterogeneous multi-core processors and algorithm design, which greatly improves the processing efficiency of satellite mission planning compared with the traditional single-core serial processing method. It can quickly process massive amounts of data and meet real-time requirements. Attached Figure Description

[0054] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0055] Figure 1 A schematic diagram illustrating the process of dynamically allocating computing power for satellite mission planning based on heterogeneous multi-core processors. Detailed Implementation

[0056] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0057] The present invention provides a satellite mission planning computing power dynamic allocation system based on a heterogeneous multi-core processor, which can efficiently and accurately complete satellite mission planning calculation tasks and has high reliability, meeting the needs of different fields for satellite mission planning data processing. Specifically, it includes: a planning computing power dynamic allocation module and a heterogeneous task partitioning algorithm;

[0058] The planning computing power dynamic allocation module includes a CPU (Central Processing Unit), multiple DSPs (Digital Signal Processors), and shared memory.

[0059] DSPs possess powerful parallel data processing capabilities, making them particularly suitable for handling computationally intensive tasks in task planning. The DSP is used to parallelize computationally intensive task planning tasks and generate coarse planning results.

[0060] Specifically, multiple DSPs work together to process computationally intensive tasks in parallel, generating coarse planning results through rapid data processing and computation.

[0061] The computationally intensive tasks in the task planning include tasks such as orbital dynamics simulation, sensor coverage analysis, and visible time window calculation.

[0062] The adoption of a multi-DSP redundancy architecture gives the satellite computing platform strong fault tolerance and enhances its reliability. Under normal operating conditions, multiple DSPs work simultaneously, backing up each other and monitoring each other's operating status in real time.

[0063] The CPU has good logic control and complex task scheduling capabilities, which are used to perform fine planning processing on the coarse planning results output by the DSP.

[0064] The DSP is responsible for the rapid initial processing of data and generates coarse planning results, while the CPU performs fine planning on the coarse planning results based on real-time task planning characteristics. This fully leverages the advantages of both, improving processing efficiency while ensuring computational accuracy, and providing accurate and reliable task planning data for various application fields.

[0065] In more preferred examples, CPU and DSP chips with matching performance are selected.

[0066] Choose a CPU model with strong logic control and task scheduling capabilities, such as PowerPC 460 GTx, PowerPC 460SX, PowerPC 405EX, PowerPC 750CL, and PowerPC 970GX. Select a DSP chip with high-speed parallel data processing capabilities, such as FT6672, FT6678, and TMS320C6678. Determine the number of DSPs based on computing requirements, preferably 2 to 4.

[0067] The shared memory serves as a bridge for communication between heterogeneous cores, enabling low-latency communication between the CPU and the DSP. This ensures fast and accurate data transmission and sharing, allowing the CPU to process coarse planning results promptly based on real-time task planning characteristics.

[0068] In more preferred embodiments, high-speed, high-capacity storage chips are used to construct the shared memory module, ensuring low-latency data communication between the CPU and DSP. The shared memory is connected to the CPU and DSP via a high-speed bus, ensuring the stability and efficiency of data transmission.

[0069] By integrating the CPU, multiple DSPs, and shared memory onto the same circuit board, the components are rationally arranged, the circuit design is optimized, signal interference is reduced, and the overall performance and stability of the hardware system are improved.

[0070] Specifically, it is necessary to meet the requirements for high-speed signal integrity layout, heat dissipation design, electromagnetic compatibility and crosstalk control, and synchronization and communication layout between redundant DSPs.

[0071] High-speed signal integrity layout requirements: High-speed buses (such as DDRx interfaces) between the CPU, DSP and shared memory must strictly adhere to equal-length wiring and impedance control.

[0072] Thermal design requirements: CPU and multiple DSP chips should be covered with heat sinks or heat spreaders; the PCB layout should fully consider heat dissipation channels to avoid heat accumulation; for high-power chips, the layout should avoid heat-sensitive devices (such as crystal oscillators).

[0073] Electromagnetic compatibility and crosstalk control: Sensitive high-speed signal lines (such as memory buses and differential clock lines) should be kept away from noise sources (such as switching power supply circuits); a 3W (3 times the line width) spacing should be maintained between different groups of high-speed signal lines; grounding should be performed when necessary.

[0074] Requirements for synchronization and communication layout between redundant DSPs: The interconnection lines (such as SPI, I2C, GPIO) used to implement real-time communication mechanisms and heartbeat signals between DSPs should have the shortest possible routing delay and be symmetrical.

[0075] The heterogeneous task partitioning algorithm can dynamically adjust the computing load ratio between the DSP and the CPU according to the task planning and computing requirements.

[0076] In the initial stages of task planning and computation, the data volume is enormous and the computational tasks are mostly data-intensive. Therefore, more computational load is allocated to the DSP to fully leverage its parallel processing advantages and quickly complete the initial data processing and generate coarse planning results. As the computation progresses, when logical analysis, optimization, and fine planning of the results are required, the CPU's computational load is increased accordingly, utilizing the CPU's logical processing capabilities to refine the coarse planning results.

[0077] This dynamic load adjustment significantly improves processing efficiency while maintaining computational accuracy, compared to the traditional single-core serial processing method.

[0078] Specifically, including:

[0079] Module MA.1 analyzes the planning calculation task and decomposes it into a series of more granular subtasks.

[0080] Subtasks are categorized into data-intensive tasks or logic-processing tasks based on their computational characteristics. Coarse-grained planning tasks mainly consist of data-intensive subtasks, involving a large amount of parallel, rule-based computation. Fine-grained planning tasks mainly consist of logic-processing subtasks.

[0081] In many preferred examples, the fine planning phase also calls some data calculations (but the complexity is not high), while the coarse planning phase also includes simple logical judgments.

[0082] In typical cases, the tasks assigned to the DSP are mainly data-intensive tasks, and their output is the result of coarse planning; while the tasks assigned to the CPU are mainly logic processing tasks, which are fine planning based on the result of coarse planning.

[0083] Module MA.2 monitors the CPU and DSP load in real time during the calculation process, including parameters such as computing resource utilization and task queue length.

[0084] Running a multi-DSP redundancy architecture specifically includes:

[0085] Module MB.1 and multiple DSPs are configured with the same computing tasks and parameters during initialization and start working simultaneously.

[0086] Module MB.2 establishes a real-time communication mechanism between DSPs, which monitors each other's working status by periodically sending heartbeat signals and task status information.

[0087] Module MB.3: Under normal operating conditions, the two DSPs work simultaneously, backing up each other and monitoring each other's working status in real time; when one DSP fails, the other DSP can immediately take over the task of the failed DSP and continue to complete the task planning calculation.

[0088] Specifically, when any DSP detects a fault in one of its DSPs (such as multiple consecutive failures to receive heartbeat signals, abnormal calculation results, etc.), the redundancy switching mechanism is immediately triggered. The remaining DSPs can immediately take over the task queue of the faulty DSP and continue to complete the remaining task planning calculations, ensuring that the entire task planning calculation process is uninterrupted and effectively avoiding calculation failures caused by the failure of a single computing unit.

[0089] Meanwhile, the system records fault information for subsequent fault diagnosis and repair, which greatly enhances the reliability and stability of the satellite computing platform in complex space environments and reduces the risk of data processing failure due to hardware failure.

[0090] Module MA.3 dynamically adjusts the computational load ratio based on different stages of task planning and computational requirements, combined with the load conditions of the CPU and DSP.

[0091] In more preferred examples, during the data acquisition and preliminary processing stages, 80% of the computational load is allocated to the DSP and 20% to the CPU; during the result optimization and fine-tuning stages, the load is adjusted to 30% to the DSP and 70% to the CPU.

[0092] Module MA.4, the scheduler, adopts a task queue and priority scheduling mechanism to ensure that tasks can be reasonably allocated and executed between the CPU and DSP according to priority order, avoiding task blocking and resource waste.

[0093] Specifically, for the specific hardware environment of CPU and multi-DSP redundant architecture, the conventional scheduling mechanism has been deeply adjusted and customized to achieve the core goals of heterogeneous collaboration and fault tolerance, including:

[0094] Heterogeneous task identification and dispatch: It is necessary to distinguish the task type and dynamically assign it to the most suitable processing unit (CPU or DSP).

[0095] Multi-DSP dynamic load balancing: It is necessary to monitor the load of each DSP in real time and intelligently allocate tasks to the least idle DSP to achieve efficient parallelism.

[0096] Fault-tolerant scheduling integration: The scheduler works in conjunction with the heartbeat monitoring mechanism to immediately isolate a DSP in case of failure and automatically reassign its tasks to a healthy DSP. This is the core of achieving high system reliability.

[0097] Task dependency management: The scheduler needs to manage the data dependencies between CPU tasks and DSP tasks to ensure the correctness of the data processing flow.

[0098] By parallelizing the computationally intensive task planning using multiple DSPs and refining the coarse planning results using the CPU, combined with algorithm optimization to dynamically adjust the computational load, this approach significantly improves processing efficiency while maintaining computational accuracy compared to traditional single-core serial processing. It enables rapid processing of massive amounts of data, meeting real-time requirements. Simultaneously, it enhances the reliability of the satellite computing platform to meet the high-efficiency and stable needs of satellite mission planning computation in various applications.

[0099] According to the present invention, a method for dynamic allocation of computing power for satellite mission planning based on heterogeneous multi-core processors is provided. Figure 1 For example, including:

[0100] Step S1: Satellite reception mission planning requirements.

[0101] Step S2: Data is transferred to shared memory;

[0102] Specifically, the raw mission planning data collected by the satellite is transmitted to shared memory.

[0103] The task planning requirements are the highest-level user instructions, serving as the starting point and objective of task planning. They are typically expressed in natural language or as high-level descriptive documents, such as: "Achieve full coverage observation of a certain area within the next 24 hours" or "Prioritize disaster monitoring requests for a certain area."

[0104] The raw mission planning data is structured input data generated by the satellite system after parsing and parameterizing the mission planning requirements. It is directly usable by the processor and is transmitted to shared memory. Examples include: the latitude and longitude coordinate boundaries of the target area, mission priority weights, satellite platform energy constraints, storage constraints; payload (camera, radar) performance parameters (side swing angle range, resolution); and satellite orbit ephemeris data.

[0105] Step S3: The CPU and DSP access shared memory to obtain data.

[0106] Step S4: Multiple DSPs process the data in parallel to generate coarse planning results and store them in shared memory;

[0107] Specifically, multiple DSPs read the raw task planning data from shared memory, execute computationally intensive tasks such as data filtering, feature extraction, and preliminary modeling in parallel, generate coarse planning results, and store the results back into shared memory.

[0108] The task planning computation task refers to the specific data processing process within the system. The heterogeneous task partitioning module decomposes the original task planning data into a series of specific computation tasks (data-intensive tasks, logic processing tasks, etc.) and dynamically allocates them to the DSP or CPU for execution. For example: "Visible time window of computation grid A1".

[0109] Step S5: The CPU reads the coarse planning result from the shared memory, processes it to generate the fine planning result, and outputs it.

[0110] Specifically, the CPU reads the coarse planning results generated by the DSP from shared memory, and based on the real-time mission planning characteristics, uses complex logical algorithms and optimization strategies to perform fine planning processing on the coarse planning results, including mission planning smoothing, boundary optimization, outlier correction, etc., and finally generates an accurate satellite mission plan.

[0111] The real-time task planning features are key information and decision-making criteria extracted by the CPU from the coarse planning results generated by the DSP during the fine planning process. They are derived features generated after preliminary processing and analysis of the original task planning data. For example:

[0112] Conflict characteristics: Points of conflict in time or resources among multiple tasks identified from the coarse planning results.

[0113] Efficiency characteristics: Evaluation of the overall efficiency (such as energy utilization rate and total time) that different task execution sequences may bring.

[0114] Opportunity characteristic: Unplanned observation opportunities discovered.

[0115] Quality characteristics: Indicators that affect the final planning quality, such as the confidence level of certain data in the coarse planning results and the cloud coverage ratio.

[0116] In more preferred embodiments, the CPU is a model with logic control and task scheduling capabilities, and the DSP is a model with high-speed parallel data processing capabilities.

[0117] The shared memory is constructed using high-speed and high-capacity storage chips.

[0118] The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, with the interconnect lines between the multiple DSPs arranged symmetrically.

[0119] The DSP consists of 2 to 4 modules, with multiple DSPs operating simultaneously, providing mutual backup, and monitoring their operational status in real time. A multi-DSP redundancy architecture is employed, including:

[0120] Multiple DSPs are configured with the same type and parameters for planning calculation tasks and start working simultaneously.

[0121] Multiple DSPs periodically send heartbeat signals and status information to each other, backing up each other and monitoring each other's status information;

[0122] When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information.

[0123] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors, characterized in that, include: The module for dynamic allocation of computing power and the module for heterogeneous task partitioning are planned. The dynamic allocation module for computing power planning includes a CPU, a DSP, and shared memory; Multiple DSPs work together to decompose the planning calculation task based on the original task planning data and execute it in parallel to generate coarse planning results. The CPU extracts the real-time mission planning features from the coarse planning results, performs fine planning processing to generate satellite mission planning results, and outputs them. Shared memory is connected to the CPU and DSP via a high-speed bus to store raw task planning data and coarse planning results. The heterogeneous task partitioning module dynamically adjusts the computing load ratio between the DSP and CPU based on the original task planning data; The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, and the high-speed bus between the CPU, DSPs, and shared memory follows equal-length wiring and impedance control.

2. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1, characterized in that, The DSP consists of 2 to 4 DSPs, with multiple DSPs working simultaneously, backing each other up, and monitoring their working status in real time. The CPU is a model with logic control and task scheduling capabilities, and the DSP is a model with high-speed parallel data processing capabilities. The shared memory is constructed using high-speed and high-capacity storage chips, and the interconnection lines between multiple DSPs are arranged symmetrically.

3. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1, characterized in that, The DSP adopts a multi-DSP redundancy architecture, including: Multiple DSPs are configured with the same type and parameters for planning calculation tasks and start working simultaneously. Multiple DSPs periodically send heartbeat signals and status information to each other, backing up each other and monitoring each other's status information; When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information.

4. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 3, characterized in that, If any DSP fails to receive a heartbeat signal from any other DSP for several consecutive times or determines that the planning calculation result is abnormal, it is marked as a faulty DSP and the redundancy switching mechanism is immediately triggered. The remaining DSPs immediately take over the task queue of the faulty DSP and continue to complete the remaining planning calculation tasks.

5. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 1, characterized in that, When the type of the planned computing task is a data-intensive task, the heterogeneous task partitioning module allocates more than 50% of the computing load to the DSP and the remaining computing load to the CPU. When the type of computational task planned is a logical processing task, increase the computational load on the CPU.

6. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 5, characterized in that, The heterogeneous task partitioning module includes: Module MA.1 analyzes and decomposes the planning calculation task to obtain sub-tasks; Module MA.2 monitors the CPU and DSP load in real time when executing subtasks; Module MA.3: Dynamically adjust the computational load ratio based on the type of subtask and the load conditions of the CPU and DSP; Module MA.4: The scheduler allocates CPU and DSP to execute subtasks according to the set task queue and priority scheduling mechanism.

7. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 6, characterized in that, The types of subtasks include data-intensive tasks and logic processing tasks; The load conditions include computing resource utilization and task queue length; In module MA.3, for data-intensive tasks, 80% of the computing load is allocated to the DSP and 20% to the CPU; for logic processing tasks, 30% of the computing load is allocated to the DSP and 70% to the CPU.

8. The satellite mission planning computing power dynamic allocation system based on heterogeneous multi-core processors according to claim 6, characterized in that, The scheduler includes: The heterogeneous task identification and dispatch module identifies the types of subtasks and assigns them to the corresponding CPUs or DSPs based on their types. The dynamic load balancing module detects the real-time load of the DSP and allocates subtasks to the DSP with the lowest resource utilization or the shortest task queue length. The fault-tolerant scheduling integration module detects the status information of the DSP, isolates the faulty DSP, and allocates its subtasks in the task queue to the remaining DSPs. The task dependency management module manages the data dependencies between subtasks executed by the CPU and DSP.

9. A method for dynamic allocation of computing power for satellite mission planning based on heterogeneous multi-core processors, comprising using the dynamic allocation system for satellite mission planning based on heterogeneous multi-core processors as described in any one of claims 1-8 for computing power allocation, characterized in that, include: Step S1: The satellite receives the mission planning requirements, parses them into the original mission planning data, and transmits it to shared memory; Step S2: The DSP accesses the shared memory to read the original task planning data and decomposes it into planning calculation tasks. The tasks are executed in parallel to generate coarse planning results and stored in the shared memory. Step S3: The CPU accesses shared memory to read the coarse planning results, extracts real-time task planning features, performs fine planning processing to generate satellite mission planning results, and outputs them. The CPU, multiple DSPs, and shared memory are integrated on the same circuit board, and the high-speed bus between the CPU, DSPs, and shared memory follows equal-length wiring and impedance control.

10. The method for dynamic allocation of computing power for satellite mission planning based on heterogeneous multi-core processors according to claim 9, characterized in that, The CPU is a model with logic control and task scheduling capabilities, and the DSP is a model with high-speed parallel data processing capabilities. The shared memory is constructed using high-speed and high-capacity storage chips, and the interconnection lines between multiple DSPs are arranged symmetrically. The DSP consists of 2 to 4 modules, with multiple DSPs operating simultaneously, providing mutual backup, and monitoring their operational status in real time. A multi-DSP redundancy architecture is employed, including: Multiple DSPs are configured with the same type and parameters for planning calculation tasks and start working simultaneously. Multiple DSPs periodically send heartbeat signals and status information to each other, backing up each other and monitoring each other's status information; When any DSP fails, the remaining DSPs immediately take over the tasks of the failed DSP, continue to complete the task planning and calculation work, and record the fault information.

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