Chip communication interface test system and method

Abstract

The invention provides a chip communication interface test system and method, an upper computer configures a to-be-tested chip into a write mode through a first interface board and sends a write instruction of the test to a switch chip, and the write instruction comprises at least one interface board identifier; the switch chip forwards the write instruction to a plurality of second interface boards; when the second interface board is matched with any interface board identifier in the writing instruction, target data corresponding to the writing instruction is written into the to-be-tested chip; after the write instruction of the current round of test is executed, the upper computer configures the to-be-tested chip into a read mode through the first interface board, reads data written by the to-be-tested chip in the current round of test, and compares the read data with corresponding target data to generate a test result indicating whether the communication interface is qualified or not. The test system is simple in structure, high in test efficiency and higher in accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of testing, in particular to a chip communication interface test system and method. BACKGROUND

[0002] With the increasing number of interconnected devices, the ordinary serial communication interface becomes a bottleneck limiting the communication rate, and the communication interface needs to be improved. For this purpose, the Improved Inter-Integrated Circuit (I3C) communication interface emerges as the times require. The I3C communication interface provides a simple, high-speed, high-bandwidth bus design for the system through the clock line (Serial Clock Line, SCL) and the data line (Serial Data Line, SDA), and the corresponding transmission rate can reach 12.5MHz.

[0003] The I3C Hub chip provided with the I3C communication interface can be applied to peripheral expansion. At present, there are still many System Management Bus (SMBus) devices and Inter-Integrated Circuit (I2C) devices on the market. In some scenarios, I2C, SMBus and I3C may be mixed. Therefore, it is necessary to integrate the corresponding communication interfaces of I2C, SMBus and I3C on the I3C Hub chip.

[0004] The number of communication interfaces on the I3C Hub chip is large, and the protocol is complex. Under such circumstances, how to efficiently and accurately complete the test work of the communication interface on the I3C Hub chip has become a difficult problem for technicians in the field. SUMMARY

[0005] The purpose of the present application is to provide a chip communication interface test system and method to improve the above problems.

[0006] In order to achieve the above purpose, the technical scheme adopted by the embodiments of the present application is as follows: In a first aspect, the embodiments of the present application provide a chip communication interface test system, which comprises: a host computer, a first interface board, a switch chip and a plurality of second interface boards. The host computer is connected with the first interface board, the first interface board is connected with the switch chip, and the first interface board is further used to connect the main port of the chip to be tested. The first port of each of the plurality of second interface boards is connected to the switch chip, and the second port of the second interface board is used to connect the corresponding slave port on the chip to be tested. The host computer is configured to configure the chip under test to a write mode through the first interface board, and send a write instruction of the current test to the switch chip, the write instruction comprising at least one interface board identifier; The switch chip is configured to forward the write instruction to the plurality of second interface boards; The second interface board is configured to write target data corresponding to the write instruction into the chip under test when the interface board identifier in the write instruction matches; After the write instruction of the current test is executed, the host computer is further configured to configure the chip under test to a read mode through the first interface board, read data written into the chip under test in the current test, and compare the read data with the corresponding target data to generate a test result corresponding to the communication interface.

[0007] In the chip communication interface test system provided by the embodiment of the application, target data is first written into the chip under test through the slave port of the chip under test, and then read, and the host computer compares the read data with the corresponding target data to generate a test result indicating whether the communication interface is qualified. The test system has a simple structure, high test efficiency, and higher accuracy.

[0008] Optionally, the write instruction comprises a data write length; and the second interface board is configured to take corresponding target data from an array set stored in the second interface board when the interface board identifier in the write instruction matches, and write the target data into the chip under test; The length of the target data is equal to the data write length in the write instruction, and the first bit of the target data is the first bit in the array set.

[0009] Because the write instruction does not comprise target data, only the data write length is carried. The data amount of the write instruction itself can be reduced, and the transmission speed of the write instruction is improved. In addition, the array set in different second interface boards can be different, so that when the write instruction is executed, even if the data write length is the same, the target data of different second interface boards can be different, thereby ensuring the diversity of the written data and improving the comprehensiveness of the test.

[0010] Optionally, the host computer is configured to send a read instruction of the current test to the switch chip through the first interface board, the read instruction comprising the same interface board identifier as the write instruction of the current test; The switch chip is configured to forward the read instruction to the plurality of second interface boards; The second interface board is configured to read data written into the chip under test by itself in the current test when the interface board identifier in the read instruction matches, and feed back the read data to the switch chip, the read data comprising the interface board identifier of the second interface board. The switch chip is configured to send the read data received in the current test to the host computer through the first interface board; The host computer is configured to compare the read data with the corresponding target data to generate a test result corresponding to the target communication interface; The target communication interface is a slave port in the chip under test, and the target communication interface is connected with a second interface board corresponding to the interface board identifier in the read data.

[0011] In the test process, the second interface board writes data to the chip under test (corresponding to the execution process of the write instruction), and the chip under test feeds back data to the second interface board (corresponding to the execution process of the read instruction), so that the write side and the read side of the slave port are directly verified. When either the write side or the read side of the slave port is unqualified, the test result indicates that the target communication interface is unqualified, thereby improving the test efficiency and accuracy.

[0012] Optionally, the host computer is configured to determine a target data set corresponding to the read data according to the interface board identifier in the read data; and the host computer is configured to determine the target data corresponding to the read data from the target data set according to the data write length in the write instruction of the current test.

[0013] By accurately obtaining the target data corresponding to each piece of read data, the accuracy of the test result is ensured.

[0014] Optionally, the chip under test is configured to, after being configured in a read mode, take the data written by the chip under test in the current test as first read data, and send the first read data to the host computer. Each piece of first read data includes an interface board identifier of a second interface board corresponding thereto. The host computer is configured to compare the first read data with the corresponding target data to generate a first test result corresponding to the target communication interface; The target communication interface is a slave port in the chip under test, and the target communication interface is connected with a second interface board corresponding to the interface board identifier in the read data.

[0015] After the test of the write side is completed, the host computer is configured to send a read instruction of the current test to the switch chip through the first interface board. The read instruction includes the same interface board identifier as the write instruction of the current test, or includes an interface board identifier of a target communication interface that passes the write test. The switch chip is configured to forward the read instruction to the plurality of second interface boards; The second interface board is configured to read data written by itself in the current test into the chip under test when the interface board identification matches any of the read instructions, and feed back second type read data to the switch chip, wherein the second type read data comprises the interface board identification of the second interface board. The switch chip is configured to send the second type read data received in the current test to the host computer through the first interface board. The host computer is configured to compare the second type read data with corresponding target data to generate a second test result corresponding to the target communication interface. The second test result indicates whether the target communication interface is qualified in the read test.

[0016] By comparing in stages, it can be accurately determined whether the from port is qualified in the write test and the read test, and the problem can be accurately located, thereby ensuring the accuracy of the test result and being beneficial to subsequent maintenance.

[0017] In a second aspect, an embodiment of the present application provides a chip communication interface test method applied to the chip communication interface test system, and the method comprises the following steps. The host computer configures the chip under test as a write mode through the first interface board, and sends a write instruction of the current test to the switch chip, wherein the write instruction comprises at least one interface board identification. The switch chip forwards the write instruction to a plurality of second interface boards. The second interface board writes target data corresponding to the write instruction into the chip under test when the interface board identification matches any of the write instructions. After the write instruction of the current test is executed, the host computer further configures the chip under test as a read mode through the first interface board, reads data written into the chip under test in the current test, and compares the read data with corresponding target data to generate a test result corresponding to the communication interface.

[0018] In a third aspect, an embodiment of the present application provides a chip communication interface test method applied to a host computer in the chip communication interface test system, and the method comprises the following steps. The host computer configures the chip under test as a write mode through the first interface board. The host computer sends a write instruction of the current test to the switch chip, so that the switch chip forwards the write instruction to a plurality of second interface boards, so that the second interface board writes target data corresponding to the write instruction into the chip under test when the interface board identification matches any of the write instructions, wherein the write instruction comprises at least one interface board identification. After the execution of the write instruction in the current test is completed, the upper computer further configures the chip under test into a read mode through the first interface board, reads the data written into the chip under test in the current test, and compares the read data with the corresponding target data to generate a test result corresponding to the communication interface.

[0019] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following preferred embodiments are specifically described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0021] Figure 1 A connection schematic diagram of a chip communication interface test system provided by the embodiments of the present application.

[0022] Figure 2 A flowchart of a chip communication interface test method provided by the embodiments of the present application.

[0023] Figure 3 A flowchart of a chip communication interface test method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the embodiments of the present application more apparent, the following will combine the drawings in the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application, and obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0026] It should be noted that similar reference numerals and letters refer to like items throughout the accompanying drawings, and once an item is defined in one drawing, it is not necessary to further define and explain it in the subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0027] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0028] In order to efficiently and accurately complete the test work of the communication interface on the chip, the embodiments of the present application provide a chip communication interface test system, please refer to Figure 1 , Figure 1 A connection diagram of a chip communication interface test system provided by the embodiments of the present application.

[0029] The test system comprises a host computer, a first interface board, a switch chip and a plurality of second interface boards. Among them, the first interface board can be but is not limited to a microcontroller unit (MCU) interface board, the switch chip can be but is not limited to an I2C switch chip, and the second interface board can be but is not limited to an MCU interface board. Among them, the number of second interface boards can be but is not limited to 4 or 8.

[0030] The MCU interface board in the embodiments of the present application can use the same program code, thereby reducing the development workload of the staff.

[0031] The host computer is connected with the first interface board, as Figure 1 shown, the host computer and the first interface board can be connected by a universal serial bus (USB). Of course, the host computer and the first interface board can also be connected by other types of buses, which are not limited here.

[0032] The first interface board is connected with the switch chip, and the first interface board is also used to connect the main port of the chip to be tested, which can be but is not limited to an I3C Hub chip. As Figure 1 shown, the first interface board and the switch chip, and the chip to be tested can be connected by I2C. Of course, the first interface board and the switch chip, and the chip to be tested can also be connected by other types of buses, which are not limited here. It should be noted that the host computer device has no free port compatible with the switch chip and the chip to be tested, if there is, the first interface board can be skipped.

[0033] The first ports of the plurality of second interface boards are connected to the switch chip, respectively, as Figure 1As shown, I2C connection can be adopted between the second interface board and the switch chip. Of course, other types of buses can also be adopted for connection between the second interface board and the switch chip, which is not limited herein.

[0034] The second port of the second interface board is used for connecting a corresponding slave port on the chip under test, such as Figure 1 As shown, I2C and / or SMBus connection can be adopted between the second interface board and the slave port of the chip under test. Of course, other types of buses can also be adopted for connection between the second interface board and the chip under test, which is not limited herein.

[0035] In an optional embodiment, the switch chip, the second interface board and the chip under test can be deployed on the same board (which can be but is not limited to an I3C Hub board), the second interface board can be fixed to the board through a board-to-board (BTB) connector, so as to connect the first port of the second interface board to a port of the switch chip and connect the second port of the second interface board to a slave port of the chip under test. The switch chip, the second interface board and the chip under test form a whole circuit board, which can reduce the area of the circuit board.

[0036] In the chip communication interface test system provided by the embodiments of the present application, the MCU interface board is used to complete related test projects, which has lower hardware cost and simpler connection lines of external interfaces compared with using a universal serial bus and an integrated circuit bus converter (advark trainer).

[0037] In an optional embodiment, the second interface board can be fixed to the board through a Sub-Miniature A (SMA) connector, so as to connect the first port of the second interface board to a port of the switch chip and connect the second port of the second interface board to a slave port of the chip under test. Compared with fixing by the BTB connector, only part of the connection lines need to be added when fixing by the SMA connector.

[0038] In the chip communication interface test system provided by the embodiments of the present application, the second interface board can simulate the host and the slave in the communication process, and is multiplexed to test different communication interfaces, which is repeatedly tested and used, thereby reducing the test cost.

[0039] On the basis of the foregoing, regarding the specific test process, an optional embodiment is further provided by the embodiments of the present application, which is described below.

[0040] The host computer is configured to configure the chip under test as a write mode through the first interface board, and send a write instruction of the current test to the switch chip, the write instruction comprising at least one interface board identifier. The interface board identifier in the write instruction is the identifier of the second interface board connected to the slave port in the chip under test which needs to be tested.

[0041] The switch chip is used to forward the write instruction to the plurality of second interface boards.

[0042] In the embodiment of the present application, the switch chip is used to distribute the instructions (including the write instruction and the read instruction), thereby reducing the occupation of the host computer resources.

[0043] The second interface board is used to write the target data corresponding to the write instruction into the chip to be tested when any interface board identifier in the write instruction matches.

[0044] In an optional embodiment, the write target address corresponding to each second interface board is pre-configured, the write target addresses corresponding to different second interface boards are different, the write target address corresponding to the same second interface board is the same when the second interface board executes the write instruction each time, and the write target address is a storage address in the chip to be tested. The write target address is used as the starting address of the target data to be written.

[0045] When the write instruction includes a plurality of interface board identifiers, the target data written into the chip to be tested by the second interface boards matched by different interface board identifiers can be different or the same.

[0046] After the execution of the write instruction in the current test is completed, the host computer is further used to configure the chip to be tested into a read mode through the first interface board, read the data written into the chip to be tested in the current test, and compare the read data with the corresponding target data to generate the test result corresponding to the communication interface.

[0047] In the chip communication interface test system provided by the embodiment of the present application, the target data is first written into the chip to be tested through the slave port of the chip to be tested, and then read. The host computer compares the read data with the corresponding target data to generate the test result indicating whether the communication interface is qualified. The test system has a simple structure, high test efficiency, and higher accuracy.

[0048] In an optional embodiment, the write instruction further includes the target data to be written into the chip to be tested. The data amount of the write instruction is affected by the length of the target data, and the transmission time of the write instruction can be too long.

[0049] In an optional embodiment, the write instruction includes the data write length. As to how the second interface board writes the target data corresponding to the write instruction into the chip to be tested, the embodiment of the present application further provides an optional embodiment, which is described below.

[0050] The second interface board is used to take the corresponding target data from the array set stored in the second interface board when any interface board identifier in the write instruction matches, and write the target data into the chip to be tested. The length of the target data is equal to the data write length in the write instruction, and the first bit of the target data is the first bit in the array set.

[0051] Since the target data is not included in the write instruction, only the data write length is carried. The data amount of the write instruction itself can be reduced, and the transmission speed of the write instruction is improved.

[0052] In addition, the array set in different second interface boards can be different, so that when the write instruction is executed, even if the data write length is the same, the target data of different second interface boards can be different, thereby ensuring the diversity of the write data and improving the comprehensiveness of the test.

[0053] In an optional embodiment, the write instruction includes an instruction identifier. The application also provides an optional embodiment for how the second interface board writes the target data corresponding to the write instruction to the chip under test, please refer to the following.

[0054] The second interface board is configured to, when matching any interface board identifier in the write instruction, take the target data corresponding to the instruction identifier from the instruction set stored in the second interface board, and write the target data to the chip under test.

[0055] It should be understood that the host computer stores the instruction set of each second interface board, so that when it is necessary to compare the read data with the target data, the read data corresponding target data can be determined from the target instruction set according to the instruction identifier in the write instruction. The target instruction set is the instruction set corresponding to the interface board identifier in the read data.

[0056] On the basis of the foregoing, the application also provides an optional embodiment for how the host computer reads the data in the chip under test, please refer to the following.

[0057] The host computer is configured to send a read instruction of the current test to the switch chip through the first interface board, the read instruction including the same interface board identifier as the write instruction of the current test.

[0058] The switch chip is configured to forward the read instruction to the plurality of second interface boards.

[0059] The second interface board is configured to, when matching any interface board identifier in the read instruction, read the data written to the chip under test by itself in the current test, and feed back the read data to the switch chip, the read data including the interface board identifier of the second interface board.

[0060] It should be understood that the read data fed back by the nth second interface board includes the interface board identifier of the nth second interface board, and 1≤n≤the total number of second interface boards.

[0061] Optionally, the second interface board is configured to read data of a preset length from a read target address in the to-be-tested sub-chip, as the read data, wherein the read target address is the same as the write target address in the current test, and the preset length is the length of the target data written in the current test, which can be the data write length in the write instruction.

[0062] The switch chip is configured to send the read data received in the current test to the host computer through the first interface board.

[0063] The host computer is configured to compare the read data with the corresponding target data to generate a test result corresponding to the target communication interface, wherein the target communication interface is a slave port in the to-be-tested chip, and the target communication interface is connected to the second interface board corresponding to the interface board identifier in the read data.

[0064] When the read data is consistent with the corresponding target data, the test result indicates that the target communication interface is qualified; when the read data is different from the corresponding target data, the test result indicates that the target communication interface is unqualified.

[0065] In the test process, the second interface board writes data into the to-be-tested chip (corresponding to the write instruction execution process), and the to-be-tested chip feeds back data to the second interface board (corresponding to the read instruction execution process), so that the write side and the read side of the slave port are directly verified. When either the write side or the read side of the slave port is unqualified, the test result indicates that the target communication interface is unqualified, thereby improving the test efficiency and accuracy.

[0066] In an optional embodiment, the target data corresponding to all write instructions in the current test is the same, which is uniformly issued by the host computer to the second interface board. At this time, the target data of the current test is stored in the host computer, and the target data corresponding to all read data is the same, which can be directly compared.

[0067] In an optional embodiment, the target data corresponding to different second interface boards is different. Specifically, please refer to the related content of the write instruction including the data write length or the instruction identifier, which will not be repeated here. In this case, how the host computer obtains the target data corresponding to each read data to ensure the accuracy of the test result is provided in an optional embodiment of the present application, which will be described below.

[0068] The host computer is configured to determine a target data set (or a target instruction set) corresponding to the read data according to the interface board identifier in the read data.

[0069] It should be understood that the host computer stores the data set (or the instruction set) corresponding to all second interface boards, and the mapping relationship between the interface board identifier and the data set (or the instruction set).

[0070] The host computer is configured to determine target data corresponding to the read data from a target array set (or a target instruction set) according to the data write length in the write instruction of the current test.

[0071] In the test mode described above, when either the slave port write side or the read side is unqualified, the test result indicates that the target communication interface is unqualified, and the specific problem cannot be determined. To this end, an optional embodiment of the present application is provided, which is described below.

[0072] The chip under test is configured to, after being configured in a read mode, send, as first read data, data written into the chip under test in the current test to the host computer, and each piece of first read data includes an interface board identifier of a second interface board corresponding thereto.

[0073] The second interface board corresponding to the first read data is the second interface board that writes the first read data into the chip under test.

[0074] The host computer is configured to compare the first read data with the corresponding target data to generate a first test result corresponding to the target communication interface.

[0075] The target communication interface is a slave port in the chip under test, the target communication interface is connected to a second interface board corresponding to the interface board identifier in the first read data, and the first test result indicates whether the target communication interface is qualified in the write test.

[0076] Optionally, if the first test result indicates that the target communication interface is unqualified in the write test, an error prompt is given.

[0077] The target data is obtained in the manner described above, and details are not described herein.

[0078] After the test on the write side ends, the host computer is configured to send a read instruction of the current test to the switch chip through the first interface board, the read instruction including the same interface board identifier as the write instruction of the current test or including an interface board identifier of a target communication interface that is qualified in the write test.

[0079] The switch chip is configured to forward the read instruction to the plurality of second interface boards.

[0080] The second interface board is configured to, when matching any interface board identifier in the read instruction, read data written into the chip under test in the current test by itself, and feed back second read data to the switch chip, the second read data including an interface board identifier of the second interface board.

[0081] It should be understood that the second read data fed back by the nth second interface board includes an interface board identifier of the nth second interface board, and 1≤n≤total number of the second interface boards.

[0082] Optionally, the second interface board is configured to read data of a preset length from a read target address in the to-be-tested sub-chip, as the second type of read data, wherein the read target address is the same as the write target address in the current round of testing, and the preset length is the length of the target data written in the current round of testing, which can be the data write length in the write instruction.

[0083] The switch chip is configured to send the second type of read data received in the current round of testing to the host computer through the first interface board.

[0084] The host computer is configured to compare the second type of read data with the corresponding target data to generate a second test result corresponding to the target communication interface. The second test result indicates whether the target communication interface is qualified in the read test.

[0085] Optionally, if the second test result indicates that the target communication interface is not qualified in the read test, an error prompt is generated. The target data can be obtained in the manner described above, and thus will not be described here.

[0086] It should be noted that, when testing the chip communication interface, the data written into the to-be-tested chip needs to be changed to meet the requirements of the adaptation protocol (including I2C and SMBus). Therefore, the test items need to be divided into multiple rounds. In order to ensure that all test items are completed, the present embodiment further provides an optional implementation, which is described below.

[0087] After the current round of testing is completed, the host computer is further configured to determine whether the testing of all rounds has been completed. If not, a next round of write instruction is generated, and the next round of testing is carried out based on the next round of write instruction, until the testing of all rounds is completed.

[0088] It should be understood that generating the next round of write instruction can refer to generating the data write length or the instruction identifier in the next round of testing, or refer to generating the target data in the next round of testing.

[0089] After the test result is obtained, a corresponding test report can be generated and printed, and the test includes the test results of each slave port on the to-be-tested chip.

[0090] The present embodiment further provides a chip communication interface testing method applied to the chip communication interface testing system described above. Please refer to Figure 2 The chip communication interface testing method includes S11, S12, S13 and S14, which are described as follows.

[0091] S11, the host computer configures the to-be-tested chip as a write mode through the first interface board, and sends a write instruction of the current round of testing to the switch chip.

[0092] The write instruction includes at least one interface board identifier.

[0093] S12, the switch chip forwards the write instruction to the plurality of second interface boards.

[0094] S13, the second interface board writes the target data corresponding to the write instruction into the chip under test when the write instruction matches any interface board identification in the write instruction.

[0095] S14, after the execution of the write instruction in the current test is completed, the host computer further configures the chip under test as a read mode through the first interface board, reads the data written into the chip under test in the current test, and compares the read data with the corresponding target data to generate the test result corresponding to the communication interface.

[0096] Optionally, the write instruction includes a data write length, and S13, the second interface board writes the target data corresponding to the write instruction into the chip under test when the write instruction matches any interface board identification in the write instruction, includes S131, which is specifically described as follows.

[0097] S131, the second interface board takes the target data corresponding to the write instruction from the array set stored in the second interface board when the write instruction matches any interface board identification in the write instruction, and writes the target data into the chip under test, wherein the length of the target data is equal to the data write length in the write instruction, and the first bit of the target data is the first bit in the array set.

[0098] The embodiment of the application further provides a chip communication interface test method applied to the host computer in the chip communication interface test system, please refer to Figure 3 , the chip communication interface test method includes S21, S22 and S23, which are specifically described as follows.

[0099] S21, the host computer configures the chip under test as a write mode through the first interface board.

[0100] S22, the host computer sends the write instruction of the current test to the switch chip, so that the switch chip forwards the write instruction to the plurality of second interface boards, so that the second interface board writes the target data corresponding to the write instruction into the chip under test when the write instruction matches any interface board identification in the write instruction, and the write instruction includes at least one interface board identification.

[0101] S23, after the execution of the write instruction in the current test is completed, the host computer further configures the chip under test as a read mode through the first interface board, reads the data written into the chip under test in the current test, and compares the read data with the corresponding target data to generate the test result corresponding to the communication interface.

[0102] In summary, the chip communication interface test system and method provided by the embodiment of the application, the host computer configures the to-be-tested chip as a write mode through the first interface board, and sends a write instruction of the current test to the switch chip, the write instruction comprising at least one interface board identifier; the switch chip forwards the write instruction to the plurality of second interface boards; the second interface board writes target data corresponding to the write instruction into the to-be-tested chip when matching any interface board identifier in the write instruction; after the write instruction of the current test is executed, the host computer configures the to-be-tested chip as a read mode through the first interface board, reads the data written into the to-be-tested chip in the current test, and compares the read data with the corresponding target data to generate a test result indicating whether the communication interface is qualified. The test system has a simple structure, high test efficiency, and higher accuracy.

[0103] The preferred embodiments of the application have been described above with the specific details. Obviously, those skilled in the art can make various modifications and variations to the application without departing from the spirit and principle of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall within the scope of the protection of the application.

[0104] It is obvious for those skilled in the art that the application is not limited to the details of the above exemplary embodiments, and the application can be implemented in other specific forms without departing from the spirit or essential characteristics of the application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be regarded as limiting the involved claims.

Claims

1. A chip communication interface test system, characterized in that: The test system includes: a host computer, a first interface board, a switch chip and a plurality of second interface boards; The host computer is connected to the first interface board, the first interface board is connected to the switch chip, and the first interface board is also used to connect to the main port of the chip to be tested; The first ports of the plurality of second interface boards are respectively connected to the switch chip, and the second ports of the second interface boards are used to connect to the corresponding slave ports on the chip to be tested; The host computer is used to configure the chip under test to a write mode through the first interface board, and send a write instruction for this round of testing to the switch chip, wherein the write instruction includes at least one interface board identifier; The switch chip is used to forward the write instruction to the multiple second interface boards; The second interface board is used to write the target data corresponding to the write instruction into the chip under test when matching any interface board identifier in the write instruction; After the execution of the write instructions of this round of testing is completed, the host computer is also used to configure the chip to be tested to read mode through the first interface board, read the data written by the chip to be tested in this round of testing, and compare the read data with the corresponding target data to generate a test result corresponding to the communication interface.

2. The chip communication interface testing system according to claim 1, wherein: The write instruction includes the data write length; The second interface board is used to fetch corresponding target data from an array set stored therein when matching any interface board identifier in the write instruction, and write the target data into the chip under test; The length of the target data is equal to the data write length in the write instruction, and the first bit of the target data is the first bit in the array set.

3. The chip communication interface testing system according to claim 1, wherein: The host computer is used to send a read instruction of this round of testing to the switch chip through the first interface board, wherein the read instruction includes the same interface board identifier as the write instruction of this round of testing; The switch chip is used to forward the read instruction to the multiple second interface boards; The second interface board is used to read the data written by itself to the chip under test in this round of testing when matching any interface board identifier in the read instruction, and feed back the read data to the switch chip, wherein the read data includes the interface board identifier of the second interface board; The switch chip is used to send the read data received in this round of testing to the host computer through the first interface board; The host computer is used to compare the read data with the corresponding target data to generate a test result corresponding to the target communication interface; The target communication interface is a slave port in the chip to be tested, and the target communication interface is connected to a second interface board corresponding to the interface board identifier in the read data.

4. The chip communication interface testing system according to claim 3, wherein: The host computer is used to determine the target array set corresponding to the interface board identifier in the read data; The host computer is used to determine the target data corresponding to the read data from the target array set according to the data write length in the write instruction of this round of testing.

5. The chip communication interface testing system according to claim 1, wherein: The chip under test is configured to, after being configured in a read mode, use the data written by the chip under test in the current round of testing as first-category read data, and send the first-category read data to the host computer, wherein each piece of the first-category read data includes an interface board identifier of the corresponding second interface board; The host computer is used to compare the first type of read data with corresponding target data to generate a first test result corresponding to the target communication interface; Among them, the target communication interface is a slave port in the chip to be tested, and the target communication interface is connected to the second interface board corresponding to the interface board identifier in the first type of read data. The first test result indicates whether the target communication interface is qualified during the write test.

6. The chip communication interface testing system according to claim 5, wherein: After the test on the write side is completed, the host computer is used to send a read instruction of this round of test to the switch chip through the first interface board, wherein the read instruction includes the same interface board identifier as the write instruction of this round of test, or includes the interface board identifier of the target communication interface that passed the write test; The switch chip is used to forward the read instruction to the multiple second interface boards; The second interface board is configured to read the data written by itself to the chip under test in this round of testing when matching any interface board identifier in the read instruction, and feed back second-type read data to the switch chip, wherein the second-type read data includes the interface board identifier of the second interface board; The switch chip is used to send the second type of read data received in this round of testing to the host computer through the first interface board; The host computer is used to compare the second type of read data with the corresponding target data to generate a second test result corresponding to the target communication interface; The second test result indicates whether the target communication interface passes the reading test.

7. The chip communication interface testing system according to claim 1, wherein: After the current round of testing is completed, the host computer is further used to determine whether all rounds of testing have been completed. If not, the next round of write instructions is generated, and the next round of testing is carried out based on the next round of write instructions until all rounds of testing are completed.

8. A chip communication interface testing method, characterized in that: The chip communication interface testing system according to any one of claims 1 to 7, wherein the method comprises: The host computer configures the chip to be tested into a write mode through the first interface board, and sends a write instruction for this round of testing to the switch chip, wherein the write instruction includes at least one interface board identifier; The switch chip forwards the write instruction to multiple second interface boards; When the second interface board matches any interface board identifier in the write instruction, the second interface board writes the target data corresponding to the write instruction into the chip under test; After the execution of the write instructions of this round of testing is completed, the host computer also configures the chip to be tested to read mode through the first interface board, reads the data written by the chip to be tested in this round of testing, and compares the read data with the corresponding target data to generate a test result corresponding to the communication interface.

9. The chip communication interface testing method according to claim 8, wherein: The write instruction includes a data write length, and when the second interface board matches any interface board identifier in the write instruction, the second interface board writes the target data corresponding to the write instruction into the chip under test, including: When the second interface board matches any interface board identifier in the write instruction, the second interface board takes the corresponding target data from the array set stored therein and writes the target data into the chip under test; The length of the target data is equal to the data write length in the write instruction, and the first bit of the target data is the first bit in the array set.

10. A chip communication interface testing method, characterized in that: The method applied to a host computer in a chip communication interface test system according to any one of claims 1 to 7 comprises: The host computer configures the chip to be tested into a write mode through the first interface board; The host computer sends a write instruction for this round of testing to the switch chip, causing the switch chip to forward the write instruction to multiple second interface boards, so that the second interface boards, when matching any interface board identifier in the write instruction, execute the write instruction and write target data corresponding to the write instruction into the chip under test, wherein the write instruction includes at least one interface board identifier; After the execution of the write instructions of this round of testing is completed, the host computer also configures the chip to be tested to read mode through the first interface board, reads the data written by the chip to be tested in this round of testing, and compares the read data with the corresponding target data to generate a test result corresponding to the communication interface.

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