Address management command processing method and device, electronic equipment and storage medium

Abstract

The invention discloses a command processing method and device for address management, electronic equipment and a storage medium, and relates to the technical field of computers. And comprehensive processing is carried out according to an overlapping detection result of a logic block address and a pre-stored address and an operation type when the command is processed, so that each command from different central processing units and a processing result thereof are ensured to always keep strict matching and consistency on a hardware level; the technical problems of command response disorder and system reliability reduction caused by the fact that a processing result of a hardware address management module under a multi-central processing unit architecture cannot be correctly routed are solved, and the technical effect of remarkably improving the data processing efficiency and the overall performance of the multi-core solid state disk controller is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a command processing method and device for address management, an electronic device and a storage medium. BACKGROUND

[0002] With the rapid development of information technology, the global data volume presents explosive growth, and higher requirements are put forward for the capacity and read-write performance of data storage equipment. The traditional mechanical hard disk has gradually been difficult to meet the demand of large-scale data application in read-write speed and storage density due to its mechanical structure. Therefore, a new type of storage medium represented by solid state disk (SSD) emerges as the times require. The solid state disk relies on flash memory particles as storage units, and its access mechanism is essentially different from that of mechanical hard disk, and it needs to realize data read-write operation through a special solid state disk controller. In this process, the management of logical block address becomes a key link, and its efficiency directly affects the performance of the overall storage system.

[0003] The existing logical block address management mode includes two types of software implementation and hardware implementation. The software implementation is based on the central processor to perform the address management task, and has high flexibility but occupies a large amount of computing resources; the hardware implementation is processed through a special circuit, has fast response speed and low resource occupation, and is suitable for high-performance solid state disk controllers, but the structure of the logical block address management module of the hardware implementation is usually shared by multiple central processors. Since the processing results of the commands issued by different central processors cannot be accurately distinguished and returned to the corresponding source central processor, it is easy to cause command response disorder, reduce system reliability, and limit the further improvement of the performance of multi-core solid state disk controllers. SUMMARY

[0004] The present application provides a command processing method and device for address management, an electronic device and a storage medium, to at least solve the problem that the address management method based on hardware implementation in the related art cannot correctly return the processing result to the source central processor that initiates the command under the multi-central processor architecture, thereby causing command response disorder.

[0005] The present application provides a command processing method for address management, comprising:

[0006] obtaining a command entry from an input interface, wherein the command entry carries a logical block address and an operation type;

[0007] detecting whether the logical block address overlaps with a pre-stored address in different storage areas to obtain a first detection result;

[0008] processing the command entry according to the first detection result and the operation type to obtain a return result, and outputting the return result to an output interface corresponding to the input interface.

[0009] The application further provides a command processing device for address management, comprising:

[0010] an acquisition module, configured to acquire a command entry from an input interface, wherein the command entry carries a logical block address and an operation type;

[0011] a detection module, configured to detect whether the logical block address overlaps with a pre-stored address in a different storage area, to obtain a first detection result;

[0012] a processing module, configured to process the command entry according to the first detection result and the operation type, to obtain a return result, and output the return result to an output interface corresponding to the input interface.

[0013] The application further provides an electronic device, comprising: a memory, configured to store a computer program; and a processor, configured to execute the computer program to implement the steps of the address management command processing method.

[0014] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the address management command processing method.

[0015] The application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the steps of the address management command processing method.

[0016] According to the application, the output interface strictly corresponding to the input interface is adopted to return the processing result, and the overlap of the logical block address and the pre-stored address in the different storage area is detected in the processing process, and then the operation type is combined for comprehensive judgment, so that the processing result of each command can be accurately returned to the source processing core that originally initiates the command, thereby ensuring the consistency of the command and the response at the hardware level. Therefore, the problem of command response disorder caused by the fact that the result cannot be correctly returned in the hardware address management module under the multi-central processing unit architecture can be solved, and the technical effects of significantly improving the system reliability and the overall performance of the multi-core solid state disk controller are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the specific embodiments of the application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0018] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following embodiments are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0019] Figure 1 The flowchart of the address management command processing method provided by the embodiments of the present application is shown in the figure.

[0020] Figure 2 The working principle diagram of the finite state machine in the control unit provided by the embodiments of the present application is shown in the figure.

[0021] Figure 3 The structure diagram of the address management command processing system provided by the embodiments of the present application is shown in the figure.

[0022] Figure 4 The internal structure diagram of the controller in the address management command processing system provided by the embodiments of the present application is shown in the figure.

[0023] Figure 5 The connection structure diagram of the arbiter in the address management command processing system provided by the embodiments of the present application is shown in the figure.

[0024] Figure 6 The structure block diagram of the address management command processing device provided by the embodiments of the present application is shown in the figure.

[0025] Figure 7 The hardware structure diagram of the computer device provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be clearly and completely described in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0027] It should be noted that, in the description of the present application, the terms “include”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0028] For those skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0029] In combination with the specific application environment architecture or the specific hardware architecture on which the command processing method with address management depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0030] In the present embodiment, a command processing method with address management is provided, Figure 1 is a flowchart of the command processing method with address management according to an embodiment of the present application, as shown in the figure, the flow includes the following steps: Figure 1

[0031] Step S101, obtaining a command entry from an input interface, wherein the command entry carries a logical block address and an operation type.

[0032] In the present embodiment, the command entry is transmitted to the corresponding input interface (Inbound) through a bus (such as AXI bus, Advanced eXtensible Interface BUS), including: operation type (Opcode), such as check, add or delete command; logical block address (LBA), including start address and length; other control information, etc. The number of input interfaces can be extended according to actual needs (for example, 4 or more), and each interface is connected to an independent central processor, ensuring the distinguishability of the command source. The commands issued by different central processors are identified through the address control mechanism, and structured data is provided for subsequent processing. For example, when the central processor 0 issues an add command, the command is transmitted through the input interface 0, and the system records the command source according to the interface number (such as Inbound0) to ensure that the processing result is finally returned to the corresponding output interface 0 (Outbound0).

[0033] In addition, the number of input interfaces can be dynamically configured (such as through register setting), and the commands need to be polled or interrupted according to the number of actually activated interfaces. In order to improve the throughput, a multi-level cache mechanism can also be used to temporarily store burst commands to avoid interface blocking.

[0034] ​After obtaining the command entry from the input interface and parsing the logical block address and operation type, the historical conflict feature library to which the logical block address belongs can be synchronously called, wherein the historical conflict feature library is used to record historical data of overlap between the logical block address and its adjacent address segment (the adjacent range is [the start address of the logical block address - the preset offset, the start address of the logical block address + the preset offset], and the offset can be dynamically adjusted through the configuration register) and the pre-stored addresses in the first region and the second region within a preset statistical period, including the conflict occurrence frequency, the storage region (the first region / the second region) corresponding to each conflict, the conflict resolution time and the associated command type. Based on the above historical conflict data, the current command entry is marked with a conflict risk level: if the historical conflict frequency is greater than or equal to a preset threshold (such as 5 times) or the conflict resolution time of the last time is greater than a preset time length (such as 10 ms), it is marked as high risk; otherwise, it is marked as low risk. At the same time, the conflict risk level and the corresponding historical conflict feature data are written into the extended control field of the command entry (such as adding a bit [127:115] field in the input interface data format, wherein bit

[127] is a risk level identification bit, 1 represents high risk and 0 represents low risk, and bit [126:115] stores the historical conflict frequency code), and the extended field information will be directly used for hardware resource allocation (such as high-risk commands preferentially calling parallel comparators) and detection sequence optimization (such as high-risk commands preferentially detecting the second region) of overlap detection, so as to avoid potential detection delay in advance and improve the predictability and efficiency of conflict processing.

[0035] In step S102, whether the logical block address overlaps with the pre-stored address in the different storage regions is detected to obtain a first detection result.

[0036] In the embodiment of the present application, first, a state query signal is sent to the first region (i.e., the to-be-processed entry cache area composed of the first-in-first-out queue controller) to obtain its current state. The state signal is a key judgment basis for indicating whether there is an unprocessed entry in the first region (Pend). Then, the state signal is received, and different detection paths are executed according to the content of the state signal:

[0037] If the status signal indicates that the first region is not empty, a two-stage sequence detection is initiated: first stage comparison: the logical block address in the command entry is compared with the pre-stored addresses of all pending entries in the first region (Pend) one by one. This process continues until an overlap is found (the P_overlap flag is set immediately) or until all entries are compared (CKQ_DONE = 1), thereby obtaining a first comparison result (i.e., whether there is an overlap with the first region). Second stage comparison: regardless of whether the first stage finds an overlap, as long as it is not ended prematurely due to the finding of an overlap, detection of the second region (i.e., the main storage area composed of static random access memory, which stores non-conflicting allocated entries) is automatically triggered according to the first comparison result (i.e., the conclusion that no overlap with the first region is found). The same logical block address is compared with the pre-stored addresses of all allocated entries in the second region (Array) one by one, and this process continues until an overlap is found (the A_overlap flag is set) or all entries are compared (CKA_DONE = 1), thereby obtaining a second comparison result. Finally, based on the first comparison result and the second comparison result, logical synthesis is performed (for example, if either result is an overlap, there is an overall overlap), and a final first detection result (i.e., a Boolean conclusion of whether the new logical block address overlaps with all storage regions) is generated.

[0038] If the status signal indicates that the first region is empty (i.e., P_EMPTY = 1), the detection process is simplified, the check of the first region is skipped, and the comparison of the logical block address in the command entry with the pre-stored addresses of all allocated entries in the second region (Array) is directly triggered to obtain a third comparison result, and the first detection result is directly generated based on this result.

[0039] In addition, during the comparison process, a hardware parallel comparator or multiple comparison units can be used to compare multiple entries simultaneously, thereby significantly reducing the detection delay and speeding up the generation of the first detection result when the number of entries in the first region (Pend) or the second region (Array) is large.

[0040] Step S103: processing the command entry according to the first detection result and the operation type to obtain a return result, and outputting the return result to an output interface corresponding to the input interface.

[0041] In the embodiments of the present application, the operation type includes but is not limited to a check command, an add command, and a delete command:

[0042] For the check command: the first return result is generated directly based on the first detection result. The core of the result is an overlap flag (Bit

[43] set to 1 in the Outbound format) which explicitly indicates whether the logical block address to be checked overlaps with any address in the storage area. At this time, since no actual data storage operation has occurred, the location information field in the return result is meaningless.

[0043] For the add command: the final storage location of the command entry is determined according to the first detection result: if there is an overlap, the entire command entry is added to the first area (Pend) for temporary storage, and a second return result is generated, which also contains the overlap flag (set to 1), indicating that the addition operation has not been completed immediately due to the conflict, and the entry has been cached; if there is no overlap, the command entry is added to the second area (Array), and a third return result is generated, which contains not only the overlap flag (set to 0), but also the location information of the command entry in the second area (i.e. the Array storage location), which is the necessary address for subsequent deletion operations.

[0044] For the delete command: the processing process is a circular process triggered by subsequent cleaning: first, according to the information in the command entry (such as Bit[114:104]), the corresponding target entry is found in the second area and deleted. Then, since the changes in the second area may have resolved the conflict state of some entries, it is necessary to process each candidate entry in the first area. For each candidate entry, an overlap detection similar to step S102 is performed (to obtain a second detection result), and if there is still an overlap in the result, the candidate entry is stored back to the first area; if the conflict has been resolved, the candidate entry is migrated to the second area, and an intermediate return result is generated for this. Finally, when all entries in the first area have been rechecked and processed, a fourth return result is generated, which reflects the final changes to the states of the two storage areas due to the deletion operation and subsequent cleaning.

[0045] In all cases, after the return result is generated, it is output to the output interface corresponding to the input interface number where the command was originally received. This is achieved by recording the source information (such as the input interface flag in the first area, i.e. the Inbound flag in Pend) in the command entry or the first area entry, thereby ensuring the absolute accuracy of the processing result return in a multi-central processor environment.

[0046] In addition, when an adding operation is performed and the second region needs to be stored, an idle address searching module can also be designed to quickly allocate an empty position in the second region (Array) and write the position information into the return result and the entry in real time, thereby reducing the processing delay; for the circular checking process triggered after the deletion, a hardware accelerator can be used to check the overlap of multiple candidate entries with the second region (Array) in parallel, thereby significantly improving the cleaning efficiency, especially when there are many entries in the first region (Pend); the command receiving strategy can also be dynamically adjusted according to the depth (used amount) of the first region (Pend), for example, when the first region (Pend) is close to full, the deletion command is temporarily slowed down or preferentially processed to release resources, thereby avoiding overflow and enhancing the robustness of the system.

[0047] In the embodiments of the present application, whether the logical block address overlaps with the pre-stored address in the different storage regions is detected to obtain a first detection result, including the following steps A1-A3:

[0048] In step A1, a state query signal is sent to the first region, wherein the first region is a storage region for storing to-be-processed entries.

[0049] Specifically, after obtaining the command entry from the input interface, the finite state machine (FSM) in the control unit (CTL) sends a state query signal to the first-in-first-out queue (FIFO) controller of the first region. The signal is essentially a request to read the empty / full state flag of the first-in-first-out queue. The hardware controller of the first region (Pend) can determine whether there is valid data in the queue based on the positions of the write pointer and the read pointer in the queue, and immediately returns a state signal (for example, a simple level signal: high level indicates "non-empty" and low level indicates "empty").

[0050] In addition, to reduce the communication delay of each query, a state cache register can also be set. When an adding or deleting operation is performed on the first region, the hardware automatically updates the cache register, and the state signal can be directly read from the cache without the need to interact with the first-in-first-out queue controller each time, thereby improving the speed. At the end of system idle or processing of the previous command, the finite state machine can pre-query the state of the first region and temporarily store it. When a new command arrives, the pre-stored state signal can be directly used to make a path decision with almost zero delay. For a complex system, the first region can be composed of multiple queues. At this time, the state query signal can be an address-decoded selection signal for querying the state of a specific queue, thereby achieving more refined management and detection.

[0051] The storage state of the first area is determined by sending a state query signal to the first area, thereby avoiding unnecessary detection overhead. If the first area is empty, it indicates that there is no entry temporarily stored due to previous conflicts, and the comparison of the entire first area can be skipped, and the checking of the second area is directly entered, thereby significantly shortening the detection time and reducing the system delay.

[0052] In step A2, a state signal returned by the first area based on the state query signal is received.

[0053] Specifically, after the control unit (CTL) sends the state query signal, the hardware controller of the first area converts the current empty / full state thereof into an electrical signal as a response, i.e., the state signal. The control logic (such as a finite state machine) samples and latches the value of the signal within one clock cycle, and uses the value as a stable judgment condition for subsequent logic.

[0054] Since the state of the physical storage unit is truly and accurately captured in the control logic, based on the latched signal value, the finite state machine can reliably determine whether to enter the complete process of "checking the first area and the second area" or the simplified process of "only checking the second area", thereby ensuring the correctness and efficiency of the entire detection process.

[0055] In step A3, the corresponding storage area is triggered according to the state signal to perform an overlap detection operation based on the logical block address, and a first detection result is obtained.

[0056] By sending the state query signal, the state of the to-be-processed entry queue can be quickly perceived to provide a decision basis for subsequent operations. Receiving the state signal ensures that the system can respond to the dynamic changes of the storage area in real time. Triggering the detection according to the state signal can adaptively select the most efficient detection path (for example, if the first area is empty, the invalid comparison of the first area is skipped) based on the actual state (empty or non-empty), thereby avoiding unnecessary consumption of hardware resources and detection delay, and significantly improving the efficiency of the overlap detection operation and the overall throughput of the system.

[0057] In the embodiments of the present application, triggering the corresponding storage area to perform an overlap detection operation based on the logical block address according to the state signal to obtain a first detection result comprises:

[0058] If the state signal is a non-empty signal, the logical block address is compared with the pre-stored address of the to-be-processed entry in the first area one by one to obtain a first comparison result, the second area is triggered to perform an address comparison operation based on the logical block address according to the first comparison result to obtain a second comparison result, and the first detection result is generated based on the first comparison result and the second comparison result, wherein the second area is a storage area for storing allocated entries.

[0059] Alternatively, if the status signal is empty, the logical block address is compared with the pre-stored addresses of the allocated entries in the second region one by one to obtain a third comparison result, and the first detection result is generated based on the third comparison result.

[0060] Specifically, as shown in FIG. 2, the finite state machine in the control unit takes the status signal as a branch condition of the initial state to make the following judgments and perform the following operations: Figure 2

[0061] If the status signal is a non-empty signal: it indicates that there are entries to be processed in the first region (Pend), and the address of the new command may conflict with these entries. Therefore, the state machine triggers a two-stage sequence detection. First, the finite state machine enters the "check the first region" (Check Key Pend, CKP) state, compares the logical block address in the command with the pre-stored addresses of all the entries to be processed in the first region one by one to obtain a first comparison result (i.e., whether it overlaps with the first region). Then, regardless of the first-stage result (except that the overlap has been found and the process is ended in advance), the finite state machine automatically enters the "check the second region" (Check Key Array, CKA) state, triggers the comparison of the same logical block address with the pre-stored addresses of all the allocated entries in the second region (Array) one by one to obtain a second comparison result. Finally, the finite state machine performs logical synthesis (such as logical or operation) based on the two comparison results to generate the final first detection result.

[0062] If the status signal is an empty signal: it indicates that the first region (Pend) currently does not store any entries, and the address of the new command is only likely to conflict with the entries in the second region (Array). Therefore, the effective state machine will directly enter the "check the second region" (Check Key Array, CKA) state, trigger the comparison of the logical block address with the pre-stored addresses of the allocated entries in the second region, and directly generate the first detection result based on the third comparison result.

[0063] When the status signal is non-empty, the system can have partial parallel processing capability. For example, while triggering the comparison with the first region, the data of the second region can be prefetched in preparation, or the comparisons of the two regions can be started simultaneously on different hardware comparison units to compress the detection time. The status signal can also include depth information (such as "nearly full") in addition to empty or non-empty. The finite state machine can dynamically adjust the detection strategy according to the depth, for example, when the first region is nearly full, the entries in it are preferentially processed, and the detection of the new command is temporarily suspended, serving as a kind of flow control mechanism.

[0064] ​When the status signal is a non-empty signal, the conflict with the temporary entry can be found in time by the one-by-one comparison with the first area, and the second area comparison triggered on this basis provides a second layer of protection to ensure the absolute accuracy of the detection result; when the status signal is an empty signal, the one-by-one comparison with the second area directly avoids redundant steps, and realizes the shortest path of the detection path. This shunting detection mechanism intelligently allocates hardware comparison resources, maximally shortens the detection time and reduces the system power consumption on the premise of ensuring the correctness of the result.

[0065] It should be noted that the data formats of the input interface, the first area and the output interface are as shown in the following table:

[0066]

[0067] As can be seen from the table, the meanings of the bits in the data format of the input interface are as follows: bit[114:104] represents the position of the logical block address in the second area; bit[103:64] represents the start address of the logical block address, wherein the end address of the logical block address is [start address + address length - 1]; bit[53:32] represents the address length of the logical block address; bit[31:16] represents the operation type identifier; and bit[2:0] represents the command entry, wherein 3’b001 represents a check command for checking whether there is an overlap between the pre-stored address and the logical block address in the first area or the second area; 3’b010 represents an add command for checking whether there is an overlap between the pre-stored address and the logical block address in the first area or the second area, and when there is an overlap, adding the logical block address to the first area, and when there is no overlap, storing the logical block address in the second area and returning the storage position in the second area; and 3’b100 represents a delete command for deleting the entry in the target address that overlaps with the logical block address in the second area, and after the deletion, extracting the candidate entry from the first area, performing overlap detection on the candidate address in the candidate entry with the remaining addresses in the first area and the second area, when there is no overlap, storing the candidate entry in the second area and returning the storage position in the second area, and when there is an overlap, re-adding the candidate entry to the first area.

[0068] The meanings of the bits in the data format of the first area are as follows: bit[105:104] represents the input interface identifier, i.e. the source interface of the command entry; bit

[54] represents the overlap identifier, which is 1 when there is an overlap and 0 when there is no overlap; bit[103:64], bit[53:32], bit[31:16] and bit[2:0] have the same meanings as the corresponding positions in the data format of the input interface;

[0069] The meaning of each bit in the data format of the output interface is as follows: bit

[43] indicates an overlap identifier, and is set to 1 if there is an overlap with the pre-stored address in the first region or the second region, otherwise is set to 0; bit[42:32] indicates the storage position of the command entry in the second region; and bit[3] indicates that the operation type corresponds to the completion of the execution operation, and the return result in the output interface is valid at this time.

[0070] In the embodiment of the present application, when the operation type is the check command, the command entry is processed according to the first detection result and the operation type to obtain a return result, including: generating a first return result based on the first detection result, wherein the first return result includes an overlap identifier, and the overlap identifier is used to indicate whether the logical block address overlaps with the pre-stored address in each storage region.

[0071] Specifically, the first detection result (one Boolean value indicating "there is an overlap" or "there is no overlap") is mapped to a specific field of the return result data structure, which is referred to as an overlap identifier (such as Bit

[43] in the output interface format). If the first detection result indicates that the logical block address overlaps with any one of the pre-stored addresses in the first region (Pend) or the second region (Array), the overlap identifier is set to an effective state (for example, logical 1); otherwise, it is set to an ineffective state (for example, logical 0). Since the check command does not perform addition or deletion operations, it will not change the state of any storage region, and therefore other fields in the return result are meaningless in this scenario and are usually ignored or filled with default values. Finally, this first return result containing the explicit overlap judgment conclusion will be sent out through the output interface corresponding to the input interface number from which the command comes, ensuring that it is collected by the correct central processor.

[0072] In addition to the simple yes / no overlap identifier, the first return result can also include more detailed information. For example, several bits are added to indicate in which region (the first region or the second region) the overlap occurs specifically, and the operation identifier of the entry that overlaps with it, providing more rich debugging and decision-making information for the upper software.

[0073] A simple and efficient processing flow is provided for the check command, and the first return result is generated based on only the first detection result, wherein the overlap identifier directly and explicitly gives the address conflict query answer that the user is interested in, saving processing resources and time, providing a fast state query interface for the upper software, and improving the system decision-making efficiency.

[0074] In the embodiment of the present application, when the operation type is the check command, the command entry is processed according to the first detection result and the operation type to obtain a return result, including the following steps B1-B2:

[0075] Step B1, if the first detection result is that the logical block address overlaps with any pre-stored address in any one of the different storage areas, the command entry is added to the first area, and a second return result is generated, wherein the second return result includes an overlap identifier.

[0076] Specifically, when the operation type is an add command (i.e., an add command) and the first detection result (i.e., the logical block address overlaps with a pre-stored address in the storage area), the finite state machine first determines that there is an overlap according to the first detection result (e.g., the field P_overlap or A_overlap is 1). At this time, the command entry currently obtained from the input interface (e.g., inbound0) is added to the first area (Pend). During the adding process, the input interface number (e.g., inbound0 corresponds to number 0) of the source of the entry is recorded and written to the bit[105:104] field of the first area (Pend) entry, so as to ensure that the subsequent processing result can be returned to the corresponding output interface (e.g., outbound0). At the same time, a second return result (i.e., data in the Outbound format) is generated, wherein the overlap identifier (e.g., bit

[43] ) is set to 1, indicating that there is an overlap, and the position information field (bit[42:32]) is invalid. In addition, the overlap identifier (i.e., the Overlap identifier, such as bit

[54] ) in the first area (Pend) entry is set to 1 (overlapping with the entry in the first area) or 0 (overlapping with the entry in the second area) according to the overlap source, so as to distinguish the overlap type.

[0077] Step B2, if the first detection result is that the logical block address does not overlap with any pre-stored address in the different storage areas, the command entry is added to the second area, and a third return result is generated, wherein the third return result includes an overlap identifier and position information of the command entry in the second area.

[0078] Specifically, when the operation type is an add command and the first detection result is that the logical block address does not overlap with the pre-existing address in the different storage area, the finite state machine control adds the command entry currently obtained from the input interface (such as intbound0) to the second area (Array). An idle physical position (Position) is allocated for the entry in the Array, and the start address, length, and other information of the logical block address are written into the position. Meanwhile, a third return result (i.e. data in the Outbound format) is generated, in which the overlap identifier (bit

[43] ) is 0, indicating no overlap; and the position information in the second area allocated is written into the bit[42:32] field of the return result. In addition, the operation completion flag (bit[3]) in the return result is 1, indicating that the command execution is successful, the operation type identifier (bit[2:0]) is consistent with the original command, and the operation type identifier (bit[31:16]) remains unchanged, to ensure that the CPU can correctly identify that the return result corresponds to the specific command issued by it. Finally, the return result is returned to the central processing unit that initiates the command through the output interface (such as outbound0) corresponding to the input interface number.

[0079] Two-branch processing logic is provided for the add command, ensuring the uniqueness of the address space and the consistency of the data. When there is an overlap, the command entry is added to the first area and a result containing the overlap identifier is generated, effectively buffering the conflicting entries and avoiding data corruption, and immediately notifying the requester of the current status; when there is no overlap, the command entry is added to the second area and the position information thereof is returned, not only completing the address allocation, but also providing a key basis for the subsequent management of the entry. It is ensured that all entries in the second area do not overlap, and temporary conflicts are handled through the first area, enhancing the robustness and fault tolerance of the system.

[0080] In the embodiment of the present application, when the operation type is a delete command, the command entry is processed according to the first detection result and the operation type to obtain a return result, including the following steps C1-C3:

[0081] Step C1, according to the first detection result, determine the target address in the second area that overlaps with the logical block address, and delete the allocated entry corresponding to the target address from the second area.

[0082] Specifically, when the operation type is a delete command, the finite state machine directly locates the target entry in the second area according to the logical block address carried in the command entry obtained from the input interface (such as inbound0), specifically the bit[114:104] field in the input interface data format (which explicitly indicates the specific location information of the entry to be deleted in the second area). This location information is assigned and returned to the central processor by the system when the previous execution of the add command for the target entry is successful, and is now provided by the central processor as it is to perform deletion. Subsequently, the delete operation marks the corresponding storage location of the entry in the second area as "free" or "invalid" (for example, clears the data of the location or resets its valid bit), thereby releasing the storage resource for subsequent add commands. This deletion operation is a prerequisite for processing the pending entries in the first area, because it may have lifted the restriction that caused those entries to have address overlap before.

[0083] Step C2: selecting a candidate entry from the pending entries in the first area, and detecting whether the candidate address of the candidate entry overlaps with the pre-existing addresses in the storage area, to obtain a second detection result.

[0084] Specifically, during the execution of the delete command, after successfully deleting the entry corresponding to the target address from the second area (Array), the pending entries in the first area (Pend) that were temporarily stored due to historical overlap need to be processed. A candidate entry is selected from the first area (usually following the first-in-first-out rule), and its candidate address is detected for overlap with the pre-existing addresses in all storage areas (including the remaining entries in the first area and the remaining entries in the second area). First, check whether the candidate address overlaps with other entries in the first area, and if there is no overlap, further check whether it overlaps with all entries in the second area. According to the detection result (second detection result), the candidate entry is stored back to the first area (when there is still overlap) or migrated to the second area (when there is no overlap), and a return result is generated for the entry that is successfully migrated to the second area. This process is executed in a loop until all entries in the first area are processed, ensuring that the entries that may have lifted the overlap constraint due to the delete operation are timely and correctly allocated and managed.

[0085] In addition, in a specific application scenario, the entries in the first area can be marked with a priority (such as a service type identifier), and a candidate entry with a high priority can be selected preferentially for detection and migration, so as to ensure that the logical block addresses of a key service are preferentially allocated to the second area, and the processing delay is reduced. The strategy for selecting entries from the first area can also be dynamically adjusted according to the system load. For example, during an idle period of the system, all entries in the first area can be subjected to a complete round of overlap detection; and during a high-load period, only the entries recently added to the first area can be detected, so as to balance the processing efficiency and real-time performance.

[0086] Step C3: performing a region management operation on the candidate entry based on the second detection result, and selecting a next candidate entry from the first area until all entries in the first area are processed, to generate a fourth return result, wherein the fourth return result includes the entry processing results of the second area and the first area.

[0087] The delete command is not a simple address release, but an intelligent process that can automatically clean up and optimize the storage state. The allocated entry corresponding to the target address of the delete command directly completes the core operation requested by the user; subsequently, a candidate entry is selected from the first area and detected to actively utilize the address space newly released due to the deletion, to attempt to solve the conflict problem left over from the history; the region management operation based on the second detection result can intelligently determine whether to store back or migrate the candidate entry; and the cycle continues until the entries in the first area are processed, to ensure that the storage state is optimized to the maximum extent after each deletion, and multiple temporarily stored entries due to conflicts are successfully transferred to the second area. This process reduces the accumulation of fragments in the first area, automatically completes system maintenance, and improves the utilization of storage space and the execution efficiency of subsequent commands.

[0088] In the embodiments of the present application, the region management operation performed on the candidate entry based on the second detection result includes: if the second detection result indicates that the candidate address overlaps with any one of the pre-stored addresses in the first area or the second area, the candidate entry is stored back to the first area; or if the second detection result indicates that the candidate address does not overlap with any one of the pre-stored addresses in the first area or the second area, the candidate entry is added to the second area.

[0089] Specifically, after the target entry is successfully deleted from the second area (Array) and the overlap detection of a candidate entry in the first area (Pend) is completed (the second detection result is obtained), a specific area management operation is performed on the candidate entry according to the detection result. If the second detection result shows that the candidate address of the candidate entry overlaps with any pre-stored address in the current first area (Pend) or the second area (Array), the candidate entry is stored back to the end of the first area (Pend) (following the first-in-first-out principle). This operation is called re-storage; if the second detection result shows that there is no overlap, the candidate entry is added to the free position in the second area (Array) and a corresponding successful allocation result is generated. After completing the processing of the current candidate entry, the next candidate entry to be processed is automatically selected from the first area (Pend), and the above-mentioned detection and area management operations are repeated. This cyclic process continues until all entries in the first area (Pend) are taken out and processed. The fourth return result is finally generated, which contains a collection of all results generated after processing all entries in the first area triggered by this deletion command. These results include the location information of the entries successfully migrated to the second area and the final state of the first area (empty or non-empty), ensuring the state consistency of the system.

[0090] If a candidate address overlaps with any pre-stored address, the candidate entry is saved back to the first area, adhering to the hard constraint of non-overlapping addresses, ensuring data correctness and avoiding invalid migration operations. If there is no overlap with any pre-stored address, the candidate entry is added to the second area, transitioning the entry from pending status to officially allocated, effectively utilizing the newly freed space resources. This management strategy is the core mechanism that ensures data consistency and space efficiency throughout the system despite dynamic changes.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0092] This embodiment provides a command processing system for address management, such as Figure 3 As shown, it includes: a bus, a register list, a controller, a preset number of input interfaces and an output interface;

[0093] A bus for transmitting command entries from different central processing units and sending return results to each central processing unit;

[0094] Register list, used to dynamically configure system parameters (such as enabling / disabling specific input interfaces, setting operating modes, querying the current status of the first and second areas, etc.), and reflect changes in key signals within the system in real time, providing an interface for system monitoring and debugging;

[0095] a controller configured to obtain a command entry from an input interface, detect whether a logical block address in the command entry overlaps with pre-stored addresses in different storage areas, obtain a first detection result, and process the command entry according to the first detection result and an operation type in the command entry to obtain a return result;

[0096] Input interface, used to provide an independent command entry submission channel for each connected CPU. Each input interface has a unique number. The controller identifies the source of the command entry by the number and binds it to the corresponding output interface.

[0097] Output interface, used to provide an independent result return channel for each connected central processor, whose number matches the input interface. The controller feeds back the return result to the output interface with the same number according to the input interface of the command source;

[0098] Among them, Figure 4 As shown, the controller includes: a finite state machine, a first area and a second area;

[0099] A finite state machine, configured to schedule and control data flow and operation sequences (e.g., starting overlap detection, determining entry storage locations, triggering result return, etc.) by jumping between different states, wherein execution of the finite state machine may be triggered by a command entry from an input interface or a candidate entry retrieved from the first area;

[0100] The first area is used to store pending entries that cannot be processed immediately due to address overlap with existing entries. When subsequent conditions are met (such as eliminating overlap), the pending entries will be retrieved for inspection and processing again;

[0101] The second area is used to store allocated entries with no address overlap, provide a storage location for an add command, and provide an operation target for a delete command.

[0102] The system guarantees high throughput and low latency of concurrent access of multiple central processors through a bus; uses a hardware-implemented finite state machine for accurate scheduling, in combination with a second area to ensure high-speed storage and retrieval of non-conflicting addresses and efficient management of conflicting entries in a first area; a unique input / output interface hardware binding mechanism, in combination with real-time configuration and monitoring capabilities of the register list, fundamentally eliminates the confusion of multiple source commands and results at the hardware level; the entire system uses a highly modular hardware design, with excellent scalability, deterministic processing timing, and reliable operating efficiency, and can be integrated into a multi-core system-level chip or parallel computing system with extremely high requirements for real-time performance and consistency.

[0103] In the embodiments of the present application, the system further includes an arbitrator, as shown in Figure 5 connected between the plurality of input interfaces and the finite state machine, for receiving command requests submitted by all input interfaces and arbitrating in real time according to a preset scheduling strategy (such as a fixed priority polling strategy) to select a current command entry to be processed from a plurality of pending commands and submit it to the finite state machine for subsequent operation.

[0104] This mechanism ensures that the system can process commands in an orderly and efficient manner when multiple interfaces request concurrently, avoiding access conflicts and supporting different scheduling requirements of quality of service (such as prioritizing processing of specific interfaces or specific types of commands) through configuration. At the same time, the arbitrator can also monitor the status of each interface in real time during processing, such as automatically excluding an interface from the arbitration queue if it is abnormal or disabled, thereby enhancing the robustness of the system.

[0105] In the embodiments, an address management command processing device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware or a combination of software and hardware is also possible and contemplated.

[0106] The embodiments provide an address management command processing device, as shown in Figure 6 The device includes:

[0107] The acquisition module 61 is configured to acquire a command entry from an input interface, where the command entry carries a logical block address and an operation type.

[0108] The detection module 62 is configured to detect whether the logical block address overlaps with a pre-stored address in a different storage area to obtain a first detection result.

[0109] The processing module 63 is configured to process the command entry according to the first detection result and the operation type, obtain a return result, and output the return result to an output interface corresponding to the input interface.

[0110] Further, the detection module 62 comprises:

[0111] The sending sub-module is configured to send a state query signal to the first region, wherein the first region is a storage region for storing the to-be-processed entry.

[0112] The receiving sub-module is configured to receive a state signal returned by the first region based on the state query signal.

[0113] The triggering sub-module is configured to trigger the corresponding storage region to perform an overlap detection operation based on the logical block address, to obtain the first detection result, according to the state signal.

[0114] Further, the triggering sub-module is configured to, if the state signal is a non-empty signal, compare the logical block address with the pre-stored addresses of the to-be-processed entries in the first region one by one to obtain a first comparison result, trigger the second region to perform an address comparison operation based on the logical block address according to the first comparison result to obtain a second comparison result, and generate the first detection result based on the first comparison result and the second comparison result, wherein the second region is a storage region for storing the already-allocated entry; or, if the state signal is an empty signal, compare the logical block address with the pre-stored addresses of the already-allocated entries in the second region one by one to obtain a third comparison result, and generate the first detection result based on the third comparison result.

[0115] Further, the processing module 63 comprises a first processing sub-module, a second processing sub-module, and a third processing sub-module.

[0116] Further, the first processing sub-module is configured to, when the operation type is the check command, generate a first return result based on the first detection result, wherein the first return result comprises an overlap identifier, and the overlap identifier is used to represent whether the logical block address overlaps with the pre-stored addresses in each storage region.

[0117] Further, the second processing sub-module is configured to, when the operation type is the add command, if the first detection result is that the logical block address overlaps with any one of the pre-stored addresses in different storage regions, add the command entry to the first region, and generate a second return result, wherein the second return result comprises the overlap identifier; or, if the first detection result is that the logical block address does not overlap with the pre-stored addresses in different storage regions, add the command entry to the second region, and generate a third return result, wherein the third return result comprises the overlap identifier and position information of the command entry in the second region.

[0118] Further, the third processing submodule is configured to, when the operation type is a delete command, process the command entry according to the first detection result and the operation type, and obtain a return result.

[0119] Further, the third processing submodule comprises:

[0120] The determining unit is configured to determine a target address in the second region that overlaps the logical block address according to the first detection result, and delete an allocated entry corresponding to the target address from the second region;

[0121] The selecting unit is configured to select a candidate entry from the to-be-processed entries in the first region, and detect whether a candidate address of the candidate entry overlaps a pre-stored address in the storage region, to obtain a second detection result;

[0122] The generating unit is configured to perform a region management operation on the candidate entry based on the second detection result, and select a next candidate entry from the first region until all the entries in the first region are processed, and generate a fourth return result, wherein the fourth return result comprises entry processing results of the second region and the first region.

[0123] Further, the generating unit is configured to, if the second detection result is that the candidate address overlaps any one of the pre-stored addresses in the first region or the second region, store the candidate entry back to the first region; or, if the second detection result is that the candidate address does not overlap any one of the pre-stored addresses in the first region or the second region, add the candidate entry to the second region.

[0124] Please refer to Figure 7 , Figure 7 is a structural schematic diagram of a computer device provided by an optional embodiment of the present application, as shown in Figure 7 the computer device comprises one or more processors 10, a memory 20, and an interface for connecting various components, including a high-speed interface and a low-speed interface. Various components are communicatively connected with each other by using different buses, and can be installed on a common mainboard or in other manners as needed. The processor can process instructions executed in the computer device, including instructions stored in the memory or graphics information of the memory to display a GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple storage devices. Similarly, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system).

[0125] The processor 10 can be a central processing unit, a network processing unit, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a generic array logic, or any combination thereof.

[0126] The memory 20 stores instructions executable by the at least one processor 10 for causing the at least one processor 10 to perform the methods illustrated in the above embodiments.

[0127] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and applications required by at least one function. The data storage area can store data created by the use of the computer device according to the presentation of a small program landing page, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some optional embodiments, the memory 20 can optionally include a memory disposed remotely relative to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0128] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0129] The computer device further includes a communication interface 30 for communication of the computer device with other devices or communication networks.

[0130] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer codes stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer codes, when the software or computer codes are accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0131] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A command processing method for address management, characterized in that: include: Acquire a command entry from an input interface, wherein the command entry carries a logical block address and an operation type; detecting whether the logical block address overlaps with pre-stored addresses in different storage areas to obtain a first detection result; The command entry is processed according to the first detection result and the operation type to obtain a return result, and the return result is output to an output interface corresponding to the input interface.

2. The method according to claim 1, characterized in that The detecting whether the logical block address overlaps with pre-stored addresses in different storage areas to obtain a first detection result includes: Sending a status query signal to a first area, wherein the first area is a storage area for storing items to be processed; receiving a status signal returned by the first area based on the status query signal; The corresponding storage area is triggered according to the state signal to perform an overlap detection operation based on the logic block address to obtain a first detection result.

3. The method according to claim 2, characterized in that The triggering, according to the state signal, of the corresponding storage area to perform an overlap detection operation based on the logic block address to obtain a first detection result includes: If the status signal is a non-empty signal, the logical block address is compared one by one with pre-stored addresses of entries to be processed in the first area to obtain a first comparison result, the second area is triggered to perform an address comparison operation based on the logical block address according to the first comparison result to obtain a second comparison result, and a first detection result is generated based on the first comparison result and the second comparison result, wherein the second area is a storage area for storing allocated entries; Alternatively, if the state signal is a null signal, the logical block address is compared one by one with pre-stored addresses of allocated entries in the second area to obtain a third comparison result, and the first detection result is generated based on the third comparison result.

4. The method according to claim 1, wherein When the operation type is a check command, processing the command entry according to the first detection result and the operation type to obtain a return result includes: A first return result is generated based on the first detection result, wherein the first return result includes an overlap flag, and the overlap flag is used to indicate whether the logical block address overlaps with pre-stored addresses in each storage area.

5. The method according to claim 1, wherein When the operation type is adding a command, processing the command entry according to the first detection result and the operation type to obtain a return result includes: If the first detection result is that the logical block address overlaps with any pre-stored address in different storage areas, adding the command entry to the first area and generating a second return result, wherein the second return result includes an overlap flag; Alternatively, if the first detection result is that there is no overlap between the logical block address and the pre-stored addresses in different storage areas, the command entry is added to the second area to generate a third return result, wherein the third return result includes an overlap identifier and location information of the command entry in the second area.

6. The method according to claim 1, characterized in that When the operation type is a delete command, processing the command entry according to the first detection result and the operation type to obtain a return result includes: determining a target address in the second area that overlaps with the logical block address according to the first detection result, and deleting an allocated entry corresponding to the target address from the second area; Selecting a candidate entry from the entries to be processed in the first area, and detecting whether a candidate address of the candidate entry overlaps with a pre-stored address in the storage area, to obtain a second detection result; Based on the second detection result, a region management operation is performed on the candidate entry, and the next candidate entry is selected from the first region until all entries in the first region are processed, and a fourth return result is generated, wherein the fourth return result includes entry processing results of the second region and the first region.

7. The method according to claim 6, characterized in that The performing the area management operation on the candidate entry based on the second detection result includes: If the second detection result is that the candidate address overlaps with any pre-stored address in the first area or the second area, storing the candidate entry back into the first area; Alternatively, if the second detection result is that the candidate address does not overlap with any pre-stored address in the first area or the second area, the candidate entry is added to the second area.

8. A command processing device for address management, characterized in that: include: An acquisition module, configured to acquire a command entry from an input interface, wherein the command entry carries a logical block address and an operation type; a detection module, configured to detect whether the logical block address overlaps with pre-stored addresses in different storage areas, and obtain a first detection result; A processing module is used to process the command entry according to the first detection result and the operation type to obtain a return result, and output the return result to an output interface corresponding to the input interface.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 7 when executed by a processor.

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