Indirect memory access using shared pointers

Abstract

The invention relates to indirect memory access using a shared pointer. Systems and techniques for indirectly accessing an object in a memory are described herein. A memory allocation request for an object is received, the memory allocation request specifying use of a shared pointer. A memory address to fulfill this allocation is identified and a pointer to this address is written into a shared memory location accessible by both the host and the memory device. When the host requests the object, the host references the pointer to fetch the memory address of the requested object. The memory device can then return requested data.

Description

TECHNICAL FIELD

[0001] Embodiments described herein generally relate to memory control in computing devices, and more specifically, to indirect memory access using shared pointers. BACKGROUND

[0002] Memory address translation in a typical computer is a technique that involves converting a virtual memory address (e.g., generated by a processor instruction) to a physical address in the main (e.g., working) memory (e.g., random access memory (RAM)) of the computer. Memory address translation enables efficient memory management or process isolation in modern operating systems. Typically, a central processing unit (CPU) executes a program using virtual addresses, which are then translated to actual physical memory addresses by a system called a memory management unit (MMU). The MMU uses a data structure, such as a page table, maintained by the operating system to map virtual addresses to physical addresses. Typically, each entry in the page table corresponds to a block of memory, called a page. The translation involves locating the page table entry that corresponds to the virtual address, and then combining the physical address base from this entry with the offset of the virtual address to form the complete physical address. This mechanism allows features such as virtual memory (where portions of a program can be stored on disk when not in use) and memory protection, ensuring that one process cannot access another process's memory.

[0003] Cache coherency generally ensures consistency of data stored in local caches of different CPUs, cores, or other devices (e.g., memory devices, co-processors, etc.) of a computing system. When multiple devices access and modify shared data, there is a risk of having different, inconsistent copies of the data in the caches of these devices, leading to errors and inconsistencies in program execution. Cache coherency protocols (e.g., the MESI (Modified, Exclusive, Shared, Invalid) protocol) can be employed to address the consistency issue among caches of shared data. These protocols aim to ensure that any changes made to data in one cache are immediately reflected in other caches, or that other caches are invalidated or updated accordingly. This is typically achieved through communication and coordination among caches, where a cache sends signals or messages to other caches (e.g., or devices) to notify of read or write operations. If a cache modifies data, the protocol propagates this change to other caches by updating or marking the copies at other caches as invalid, ensuring that all caches have a consistent view of the data. SUMMARY

[0004] According to an aspect of the disclosure, an apparatus for indirect memory access using shared object pointers is provided. The apparatus comprises an interface to a memory device; and processing circuitry, when in operation, configured to: receive a request for a memory allocation for an object, the request specifying use of the shared pointer; identify a memory address, the memory address being a portion of memory accessible via the interface to fulfill the memory allocation; write a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; receive a request for the object from the host, the request including the memory address read by the host from the pointer; and based on the request from the host, return data at the memory to be retrieved via the interface to fulfill the memory allocation.

[0005] According to another aspect of the disclosure, a method for indirect memory access using shared object pointers is provided. The method comprises: receiving, at a memory device, a request for a memory allocation for an object, the request specifying use of the shared pointer; identifying a memory address, the memory address being a portion of memory to fulfill the memory allocation; writing a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; receiving a request for the object from the host, the request including the memory address read by the host from the pointer; and based on the request from the host, returning data at the memory to fulfill the memory allocation.

[0006] According to yet another aspect of the disclosure, a machine readable medium is provided. The machine readable medium includes instructions that, when executed by processing circuitry, cause the processing circuitry to perform the above-described method.

[0007] According to a further another aspect of the disclosure, a system is provided. The system comprises means to perform the above-described method. BRIEF DESCRIPTION OF DRAWINGS

[0008] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein.

[0009] Figure 1 is a block diagram of an example of an environment including a system for indirect memory access using shared pointers according to embodiments.

[0010] Figure 2Examples of arrangements of shared memory, memory devices, and host devices according to embodiments are illustrated.

[0011] Figure 3 Examples of hosts connected to CXL devices according to embodiments are illustrated.

[0012] Figure 4 A flowchart illustrating examples of methods for indirect memory access using shared pointers according to embodiments is illustrated.

[0013] Figure 5 is a block diagram of an example of a machine in which one or more embodiments can be implemented. DETAILED DESCRIPTION

[0014] In typical computing systems using virtual memory, address translation and data mapping overhead tends to increase as system memory capacity increases. Operating system (OS) page tables traditionally maintain mappings of user applications to physical memory. These page tables are protected from unauthorized changes and thus updates typically involve a privileged execution mode switch (e.g., changing from a non-privileged execution mode to a privileged execution mode) to perform computationally expensive page table manipulations. Typically, these manipulations are limited to relatively coarse-grained (e.g., large data segments) aspects of memory, for example at a page size of four kilobytes. Thus, traditional virtual memory approaches tend to be computationally expensive, rely on host processor intervention, and result in coarse-grained changes to memory mappings.

[0015] To address these issues, indirect memory access using shared pointers can be used. Here, a user program accesses memory via a pointer to enable a degree of indirection in memory access. This enables another device (e.g., a CXL memory device) to move data to a new memory location and update the pointer to enable the user program to continue accessing the data. In examples, the pointer is involved in cache coherency arrangements with a host processor. Here, mechanisms present in, for example, the CXL standard, provide for changes to the pointer to be reflected on various devices participating in cache coherency. Thus, for example, when a memory device updates the pointer locally, the host processor is notified of the change since the pointer is maintained in a region shared via cache coherency mechanisms.

[0016] Compared to traditional virtual memory techniques, the indirect memory access described herein has several advantages. For example, the techniques are lightweight, involving less hardware and processing by the host system than is typical in virtual memory techniques. By having pointers point to variable-sized data segments, indirect memory access also enables more fine-grained changes. In this example, an array of pointers can represent a portion of user program data and any of these pointers can be updated to reflect data movement. With respect to host flexibility, this indirect memory access can provide a shared array of memory object locks and pointers between a host processor and a memory device in user space. Address space segments (e.g., covering multiple memory levels) can be provided to an application to represent a contiguous virtual address space. Here, a host or memory device can allocate or remap objects in the virtual address space by modifying the shared pointers. When the memory device includes atomic operators, the memory device can use atomic memory operations to ensure consistency of updates to shared object pointers.

[0017] Data tiering and level management is a motivation for enabling a memory device to control data movement. In data tiering, data can move to different storage media depending on various factors. For example, if data is small, frequently accessed, and low latency is important, the data can be stored in static random access memory (SRAM). In contrast, if data is large, not frequently accessed, and latency is not important, the data can be stored in NAND flash memory or magnetic tape as a cost-effective solution. With the mixed media capabilities that can be accessed by a memory device controller based on a new physical or access protocol (e.g., CXL), this memory tiering can be handled by the memory device given the indirect memory access described herein. Additional details and examples are given below.

[0018] Figure 1 is a block diagram of an example of an environment including a system 105 for indirect memory access using shared pointers according to an embodiment. The system 105 includes a first host 110 (e.g., a central processing unit (CPU)) and a second host 160 (e.g., an accelerator), and a memory system 125. The first host 110 can have a host memory 115 directly attached in the system 105. In an example, the system 105 is a server computer, a workstation, a personal laptop computer, a desktop computer, a digital camera, a smartphone, a memory card reader, an Internet of Things capable device, or the like, or a portion thereof. The first host 110 or the second host 160 can include one or more processor cores, a parallel processor system, or other CPU arrangement.

[0019] The memory system 125 includes a controller 130, a buffer 135 (e.g., internal state storage), a cache 140, and a first memory device 145. The first memory device 145 can include, for example, one or more memory modules (e.g., a single in-line memory module, a dual in-line memory module, etc.). The first memory device 145 can include volatile memory or non-volatile memory. The first memory device 145 can include a multi-chip device comprising one or more different memory types or modules. In an example, the system 105 includes a second memory device 150 that interfaces with the memory system 125 and the first host 110.

[0020] The system 105 can include a backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry), including the first host 110 and the second host 160 or in addition to the first host 110 and the second host 160. The system 105 can optionally include separate integrated circuits for the first host 110, the second host 160, the memory system 125, the controller 130, the buffer 135, the cache 140, the first memory device 145, the second memory device 150, any one or more of which can comprise respective chiplets that can be connected and used together. In an example, the system 105 includes a server system or a high-performance computing (HPC) system or a portion thereof. Embodiments of the first host 110 or other components of the system 105 can be implemented in a Von Neumann or a non-Von Neumann architecture, which can include one or more components (e.g., CPU, abstract logic unit (ALU), etc.) typically associated with a Von Neumann architecture, or can omit these components.

[0021] In an example, the first memory device 145 can provide main memory for the system 105, or the first memory device 145 can comprise an adjunct memory or storage device for use by the system 105. In an example, the first memory device 145 or the second memory device 150 includes one or more arrays of memory cells (e.g., volatile or non-volatile memory cells). For example, the arrays can be flash arrays having a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory device can include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

[0022] In embodiments in which the first memory device 145 includes persistent or non-volatile memory, the first memory device 145 can include a flash memory device, such as a NAND or NOR flash memory device. The first memory device 145 can include other non-volatile memory devices, such as non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM). Some memory devices— such as ferroelectric RAM (FeRAM) devices including ferroelectric capacitors— can exhibit hysteresis characteristics, such as 3D cross-point (3D XP) memory devices or combinations thereof.

[0023] In an example, the interface 120 or the interface 165 can include any type of communication path, bus, interconnect, or the like that enables information to be communicated between the first host 110 or the second host 160, respectively, or other devices of the system 105 and the memory system 125. Non-limiting examples of interfaces can include a peripheral component interconnect (PCI) interface, a peripheral component interconnect express (PCIe) interface, a serial advanced technology attachment (SATA) interface, a universal serial bus (USB) interface, a Thunderbolt interface, or a micro serial advanced technology attachment (mSATA) interface, among others. In an example, the interface 120 includes a PCIe 5.0 interface that is compliant with the Compute Express Link (CXL) protocol standards. Thus, in some embodiments, the interface 120 supports a transfer speed of at least 32 GT / s.

[0024] CXL is a high-speed central processing unit (CPU) to device and CPU to memory interconnect designed to enhance compute performance. CXL maintains memory coherency between CPU memory space (e.g., host memory 115 or cache maintained by first host 110) and memory on attached devices or accelerators (e.g., first memory device 145 or second memory device 150). This arrangement enables resource sharing with higher performance, reduced software stack complexity, and lower overall system cost compared to other interconnect arrangements. CXL is an industry open standard interface for high-speed communication with accelerators that are increasingly being used to supplement CPUs to support emerging data-rich and compute-intensive applications such as artificial intelligence and machine learning. Memory system 125 is illustrated with atomic processing circuitry 155 as an accelerator in order to perform near-memory operations. Generally, atomic memory operations (AMO) performed by atomic processing circuitry 155 include small operations such as incrementing a number at a memory address or multiplying numbers in two memory addresses. While AMO are typically used for such operations, manipulation of memory is not so limited. For example, modern artificial neural network architectures often involve applying small addition or multiplication operations or thresholding across a large number of artificial neurons. Because the computations are often simple, but the data is large, near-memory execution of such operations is possible and beneficial given the illustrated architecture.

[0025] In an example, controller 130 comprises a media controller, such as a non-volatile memory express (NVMe) controller. Controller 130 can be configured to perform operations such as copying, writing, reading, error correction, etc. for first memory device 145. In an example, controller 130 can include custom circuitry or instructions to perform various operations. That is, in some embodiments, controller 130 can include circuitry or can be configured to execute instructions to control movement of data or addresses associated with data, e.g., among buffer 135, cache 140, or first memory device 145 or second memory device 150.

[0026] In an example, buffer 135 comprises data buffering circuitry including a physical memory area used to temporarily store data, e.g., when moving data from one place to another. Buffer 135 can include a first-in-first-out (FIFO) queue, where oldest (e.g., first entered) data is processed first. In some embodiments, buffer 135 includes a hardware shift register, a circular buffer, or a list.

[0027] In an example, the cache 140 includes a region of physical memory used to temporarily store particular data from the first memory device 145 or the second memory device 150. Generally, the cache 140 provides faster data access than the backing memory. The cache 140 can include a pool of data entries. In an example, the cache 140 can be configured to operate according to a write-back policy in which data is written to the cache without being concurrently written to the first memory device 145. Thus, in some embodiments, data written to the cache 140 does not have a corresponding data entry in the first memory device 145. This can occur, for example, when data is written to the cache and is deleted before a write-back is triggered to write the data to the first memory device 145.

[0028] In an example, the cache 140 is implemented as a multi-way set associative cache. Here, cache entries are partitioned by some portion of the memory address, e.g., setting a number of valid bits. Groups of cache entries, referred to herein as cache sets (e.g., cache lines or ways), can be commonly associated with a same set of bits from the memory address. Generally, the number of ways in a cache set is less than the total number of memory addresses associated with the ways. Thus, ways can be evicted to be associated with new memory addresses in a range at various points.

[0029] In an example, the controller 130 can receive write requests involving the cache 140 and cause data associated with each of the write requests to be written to the cache 140. The controller 130 can similarly receive read requests and cause data stored in, e.g., the first memory device 145 or the second memory device 150, to be retrieved and written to the first host 110, e.g., via the interface 120, or the second host 160, e.g., via the interface 165. In an example, the controller 130 handles all requests for the memory it controls through the cache 140. Thus, a read request will first check the cache 140 to determine if the data has been cached. If not, a read is made to the first memory device 145 to retrieve the data. The data is then written to the cache 140. In an example, the data is then read from the cache 140 and transmitted to the requesting entity, e.g., the first host 110 or the second host 160. Working exclusively through the cache can simplify some elements of the controller 130 hardware at the cost of a little latency.

[0030] To implement indirect memory access using shared object pointers, controller 130 can be configured to receive a memory allocation request for an object. This request specifies the use of a shared pointer. Because the user program will dereference the pointer to the actual memory location, rather than simply using the actual memory location, the user program or any entity that issues the memory request is actively participating in the selection of indirect memory access over other memory access techniques. Thus, the request explicitly specifies the use of a shared pointer.

[0031] The term "object" herein denotes a data entity defined by a requestor (e.g., a user program). Thus, the object can be a structure, a value (e.g., a string, an integer, etc.), an executable block (e.g., a function, a method, etc.), an image, or another data structure. The object is not required to be aligned with a conventional memory segment value. Thus, the object need not be divisible by the conventional four kilobyte page size of other allocation techniques.

[0032] Controller 130 is configured to identify a memory address that is part of a memory (e.g., first memory device 145) to fulfill the memory allocation. Here, as part of the execution of the memory allocation request for an object, controller 130 (e.g., from first memory device 145, second memory device 150, or from a network fabric attached memory device) identifies what storage device is available and reserves that storage device to satisfy the request. The element of memory used to satisfy the request has an address that is collected by controller 130 at this stage.

[0033] In an example, the memory used to fulfill the memory allocation is tiered memory. In an example, the tiered memory includes multiple performance tiers. As noted above, tiered memory divides memory into several performance tiers. Generally, lower latency (e.g., data seek time, data access time, etc.) is achieved with higher tier memory technology. Generally, this storage media is more expensive to produce, takes up more physical area, or uses more energy to operate than other storage media. For example, SRAM is generally much faster (e.g., lower latency) than flash memory devices, but SRAM is more expensive per byte and thus is generally limited to total storage space. In this arrangement, SRAM is a higher tier than flash memory devices. As illustrated, first memory device 145 can be a higher tier than second memory device 150.

[0034] The controller 130 is configured to write a pointer to a shared memory location that points to a memory address (e.g., a memory address in an array representing an object memory allocation). The shared memory location is accessible by the first host 110 and the memory system 125. In an example, the shared memory location adheres to a cache coherency mechanism between the first host 110 and the memory system 125. In an example, the memory system 125 is attached to the host via a compute express link (CXL) interconnect (e.g., the interface 120 in an example).

[0035] In an example, the controller 130 is configured to maintain the pointer (e.g., an array of pointers) in a data structure. In an example, the data structure includes a lock for the object. An example of the structure is illustrated in Figure 2 In an example, the lock specifies which of the first host 110 or the memory system 125 can update the pointer in the data structure. In an example, the data structure includes a size of the object. This facilitates fine-grained allocation and storage movement by the controller 130.

[0036] In an example, a portion of memory used to fulfill a memory allocation is managed by a second memory device. This example occurs in the case of sharing a memory address space across several memory systems, as can occur in a global fabric attached memory (GFAM) device. In this case, the controller 130 can allocate memory in the second device using the shared address space between the two memory systems.

[0037] The controller 130 is configured to receive a request from the first host 110 for memory used to fulfill a memory allocation. This request includes a memory address read by the host from the pointer. Here, a user program running on the first host 110 has accessed the pointer to obtain a memory address for an object. The object is then requested by the address.

[0038] The controller 130 is configured to return data at the memory used to fulfill a memory allocation based on the request from the first host 110. This completes the setup and response process for indirect memory access using a shared object pointer.

[0039] A situation can arise in which requests from the first host 110 are pending at the memory system 125 when the pointer is updated. Thus, when these requests are executed, the memory address in the request no longer points to the object data. To resolve this issue, the controller 130 can update the memory address in the queued request. For example, the previous memory address can be searched for in the queued request and updated (e.g., overwritten) to the new memory address.

[0040] Thus, in an example, the controller 130 is configured to move data in the memory used to fulfill the memory allocation to a second memory - the second memory corresponding to a second memory address - and update the pointer to point to the second memory address. The controller 130 is configured to then update a set of requests for the memory address that are pending at the memory system 125 from the first memory address to the second memory address. In an example, to update the set of requests, the controller 130 is configured to rewrite the memory address to the second memory address. This in-place rewriting technique is generally feasible because the memory system 125 has the pending requests and is also performing the data move.

[0041] Other techniques can be used to address the problem when the pointer address changes. For example, to update the set of requests, the controller 130 is configured to translate the memory address to the second memory address when executing a member of the set of requests. Here, the controller 130 can version the pointer address and correspond requests to the version. Thus, if a request being executed corresponds to a previous version of the pointer, the request is fulfilled using the current version of the pointer. In an example, the requests can be queued based on objects and simply use the current pointer address of the object.

[0042] In an example, the controller 130 is configured to deny a second memory request based on receiving the second memory request from the host after data in the memory used to fulfill the memory allocation has begun to move and before updating the pointer to point to the second memory address. This example provides an alternative to address rewriting by simply denying memory requests while the data is in a state of flux. Generally, a memory request failure will trigger another attempt by the first host 110 to fetch the data, and if the move is complete, the request will be handled with the new pointer address that now points to the correct data.

[0043] Figure 2 An example of an arrangement of a shared memory 215, a memory device 210, and a host device 205 according to an embodiment is illustrated. The illustrated arrangement includes an established pointer array shared between the host device 205 and the memory device 210. The host device 205 can write to a mailbox memory region in a near-memory compute processor in a configuration register (CSR) or a memory module (NMC) of the memory device 210 to inform the memory device 210 where (e.g., how) to access the shared pointer array 220.

[0044] Pointer 225 includes a memory address of object 230 (e.g., points to object 230). Object 230 is private to memory device 210 in that object 230 is only accessible by host device 205 via pointer 225. Otherwise, the address of object 230 is not provided to host device 205 as compared to conventional virtual memory techniques. In an example, a pointer 225 in pointer array 220 can include a corresponding lock 235 (e.g., lock flag) that indicates whether host device 205 or memory device 210 is manipulating pointer 225. In an example, pointer 225 can only be changed when lock 235 has been acquired by host device 205 or memory device 210. For example, a change (e.g., an update to pointer 225) can occur after memory device 210 has relocated data of object 230 into a different memory location (e.g., a different internal storage tier or a peer memory device (e.g., via peer data replication)). In an example, lock 235 is cleared when object 230 is moved (e.g., data replication is complete).

[0045] In an example, the data structure represented by pointer array 220 can include an object size indicator field. This can enable host device 205 or memory device 210 to move object 230 as a whole. The ability to move an entire object can have several benefits, such as avoiding splitting an object that can break the continuity of the address space or break correct program execution.

[0046] To use pointer 225, host device 205, and more specifically a program executing thereon, changes behavior to use pointer 225 instead of conventional memory addressing to access object 230. Thus, a programmer, compiler, or interpreter adjusts program output to request a memory address from pointer 225 instead of managing memory offsets internally.

[0047] In the illustrated arrangement, memory device 210 is released to reprogram any object pointer that benefits from moving data in the address space (e.g., under operation testing or metrics). Because heavily used objects are relocated to higher tier media that improves system performance, while lightly used objects are moved to lower tier media that frees higher tier media for heavily used objects, this capability can improve operational efficiency of memory device 210.

[0048] Generally, any device in which data resides can move an object within the device or across devices when the device later updates a pointer. A user (e.g., host device 205, program, etc.) operates in the same manner regardless of whether data is moved, as access involves pointer 225 that points to object 230, regardless of where that object resides.

[0049] In an example, hardware or software coherency is used to ensure that the operators (e.g., host device 205 and memory device 210) see a consistent value for pointer 225. For example, the memory device 210 moving object 230 can lock pointer 225, copy the data to a new destination— aborting or buffering any writes that occur during the migration— and update pointer 225. At this point, memory device 210 will invalidate any cached copies of pointer 225 by, for example, using CXL.cache or CXL.mem invalidate-back command inherent in the protocol. Once complete, memory device 210 can release lock 235.

[0050] Figure 3 An example of a host connected to a CXL device according to an embodiment is illustrated. Figure 3 An example of a CXL system 300 is generally illustrated that uses a CXL link 306 to connect a host device 302 and a CXL device 304 via a host physical layer PCIE interface 308 and a CXL client physical layer PCIE interface 310, respectively. In an example, host device 302 comprises or corresponds to first host 110 (or second host 160), and CXL device 304 comprises or corresponds to an example of memory system 125 from system 105 in FIG. 1. In an example, CXL link 306 can support communication using a multiplexing protocol for cache (e.g., CXL.cache), memory access (e.g., CXL.mem), and data input / output transactions (e.g., CXL.io). CXL.io can include a PCIe-based protocol used for functions such as device discovery, configuration, initialization, I / O virtualization, and direct memory access (DMA) using non-coherent load-store, producer-consumer semantics. CXL.cache can enable a device to cache data from a host memory (e.g., from host memory 312) using a request and response protocol. CXL.memory can enable host device 302 to access memory of CXL device 304 using, for example, in or attached to a virtualized memory space. In an example, CXL.memory transactions can be memory load and store operations running downstream or externally to host device 302. Figure 1

[0051] In an example, a CXL memory system 125 is connected to a host device 110 (or second host 160) using a CXL link 306. In an example, CXL link 306 can support communication using a multiplexing protocol for cache (e.g., CXL.cache), memory access (e.g., CXL.mem), and data input / output transactions (e.g., CXL.io). CXL.io can include a PCIe-based protocol used for functions such as device discovery, configuration, initialization, I / O virtualization, and direct memory access (DMA) using non-coherent load-store, producer-consumer semantics. CXL.cache can enable a device to cache data from a host memory (e.g., from host memory 312) using a request and response protocol. CXL.memory can enable host device 302 to access memory of CXL device 304 using, for example, in or attached to a virtualized memory space. In an example, CXL.memory transactions can be memory load and store operations running downstream or externally to host device 302. Figure 3 ​In the example of FIG. 3, host device 302 includes host processor 314 (e.g., comprising one or more CPUs or cores) and IO device(s) 328. Host device 302 can include or can be coupled to host memory 312. Host device 302 can include various circuitry (e.g., logic) configured to facilitate CXL-based communications and transactions with CXL device 304. For example, host device 302 can include coherency and memory circuitry 318 configured to implement transactions according to CXL.cache and CXL.mem semantics, and host device 302 can include PCIe circuitry 320 configured to implement transactions according to CXL.io semantics. In an example, host device 302 can be configured to manage coherency of data cached at CXL device 304 using, for example, its coherency and memory circuitry 318.

[0052] Host device 302 can further include host multiplexer 316 configured to modulate communications via CXL link 306 (e.g., using a PCIe PHY layer). Multiplexing of protocols ensures that latency-sensitive protocols (e.g., CXL.cache and CXL.memory) have the same or similar latency as native processor-to-processor links. In an example, CXL defines upper bounds on response times for latency-sensitive protocols to help ensure that device performance is not adversely affected by variations in latency between different devices implementing coherency and memory semantics.

[0053] In an example, symmetric cache coherency protocols can be difficult to implement between host processors because different architectures can use different solutions, which in turn can compromise backward compatibility. CXL can address this issue by consolidating coherency functionality at host device 302 (e.g., using coherency and memory circuitry 318).

[0054] CXL device 304 can include an accelerator device comprising various accelerator circuitry 322. In an example, CXL device 304 can include or can be coupled to CXL device memory 326. CXL device 304 can include various circuitry configured to facilitate CXL-based communications and transactions with host device 302 using CXL link 306. For example, accelerator circuitry 322 can be configured to implement transactions according to CXL.cache, CXL.mem, and CXL.io semantics. CXL device 304 can include CXL device multiplexer 324 configured to control communications via CXL link 306. Accelerator circuitry 322 can be one or more processors that can perform one or more tasks. Accelerator circuitry 322 can be a general-purpose processor or a processor designed to accelerate one or more particular workloads. The illustrated accelerator circuitry 322 can implement the hybrid coherency mechanism described above (e.g., in FIG. 2) to manage coherency of data cached at CXL device 304. Figure 1and Figure 2 in).

[0055] Figure 4 A flowchart illustrating an example of a method 400 for indirect memory access using shared pointers according to embodiments is shown. The operations of method 400 are performed by computing hardware (e.g., computing hardware described above or below) (e.g., processing circuitry).

[0056] At operation 405, a request for a memory allocation for an object is received at a memory device. This request specifies the use of a shared pointer.

[0057] At operation 410, a memory address is identified that is a portion of memory to fulfill the memory allocation. In an example, the memory to fulfill the memory allocation is hierarchical memory that includes a plurality of performance tiers.

[0058] At operation 415, a pointer to the memory address is written into a shared memory location that is accessible by a host and the memory device. In an example, the shared memory location adheres to a cache coherency mechanism between the host and the memory device. In an example, the memory device is attached to the host via a compute express link (CXL) interconnect.

[0059] In an example, the pointer is maintained in a data structure. In an example, the data structure includes a lock for the object. In an example, the lock specifies which of the host or the memory device can update the pointer in the data structure. In an example, the data structure includes a size of the object. In an example, the portion of memory to fulfill the memory allocation is managed by a second memory device.

[0060] At operation 420, a request for the memory to fulfill the memory allocation is received from the host. This request includes the memory address read by the host from the pointer.

[0061] At operation 425, data at the memory to fulfill the memory allocation is returned based on the request from the host.

[0062] In an example, the method 400 includes an operation of moving data in the memory to fulfill the memory allocation to a second memory— and the second memory corresponds to a second memory address— and updating the pointer to point to the second memory address. In an example, the operation also includes updating a set of requests for the memory address that are pending at the memory device to the second memory address. In an example, updating the set of requests includes overwriting the memory address with the second memory address. In an example, updating the set of requests includes translating the memory address to the second memory address when a member of the set of requests is executed.

[0063] In an example, the operations of the method 400 include, after data in the memory to fulfill the memory allocation has begun to move and before the pointer is updated to point to the second memory address, denying the second memory request based on receiving the second memory request from the host.

[0064] Figure 5 A block diagram illustrating an example machine 500 is shown, upon which any one or more of the techniques (e.g., methodologies) discussed herein can perform. As discussed herein, examples can include, or can operate on, logic or a number of components, or mechanisms in machine 500. Circuitry (e.g., processing circuitry) is a collection of circuits implemented in tangible entities that include hardware (e.g., simple circuits, gates, logic, etc.). Circuitry membership can change over time. Circuitry includes all members of a team of circuits (e.g., a group of circuits) that can cause an entity to perform a specified operation, either alone or in combination with other entities. In an example, hardware of the circuitry can be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuitry can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a machine-readable medium physically modified (e.g., magnetically, electrically, by nonvolatile material, etc.) to create configuration information that can be interpreted by circuitry (e.g., instruction execution units) to cause the physical components to carry out an operation in accordance with the configuration information. In an example, components can be

[0065] In alternative embodiments, the machine 500 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine 500 can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine 500 can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine 500 can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be interpreted to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as a cloud computing, software as a service (SaaS), other computer cluster configurations.

[0066] The machine (e.g., computer system) 500 can include a hardware processor 502 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 504, a static memory (e.g., memory or storage for firmware, microcode, a basic-input- output (BIOS), unified extensible firmware interface (UEFI) etc.) 506, and mass storage 508, some or all of which can communicate with one another via an interlink (e.g., bus) 530. The machine 500 can further include a display unit 510, an alphanumeric input device 512 (e.g., a keyboard), and a user interface (UI) navigation device 514 (e.g., a mouse). In an example, the display unit 510, input device 512 and UI navigation device 514 can be a touch screen display. The machine 500 can additionally include a storage device (e.g., drive unit) 508, a signal generation device 518 (e.g., a speaker), a network interface device 520, and one or more sensors 516, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine 500 can include an output controller 528, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0067] The registers of the processor 502, the main memory 504, a static memory 506, or the mass storage 508 can be, or include, machine -readable media 522 upon which are stored, or by which are stored, one or more sets of data structure or instructions 524 (e.g., software) embodying any one or more of the techniques or functions described herein, or utilized by any one or more of the techniques or functions described herein. The instructions 524 can also reside completely, or at least partially, within any one or all of the registers of the processor 502, the main memory 504, the static memory 506, or the mass storage 508 during execution thereof by the machine 500. In an example, one or any combination of the hardware processor 502, the main memory 504, the static memory 506, or the mass storage 508 can constitute machine -readable media 522. Although the machine -readable media 522 is illustrated as a single medium, the term "machine -readable media" can include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store the one or more instructions 524.

[0068] The term "machine -readable media" can include any media capable of storing, encoding, or carrying instructions for execution by the machine 500 and that cause the machine 500 to perform any one or more of the techniques of the present disclosure, or that make the instructions available for execution by the machine 500. Non-limiting machine -readable media examples can include solid-state memories, optical media, magnetic media, and signals (e.g., radio frequency signals, other optical signals, audio signals, etc.). In an example, the non-transitory machine -readable media includes a machine -readable medium that has a plurality of particles that collectively include an intrinsic property that remains (e.g., does not change) over time, and thus is not a transitory propagating signal. Thus, a non-transitory machine -readable medium is a machine -readable medium that is not a transitory propagating signal. Specific examples of non-transitory machine -readable media can include nonvolatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0069] In examples, the information stored or otherwise provided on the machine- readable medium 522 can be representative of the instructions 524, e.g., in a format that is the instructions 524 themselves or from which the instructions 524 can be derived. Such a format from which the instructions 524 can be derived can include source code, encoded instructions (e.g., in a compressed or encrypted form), packaged instructions (e.g., into multiple packages), or the like. The information representative of the instructions 524 in the machine-readable medium 522 can be processed by the processing circuitry into the instructions to implement any of the operations discussed herein. For example, deriving the instructions 524 from the information (e.g., processing by the processing circuitry) can include compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, decrypting, packaging, unpackaging, or otherwise manipulating the information into the instructions 524.

[0070] In examples, the derivation of the instructions 524 can include assembling, compiling, or interpreting the information (e.g., by the processing circuitry) to create the instructions 524 from some intermediate or preprocessed format provided by the machine-readable medium 522. The information, when provided in multiple parts, can be combined, unpacked, and modified to create the instructions 524. For example, the information can be multiple compressed source code packages (or object code, or binary executable code, etc.) on one or several remote servers. The source code packages can be encrypted when transmitted over a network, and if necessary decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted (e.g., into a library, standalone executable, etc.) at a local machine, and executed by the local machine.

[0071] The instructions 524 can be further transmitted or received using a transmission medium via the network interface device 520 employing any of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), LoRa / LoRaWAN or satellite communication networks, mobile telephone networks (e.g., a cellular network, such as a 3G, 4G LTE / LTE-A, or 5G standard-based network), plain old telephone (POTS) networks, and wireless data networks (e.g., In examples, network interface device 520 can include one or more physical jacks (for example, Ethernet, coaxial, or phone jacks) or one or more antennas to connect to communication network 526. In examples, network interface device 520 can include a plurality of antennas to wirelessly communicate using at least one of Single-Input Multiple-Output (SIMO), Multiple-Input Multiple-Output (MIMO), or Multiple-Input Single-Output (MISO) techniques. The term“transmission medium” shall be interpreted to include any intangible medium that is capable of storing, encoding or carrying the instructions for execution by the machine 500, and includes digital or analog communications signals or other intangible media to facilitate communication of such software. The transmission medium is a machine-readable medium.

[0072] Additional notes and examples

[0073] Example 1 is an apparatus for indirect memory access using a shared object pointer, the apparatus comprising: an interface to a memory device; and processing circuitry, when in operation, configured to: receive a request for a memory allocation for an object, the request specifying use of the shared pointer; identify a memory address, the memory address being a portion of memory accessible via the interface to fulfill the memory allocation; write a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; receive a request for the object from the host, the request including a memory address read by the host from the pointer; and based on the request from the host, return data at the memory to fulfill the memory allocation retrieved via the interface.

[0074] In Example 2, the subject matter of Example 1, wherein the processing circuitry is configured to: move data in the memory to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and update the pointer to point to the second memory address.

[0075] In Example 3, the subject matter of Example 2, wherein the processing circuitry is configured to update a set of requests for the memory address pending at the memory device to the second memory address.

[0076] In Example 4, the subject matter of Example 3, wherein to update the set of requests, the processing circuitry is configured to overwrite the memory address with the second memory address.

[0077] In example 5, the subject matter of any one of examples 3-4, wherein to update the set of requests, the processing circuitry is configured to translate the memory address to the second memory address when a member of the set of requests is executed.

[0078] In example 6, the subject matter of any one of examples 2-5, wherein the processing circuitry is configured to deny a second memory request based on receiving the second memory request from the host after the data in the memory used to fulfill the memory allocation has begun to move and before updating the pointer to point to the second memory address.

[0079] In example 7, the subject matter of any one of examples 1-6, wherein the shared memory location adheres to a cache coherency mechanism between the host and the memory device.

[0080] In example 8, the subject matter of example 7, wherein the memory device is attached to the host via a compute express link (CXL) interconnect.

[0081] In example 9, the subject matter of any one of examples 1-8, wherein the memory used to fulfill the memory allocation is a tiered memory that includes a plurality of performance tiers.

[0082] In example 10, the subject matter of any one of examples 1-9, wherein the pointer is maintained in a data structure that includes a lock for the object that specifies which of the host or the memory device can update the pointer in the data structure.

[0083] In example 11, the subject matter of example 10, wherein the data structure includes a size of the object.

[0084] In example 12, the subject matter of any one of examples 1-11, wherein a portion of the memory used to fulfill the memory allocation is managed by a second memory device.

[0085] Example 13 is a method for indirect memory access using a shared object pointer, the method comprising: receiving, at a memory device, a request for a memory allocation for an object, the request specifying use of the shared pointer; identifying a memory address, the memory address being a portion of memory to fulfill the memory allocation; writing a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; receiving a request for the object from the host, the request including the memory address read by the host from the pointer; and based on the request from the host, returning data at the memory to fulfill the memory allocation.

[0086] In Example 14, the subject matter of Example 13 includes: moving data in the memory to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and updating the pointer to point to the second memory address.

[0087] In Example 15, the subject matter of Example 14 includes updating a set of requests pending at the memory device for the memory address to the second memory address.

[0088] In Example 16, the subject matter of Example 15, wherein updating the set of requests includes overwriting the memory address with the second memory address.

[0089] In Example 17, the subject matter of any one of Examples 15-16, wherein updating the set of requests includes translating the memory address to the second memory address when a member of the set of requests is executed.

[0090] In Example 18, the subject matter of any one of Examples 14-17 includes, after the data in the memory to fulfill the memory allocation has begun to move and before the pointer is updated to point to the second memory address, denying a second memory request based on receiving the second memory request from the host.

[0091] In Example 19, the subject matter of any one of Examples 13-18, wherein the shared memory location adheres to a cache coherency mechanism between the host and the memory device.

[0092] In Example 20, the subject matter of Example 19, wherein the memory device is connected to the host via a compute express link (CXL) interconnect.

[0093] In Example 21, the subject matter of any one of Examples 13-20, wherein the memory used to fulfill the memory allocation is tiered memory, the tiered memory including a plurality of performance tiers.

[0094] In Example 22, the subject matter of any one of Examples 13-21, wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure.

[0095] In Example 23, the subject matter of Example 22, wherein the data structure includes a size of the object.

[0096] In Example 24, the subject matter of any one of Examples 13-23, wherein a portion of the memory used to fulfill the memory allocation is managed by a second memory device.

[0097] Example 25 is a machine -readable medium including instructions for using an indirect memory access using a shared object pointer, the instructions, when executed by processing circuitry, cause the processing circuitry to perform operations comprising: receiving, at a memory device, a request for a memory allocation for an object, the request specifying use of the shared pointer; identifying a memory address, the memory address being a portion of memory used to fulfill the memory allocation; writing a pointer to the memory address into a shared memory location, the shared memory location being accessible by a host and the memory device; receiving, from the host, a request for the object, the request including the memory address read by the host from the pointer; and based on the request from the host, returning data at the memory used to fulfill the memory allocation.

[0098] In Example 26, the subject matter of Example 25, wherein the operations comprise: moving data in the memory used to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and updating the pointer to point to the second memory address.

[0099] In Example 27, the subject matter of Example 26, wherein the operations comprise updating a set of requests for the memory address that are pending at the memory device to the second memory address.

[0100] In Example 28, the subject matter of Example 27, wherein updating the set of requests includes overwriting the memory address with the second memory address.

[0101] In example 29, the subject matter of any of examples 27-28, wherein updating the set of requests includes translating the memory address to the second memory address when executing a member of the set of requests.

[0102] In Example 30, the subject matter of any of Examples 26-29, wherein the operation comprises denying a second memory request based on receiving a second memory request from the host after the data in the memory used to fulfill the memory allocation has begun to move and before the pointer is updated to point to the second memory address.

[0103] In example 31, the subject matter of any of examples 25-30, wherein the shared memory location adheres to a cache coherency mechanism between the host and the memory device.

[0104] In Example 32, the subject matter of Example 31, wherein the memory device is connected to the host via a Compute Express Link (CXL) interconnect.

[0105] In example 33, the subject matter of any of examples 25-32, wherein the memory used to fulfill the memory allocation is a tiered memory comprising a plurality of performance tiers.

[0106] In Example 34, the subject matter of any of Examples 25-33, wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure.

[0107] In Example 35, the subject matter of Example 34, wherein the data structure includes the size of the object.

[0108] In Example 36, the subject matter of any of Examples 25 to 35, wherein a portion of the memory used to fulfill the memory allocation is managed by a second memory device.

[0109] Example 37 is a system for indirect memory access using a shared object pointer, the system comprising: means for receiving, at a memory device, a request for a memory allocation for an object, the request specifying use of the shared pointer; means for identifying a memory address that is a portion of memory to fulfill the memory allocation; means for writing a pointer to the memory address into a shared memory location, the shared memory location accessible by a host and the memory device; means for receiving, from the host, a request for the object, the request including the memory address read by the host from the pointer; and means for returning, based on the request from the host, data at the memory to fulfill the memory allocation.

[0110] In Example 38, the subject matter of Example 37 includes: means for moving data in the memory to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and means for updating the pointer to point to the second memory address.

[0111] In Example 39, the subject matter of Example 38 includes means for updating a set of requests pending at the memory device for the memory address to the second memory address.

[0112] In Example 40, the subject matter of Example 39, wherein the means for updating the set of requests includes means for overwriting the memory address with the second memory address.

[0113] In Example 41, the subject matter of any one of Examples 39-40, wherein the means for updating the set of requests includes means for translating the memory address to the second memory address when a member of the set of requests is executed.

[0114] In Example 42, the subject matter of any one of Examples 38-41 includes means for, after the data in the memory to fulfill the memory allocation has begun to move and before the pointer is updated to point to the second memory address, denying a second memory request based on receiving the second memory request from the host.

[0115] In Example 43, the subject matter of any one of Examples 37-42, wherein the shared memory location adheres to a cache coherency mechanism between the host and the memory device.

[0116] In Example 44, the subject matter of Example 43, wherein the memory device is connected to the host via a compute express link (CXL) interconnect.

[0117] In Example 45, the subject matter of any one of Examples 37-44, wherein the memory used to fulfill the memory allocation is tiered memory, the tiered memory including a plurality of performance tiers.

[0118] In Example 46, the subject matter of any one of Examples 37-45, wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure.

[0119] In Example 47, the subject matter of Example 46, wherein the data structure includes a size of the object.

[0120] In Example 48, the subject matter of any one of Examples 37-47, wherein a portion of the memory used to fulfill the memory allocation is managed by a second memory device.

[0121] Example 49 is at least one machine -readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-48.

[0122] Example 50 is an apparatus comprising means to implement any of Examples 1-48.

[0123] Example 51 is a system to implement any of Examples 1-48.

[0124] Example 52 is a method to implement any of Examples 1-48.

[0125] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the examples can be practiced. These embodiments are also referred to as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more such examples taken with one or more aspects from a

[0126] All publications, patents and patent documents cited in this document are incorporated by reference herein in their entirety for the purposes of all that is described in the documents. In the event of an inconsistency between the present document and those documents incorporated by reference, the use in the incorporated reference(s) shall be deemed to be supplementary to that in the present document; in the case of irreconcilable inconsistencies, the use in the present document prevails.

[0127] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0128] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments will be readily ascertainable by those of ordinary skill in the art upon reviewing the foregoing description. The Abstract is provided to allow a quick access to the essence of the subject disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims. Also, in the above Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as intending that the disclosed features are necessarily related, or that the described implementation necessarily makes any or all of the disclosed features mandatory in any claims. Rather, the inventive subject matter can lie in fewer than all features of a particular disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim acting as a separate embodiment of the inventive subject matter. The scope of the embodiments should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An apparatus for indirect memory access using a shared object pointer, the apparatus comprising: an interface with a memory device; and A processing circuit system, which, when in operation, is configured to: receiving a request for memory allocation for an object, the request specifying use of the shared pointer; identifying a memory address, the memory address being a portion of memory accessible via the interface used to fulfill the memory allocation; writing a pointer to the memory address into a shared memory location, the shared memory location being accessible to a host and the memory device; receiving a request for the object from the host, the request including the memory address read by the host from the pointer; and Based on the request from the host, data retrieved via the interface at the memory used to fulfill the memory allocation is returned.

2. The apparatus of claim 1 , wherein the processing circuitry is configured to: moving data in the memory used to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and The pointer is updated to point to the second memory address.

3. The apparatus of claim 2, wherein the processing circuitry is configured to update a set of requests for the memory address pending at the memory device to the second memory address. 4 . The apparatus of claim 3 , wherein to update the set of requests, the processing circuitry is configured to rewrite the memory address to the second memory address.

5. The apparatus of claim 3, wherein to update the set of requests, the processing circuitry is configured to translate the memory address to the second memory address when executing a member of the set of requests.

6. The apparatus of claim 2 , wherein the processing circuitry is configured to deny a second memory request based on receipt of a second memory request from the host after the data in the memory used to fulfill the memory allocation has begun to be moved and before the pointer is updated to point to the second memory address.

7. The apparatus of claim 1, wherein the shared memory location adheres to a cache coherence mechanism between the host and the memory device.

8. The apparatus of claim 7, wherein the memory device is attached to the host via a Compute Express Link (CXL) interconnect.

9. The apparatus of claim 1, wherein the memory used to perform the memory allocation is a hierarchical memory comprising a plurality of performance tiers.

10. The apparatus of claim 1, wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure. The apparatus of claim 10 , wherein the data structure comprises a size of the object.

12. A method for indirect memory access using a shared object pointer, the method comprising: receiving, at a memory device, a request for memory allocation for an object, the request specifying use of the shared pointer; identifying a memory address, the memory address being a portion of memory used to fulfill the memory allocation; writing a pointer to the memory address into a shared memory location, the shared memory location being accessible to a host and the memory device; receiving a request for the object from the host, the request including the memory address read by the host from the pointer; and Based on the request from the host, data at the memory used to fulfill the memory allocation is returned.

13. The method according to claim 12, comprising: moving data in the memory used to fulfill the memory allocation to a second memory, the second memory corresponding to a second memory address; and The pointer is updated to point to the second memory address.

14. The method of claim 13, comprising updating a set of requests for the memory address pending at the memory device to the second memory address.

15. The method of claim 14, wherein updating the set of requests comprises rewriting the memory address to the second memory address.

16. The method of claim 14, wherein updating the set of requests comprises translating the memory address to the second memory address when executing a member of the set of requests.

17. The method of claim 13, comprising denying a second memory request based on receipt of a second memory request from the host after the data in the memory used to fulfill the memory allocation has begun to move and before updating the pointer to point to the second memory address.

18. The method of claim 12, wherein the shared memory location adheres to a cache coherence mechanism between the host and the memory device.

19. The method of claim 18, wherein the memory device is connected to the host via a Compute Express Link (CXL) interconnect.

20. The method of claim 12, wherein the memory used to perform the memory allocation is a hierarchical memory comprising a plurality of performance tiers.

21. The method of claim 12, wherein the pointer is maintained in a data structure, the data structure including a lock for the object, the lock specifying which of the host or the memory device can update the pointer in the data structure.

22. The method of claim 21, wherein the data structure comprises a size of the object.

23. The method of claim 12, wherein a portion of the memory used to fulfill the memory allocation is managed by a second memory device.

24. A machine-readable medium comprising instructions which, when executed by processing circuitry, cause the processing circuitry to perform any of the methods of claims 12 to 23.

25. A system comprising means for performing any of the methods of claims 12 to 23.

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