Memory aging test method and device, equipment, storage medium and program product

Abstract

The invention relates to the field of artificial intelligence chips, and provides a memory aging test method, device and equipment, a storage medium and a program product.The method comprises the steps that according to the number of kernels of a processor to be tested, the memory space of the processor is divided into a plurality of memory address blocks to be distributed to the kernels of the processor; performing permutation and combination on the plurality of memory test algorithms to generate a plurality of first algorithm sequences; issuing the first algorithm sequence to a processor core by adopting a rotary full distribution mechanism; and each kernel runs the issued first algorithm sequence based on the allocated memory address block, and executes the aging test task. By permutation and combination of the memory test algorithms and issuing of the memory test algorithms to the kernels for operation and execution of the aging test task by adopting a rotation type full distribution mechanism, it can be ensured that memory address blocks of different kernels operate different algorithms at the same moment, the complexity of a memory operation scene is improved, and the efficiency is improved. And the test result can effectively guide the screening and quality control of the memory bank.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence chips, and in particular to a memory aging test method, apparatus, device, storage medium, and program product. Background Technology

[0002] IT technology is a crucial engine driving the development of various industries. With the rapid development of emerging technologies such as cloud computing, big data, and artificial intelligence, the demand for data storage and computing has surged, making the stable operation of servers paramount. Memory, as a key component of a server, directly impacts its overall performance and stability. To reduce memory failure rates, memory aging tests are typically performed to help memory quickly overcome early failure stages. Aging tests shorten the testing cycle and rapidly identify memory modules with high failure rates by setting acceleration factors, such as increasing environmental conditions like temperature and humidity.

[0003] Currently, existing memory aging test methods are limited by their single testing algorithms or methods, making it impossible to simulate the actual operation of memory in real-world applications. As a result, the aging test results cannot accurately reflect the performance of memory modules in actual applications, and cannot effectively guide the selection and quality control of memory modules. Summary of the Invention

[0004] This application provides a memory aging test method, apparatus, device, storage medium, and program product to solve the defects of existing memory aging test methods, which are limited by the single test method and cannot simulate the real operation of memory in actual applications, resulting in test results that cannot effectively guide the selection and quality control of memory modules.

[0005] This application provides a memory aging test method, including: According to the number of cores of the processor to be tested, the memory space of the processor is divided into multiple memory address blocks and allocated to the cores of the processor; Multiple memory testing algorithms are combined and arranged to generate multiple first algorithm sequences; A round-robin full distribution mechanism is adopted to distribute the first algorithm sequence to each kernel; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0006] In one embodiment, the step of arranging and combining multiple memory testing algorithms to generate multiple first algorithm sequences includes: Multiple memory testing algorithms are categorized according to their algorithm types to obtain an algorithm array corresponding to each algorithm type; the algorithm types include data transformation type, address transformation type, and data-address combination transformation type. Memory testing algorithms are selected from the algorithm array to form an algorithm combination; the algorithm combination contains at least one memory testing algorithm from the algorithm array. The memory testing algorithms in the algorithm combination are arranged in different orders to obtain multiple first algorithm sequences.

[0007] In one embodiment, the adoption of a round-robin full distribution mechanism to distribute the first algorithm sequence to the kernel includes: Based on the number of kernels, select target algorithm sequences from the first algorithm sequence to form an algorithm sequence array; The target algorithm sequences in the algorithm sequence array are arranged in different orders to obtain multiple second algorithm sequences; each second algorithm sequence contains at least one target algorithm sequence. Assign the second algorithm sequence to the kernel; A round-robin full distribution mechanism is adopted. If the second algorithm sequence allocated to the kernel is not empty, a target algorithm sequence is selected sequentially from the second algorithm sequence allocated to the kernel and distributed to the kernel. If the second algorithm sequence is empty, return to and execute the step of selecting a target algorithm sequence from the first algorithm sequence to form an algorithm sequence array based on the number of kernels, until the test termination condition is met; the test termination condition includes the kernel's test rounds reaching a preset number of rounds, or the kernel's test duration reaching a preset duration.

[0008] In one embodiment, dividing the processor's memory space into multiple memory address blocks and allocating them to the processor's cores according to the number of cores of the processor under test includes: The memory space partitioning parameters of the processor are determined based on the number of cores of the processor to be tested; the partitioning parameters include block size and number of blocks. The memory space is divided into multiple memory address blocks based on the partitioning parameters; The plurality of memory address blocks are allocated to the processor's kernel.

[0009] In one embodiment, the number of memory address blocks is an integer multiple of the number of kernels, the memory address blocks are evenly distributed among the kernels, and the number of memory address blocks allocated to each kernel is greater than or equal to a preset value.

[0010] In one embodiment, memory address blocks allocated to the same kernel execute aging test tasks in serial mode, while memory address blocks allocated to different kernels execute aging test tasks in parallel mode.

[0011] This application also provides a memory aging test device, including the following modules: The memory allocation module is used to divide the processor's memory space into multiple memory address blocks and allocate them to the processor's cores according to the number of cores of the processor to be tested; The algorithm management module is used to arrange and combine multiple memory test algorithms to generate multiple first algorithm sequences; The test execution module is used to distribute the first algorithm sequence to the kernels using a round-robin full distribution mechanism; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0012] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the memory aging test method as described above.

[0013] This application also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the memory aging test method as described above.

[0014] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the memory aging test method as described above.

[0015] The memory aging test method, apparatus, device, storage medium, and program product provided in this application divide the processor's memory space into multiple memory address blocks according to the number of processor cores and allocate them to the processor cores. Multiple memory test algorithms are arranged and combined to generate multiple first algorithm sequences. A round-robin full distribution mechanism is used to distribute the first algorithm sequences to the cores. Each core runs the distributed first algorithm sequence based on its allocated memory address block to execute the aging test task. By arranging and combining memory test algorithms and using a round-robin full distribution mechanism to distribute them to the cores for execution, it is ensured that each core can run different memory test algorithms in different orders. Furthermore, different cores are running different test algorithms on their memory address blocks at the same time, increasing the complexity of the memory operation scenario. This simulates the real-world operation of memory in actual applications, allowing the aging test results to accurately reflect the memory's performance in real-world applications. Therefore, the test results can effectively guide the selection and quality control of memory modules. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating the memory aging test method provided in the embodiments of this application.

[0018] Figure 2 This is a schematic diagram of memory space allocation provided in an embodiment of this application.

[0019] Figure 3 This is a schematic diagram of the algorithm classification provided in the embodiments of this application.

[0020] Figure 4 This is a schematic diagram of the algorithm distribution provided in the embodiments of this application.

[0021] Figure 5 This is a schematic diagram of the memory aging test process provided in the embodiments of this application.

[0022] Figure 6 This is a schematic diagram of the memory aging test device provided by the present invention.

[0023] Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] It's important to note that memory is a crucial component of a server. When a server runs applications or processes requests, the operating system loads data from external storage devices like hard drives into memory so the CPU can access and process it quickly. The reliability of memory plays a vital role in the overall performance and stability of the server. If memory fails, the system cannot reliably access data, potentially causing applications on the server to experience timeouts, frequent crashes, or significant performance degradation due to data errors. It can even lead to serious malfunctions such as operating system crashes, blue screens, or inability to boot or restart. Therefore, testing server memory to screen and eliminate memory modules with high failure rates is essential.

[0026] In memory aging tests, the design of acceleration factors often only considers environmental conditions such as temperature and humidity, without taking into account the read / write pressure on the memory exerted by the test algorithms during the test. Furthermore, traditional aging tests typically execute all algorithms under test at once, considering the completion of all executions as one test cycle. In this approach, all processor cores tested within the same time period are executing the same test algorithm, resulting in a simplistic testing method, low test scenario complexity, and an inability to simulate the complex memory operation conditions in real-world applications.

[0027] If memory aging tests fail to simulate real-world memory operation scenarios, it can negatively impact subsequent memory use, including but not limited to the inability to effectively expose potential defects. Real-world application scenarios are often complex and varied, involving multiple types of read / write operations, different memory access patterns, and concurrent tasks. If aging tests employ only a single algorithm or method, they may not adequately cover these scenarios, preventing potential defects or vulnerabilities from being detected and exposed during the testing phase. This can lead to the use of memory modules with these issues. Increased risk of early failure: One purpose of aging tests is to accelerate memory through its early failure period. If the test scenarios are too simplistic and fail to simulate the actual workload of the memory, it may prematurely fail due to increased load or changes in application scenarios, causing server malfunctions. Reduced stability: After aging tests, memory should exhibit higher stability. However, if the testing is insufficient, the stability and reliability of the memory cannot be effectively verified. In real-world applications, this can lead to data errors, response timeouts, crashes, and other problems, reducing the overall stability of the server.

[0028] Based on this, this application provides a memory aging test method. On the basis of the acceleration factor, the method further performs aging tests on the memory based on read and write pressure acceleration through a test algorithm, thereby increasing the complexity of the test scenario and accelerating the memory aging test process.

[0029] Specifically, Figure 1 This is a flowchart illustrating the memory aging test method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes the following steps: Step 100: According to the number of cores of the processor to be tested, divide the memory space of the processor into multiple memory address blocks and allocate them to the cores of the processor; Step 200: Arrange and combine multiple memory test algorithms to generate multiple first algorithm sequences; Step 300: Using a round-robin full distribution mechanism, the first algorithm sequence is distributed to the kernels; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform the aging test task.

[0030] Based on the number of cores in the processor (CPU, Central Processing Unit) under test, the processor's memory space is divided into multiple memory address blocks, and these multiple memory address blocks are allocated to the processor's cores to obtain the memory address blocks corresponding to each core.

[0031] As one embodiment, a kernel is allocated one or more memory address blocks; in another embodiment, a kernel is allocated a preset number of memory address blocks.

[0032] As an example, different kernels may be allocated the same or different numbers of memory address blocks.

[0033] As one example, multiple memory address blocks are evenly distributed among different cores of the processor, or multiple memory address blocks are proportionally distributed among different cores of the processor.

[0034] Multiple memory testing algorithms are arranged and combined to generate multiple first algorithm sequences. In the multiple first algorithm sequences, different first algorithm sequences contain different memory testing algorithms, or different first algorithm sequences contain the same memory testing algorithm, but the memory testing algorithms contained therein have different arrangements.

[0035] As an example, any first algorithm sequence may contain some or all of a plurality of memory test algorithms, and different first algorithm sequences may contain the same or different number of memory test algorithms.

[0036] A round-robin full distribution mechanism is adopted to distribute each first algorithm sequence to the processor kernel. Each kernel runs the distributed first algorithm sequence based on the allocated memory address block and performs the aging test task.

[0037] Among them, the round-robin full distribution mechanism is not fixed in order but ensures that all first algorithm sequences are traversed. That is, the round-robin full distribution mechanism distributes all first algorithm sequences to different kernels in different orders.

[0038] It should be noted that the execution of each memory test algorithm in the first algorithm sequence by each kernel is carried out in parallel. In one embodiment, the aging test process includes multiple test rounds. In each test round, different first algorithm sequences are issued to different kernels. During the complete test process, each kernel runs all the first algorithm sequences in a different order based on the allocated memory address blocks.

[0039] By employing a round-robin full distribution mechanism to distribute the first algorithm sequence, it can be ensured that each core of the processor runs some or all of the memory test algorithms in different orders. Furthermore, different cores are running different memory test algorithms within the same time period, which helps to improve the coverage and complexity of actual memory operation scenarios.

[0040] Meanwhile, by permuting and combining memory testing algorithms to generate different first algorithm sequences that cover all possible combinations of different memory testing algorithms, and then sending the first algorithm sequences to the kernel for execution, the memory testing algorithms and their types running in the memory address blocks allocated to the kernel can be determined through the permutation and combination of the first algorithm sequences.

[0041] Furthermore, based on the memory testing algorithm and its type running on the memory address blocks allocated to the processor core, the read / write pressure on the processor's memory space can be determined. Therefore, during memory aging testing, environmental conditions such as temperature and humidity can be considered, and the speedup factor design can fully account for the read / write pressure on memory from the memory testing algorithm, thereby increasing the complexity of the test scenario.

[0042] Furthermore, different kernels run the same number of memory test algorithms and perform the same amount of test tasks when executing aging test tasks, thus ensuring that the test duration is the same for different kernels.

[0043] In this embodiment, the processor's memory space is divided into multiple memory address blocks and allocated to the processor cores according to the number of processor cores. Multiple memory testing algorithms are arranged and combined to generate multiple first algorithm sequences. A round-robin full distribution mechanism is used to distribute the first algorithm sequences to the processor cores. Each core runs the distributed first algorithm sequence based on its allocated memory address block to perform the aging test task. By arranging and combining memory testing algorithms and using a round-robin full distribution mechanism to distribute them to the cores for execution of the aging test task, it can be ensured that each core can run different memory testing algorithms in different orders. Furthermore, different cores are running different test algorithms on their memory address blocks at the same time, which increases the complexity of the memory operation scenario and can simulate the real-world operation of memory in actual applications. This allows the aging test results to accurately reflect the performance of memory in actual applications, thereby ensuring that the test results can effectively guide the selection and quality control of memory modules.

[0044] In one embodiment, the processor's memory space is divided into multiple memory address blocks and allocated to the processor's cores. Specifically, the processor's memory space is divided into multiple memory address blocks according to the number of processor cores, and then the multiple memory address blocks are allocated to each of the processor's cores. Therefore, step 100 includes: Step 101: Determine the memory space partitioning parameters of the processor based on the number of cores of the processor to be tested; the partitioning parameters include block size and number of blocks. Step 102: Divide the memory space into multiple memory address blocks based on the partitioning parameters; Step 103: Allocate the plurality of memory address blocks to the processor's kernel.

[0045] Based on the number of cores of the processor to be tested, the partitioning parameters for the processor's memory space are determined. These partitioning parameters include block size and number of blocks. The processor's memory space is then divided into multiple memory address blocks according to these parameters.

[0046] Furthermore, the divided memory address blocks are allocated to the processor's cores, resulting in memory address blocks corresponding to each core.

[0047] As an example, the number of memory address blocks divided is an integer multiple of the number of processor cores, that is, the number of blocks in the partitioning parameters is an integer multiple of the number of cores.

[0048] In one embodiment, multiple memory address blocks are evenly distributed among the kernels, and the number of memory address blocks allocated to each kernel is greater than or equal to a preset value.

[0049] As an example, the number of memory address blocks allocated to each kernel is a preset value, which is a multiple of the number of blocks relative to the number of kernels. More specifically, each kernel is allocated at least two memory address blocks.

[0050] In one embodiment, memory address blocks allocated to the same kernel execute aging test tasks in serial mode, while memory address blocks allocated to different kernels execute aging test tasks in parallel mode.

[0051] As a specific example, if the total memory space of the processor under test is 2048GB and the number of processor cores is 64, then the block size can be determined to be 16GB, and the number of blocks can be 128, which is twice the number of cores. If the 128 memory address blocks are evenly distributed among each core, then each core can be allocated two memory address blocks.

[0052] like Figure 2 As shown, Figure 2 This is a schematic diagram of the allocation of the processor's memory space provided in an embodiment of this application. The processor to be tested includes a total of N processor cores, from Core1 to CoreN. The processor's memory space is divided into multiple memory address blocks according to the number of processor cores N. Each core is allocated two memory address blocks, namely Block1 and Block2. The number of memory address blocks is 2N, which is twice the number of processor cores.

[0053] Furthermore, aging test tasks between two memory address blocks within each kernel are executed serially, while aging test tasks between different kernels are executed in parallel.

[0054] The permutation and combination of memory testing algorithms is based on the classification of memory testing algorithms. Step 200 specifically includes: Step 201: Classify multiple memory test algorithms according to their algorithm types to obtain an algorithm array corresponding to each algorithm type; the algorithm types include data transformation type, address transformation type, and data-address combination transformation type. Step 202: Select memory testing algorithms from the algorithm array to form an algorithm combination; the algorithm combination includes at least one memory testing algorithm from the algorithm array; Step 203: Arrange the memory testing algorithms in the algorithm combination in different orders to obtain multiple first algorithm sequences.

[0055] First, the memory testing algorithms are categorized according to their algorithm types, resulting in algorithm arrays corresponding to different algorithm types. Each algorithm array contains at least one memory testing algorithm. The algorithm types include data transformation, address transformation, and data-address combination transformation algorithms.

[0056] Figure 3 This is a schematic diagram of algorithm classification provided in the embodiments of this application. The memory testing algorithms include data transformation algorithms, address transformation algorithms, and data-address combination transformation algorithms.

[0057] Data transformation algorithms refer to test algorithms where the test address is written in normal ascending or descending order, without address jumps, and only performs transformations such as shifting on the test data. Specifically, data transformation algorithms include data shifting algorithms, random number algorithms, and random number combination shift algorithms. Address transformation algorithms refer to test algorithms where the test data remains unchanged, but there are address jumps each time data is written. Address transformation algorithms include linear address addressing algorithms, physical address addressing algorithms, and random addressing algorithms. Data-address combination transformation algorithms refer to test algorithms where both the test data and the test address undergo transformations; that is, algorithms combining data transformation and address transformation algorithms.

[0058] By classifying the various memory testing algorithms, we obtain an array of memory testing algorithms of different types, where each algorithm type includes one or more memory testing algorithms. For example... Figure 4 As shown, data transformation algorithms are denoted as A, which includes multiple memory test algorithms such as A1, A2, and A3; address transformation algorithms are denoted as B, which includes multiple memory test algorithms such as B1, B2, and B3; and data address combination transformation algorithms are denoted as C, which includes multiple memory test algorithms such as C1, C2, and C3.

[0059] There are multiple algorithm types, and different algorithm types correspond to different algorithm arrays. When arranging and combining the memory test algorithms, memory test algorithms are selected from each algorithm array to form an algorithm combination. This algorithm combination contains at least one memory test algorithm from at least one algorithm array. The memory test algorithms in the algorithm combination are arranged in different orders to obtain multiple first algorithm sequences.

[0060] In one embodiment, a memory testing algorithm is selected from each algorithm array to form an algorithm combination, which contains one memory testing algorithm for each algorithm type.

[0061] In one embodiment, the proportion of memory test algorithms of different algorithm types is determined based on the number of memory test algorithms in each algorithm array, and memory test algorithms are selected from each algorithm array in proportion to form an algorithm combination each time.

[0062] In one embodiment, memory testing algorithms are selected from each algorithm array to form an algorithm combination based on the number of cores of the processor to be tested. Specifically, the number of memory testing algorithms to be selected is determined based on the number of cores of the processor to be tested, and the number of memory testing algorithms to be selected is evenly distributed among each algorithm array. Algorithm combinations are then obtained by selecting algorithms according to the number of memory testing algorithms allocated to each algorithm array.

[0063] Alternatively, based on the number of cores in the processor to be tested, determine the number of memory testing algorithms to be selected, allocate these algorithms proportionally to each algorithm array, and then select algorithms according to the number of memory testing algorithms allocated to each array to obtain the algorithm combination. The allocation ratio of the selected memory testing algorithms is determined based on the proportion of each memory testing algorithm in each algorithm array.

[0064] In some embodiments, an algorithm array is randomly selected, and a preset number of memory test algorithms are selected from the randomly selected algorithm array to form an algorithm combination.

[0065] Similar to the generation method of the first algorithm sequence, a round-robin full distribution mechanism is adopted to distribute each algorithm sequence to the processor core. It is also based on the algorithm sequence implementation. Specifically, step 300 includes: Step 301: Based on the number of kernels, select target algorithm sequences from the first algorithm sequence to form an algorithm sequence array; Step 302: Arrange the target algorithm sequences in the algorithm sequence array in different orders to obtain multiple second algorithm sequences; each second algorithm sequence contains at least one target algorithm sequence. Step 303: Assign the second algorithm sequence to the kernel; Step 304: Using a round-robin full distribution mechanism, if the second algorithm sequence allocated to the kernel is not empty, a target algorithm sequence is selected sequentially from the second algorithm sequence allocated to the kernel and sent to the kernel. Step 305: If the second algorithm sequence is empty, return to and execute the step of selecting a target algorithm sequence from the first algorithm sequence to form an algorithm sequence array based on the number of kernels, until the test termination condition is met; the test termination condition includes the kernel's test rounds reaching a preset number of rounds, or the kernel's test duration reaching a preset duration.

[0066] Based on the number of kernels, target algorithm sequences are selected from each first algorithm sequence to form an algorithm sequence array. The target algorithm sequences in the algorithm sequence array are arranged in different orders to obtain multiple second algorithm sequences.

[0067] The second algorithm sequence contains at least one target algorithm sequence, and the second algorithm sequence is constructed using the target algorithm sequence as elements. In one embodiment, an algorithm sequence array may include one or more target algorithm sequences. When the algorithm sequence array contains multiple target algorithm sequences, one algorithm sequence array corresponds to multiple second algorithm sequences.

[0068] As an example, in a plurality of second algorithm sequences corresponding to an algorithm sequence array, any one of the second algorithm sequences contains part or all of the target algorithm sequences in the algorithm sequence array.

[0069] In one embodiment, the number of selected target algorithm sequences is the same as the number of kernels; in another embodiment, the number of selected target algorithm sequences is an integer multiple of the number of kernels; in some embodiments, the number of selected target algorithm sequences is determined based on the number of kernels, specifically by arranging the selected target algorithm sequences to obtain a second algorithm sequence with the same number of kernels.

[0070] Each second algorithm sequence is assigned to a processor core, specifically by associating or binding the second algorithm sequence with a processor core. Based on this, a round-robin full distribution mechanism is employed: if the second algorithm sequence assigned to a core is not empty, a target algorithm sequence is selected sequentially from the second algorithm sequences and sent to the core according to the core test round; if the second algorithm sequence is empty, the process returns and executes step 301 until the test termination condition is met.

[0071] The test termination conditions include, but are not limited to, the kernel's test rounds reaching a preset number of rounds, the kernel's test duration reaching a preset duration, or the algorithm sequence being executed by all kernels in a round.

[0072] In one embodiment, the algorithm arrays corresponding to each algorithm type include data transformation algorithms, address transformation algorithms, and data-address combination transformation algorithms. Data transformation algorithms correspond to algorithm array A, address transformation algorithms correspond to algorithm array B, and data-address combination transformation algorithms correspond to algorithm array C.

[0073] When generating the algorithm sequence, a memory test algorithm is selected from each of the algorithm arrays A, B, and C. Data transformation algorithm A1 is selected from algorithm array A, address transformation algorithm B1 is selected from algorithm array B, and data address combination transformation algorithm C1 is selected from algorithm array C, resulting in an algorithm combination consisting of A1, B1, and C1.

[0074] Furthermore, A1, B1, and C1 in the algorithm combination are arranged in different orders to obtain multiple algorithm sequences, including the algorithm sequences [A1,B1,C1], [B1,C1,A1], [C1,A1,B1], [A1,C1,B1], [B1,A1,C1], and [C1,B1,A1].

[0075] Reference Figure 5 Taking a processor with 3 cores (Core1, Core2, and Core3) as an example, and employing a round-robin full distribution mechanism, the target algorithm sequence is selected from the algorithm sequence to form an algorithm sequence array based on the number of cores. The selection of the target algorithm sequence includes two cases: [A1,B1,C1], [B1,C1,A1], [C1,A1,B1] and [A1,C1,B1], [B1,A1,C1], [C1,B1,A1]. If the selected target algorithm sequence is [A1,B1,C1], [B1,C1,A1], or [C1,A1,B1], then the selected target algorithm sequence is arranged in different orders to obtain multiple second algorithm sequences.

[0076] Specifically, according to the kernel's test rounds, an algorithm sequence is selected from the second algorithm sequence allocated to the kernel and sent to it. In each test round, the kernel runs either a memory test algorithm or an algorithm sequence. Furthermore, different kernels run different algorithm sequences simultaneously; at any given moment, different kernels in the processor are running different types of memory test algorithms.

[0077] exist Figure 5 In this system, each kernel is allocated three memory address blocks. Within each allocated memory address block, each kernel executes the memory test algorithms in the algorithm sequence sequentially, from the start address block to the end address block. For example, for kernel Core1, the second algorithm sequence [[A1,B1,C1],[B1,C1,A1],[C1,A1,B1]] is allocated to kernel Core1. According to the kernel's test round, a target algorithm sequence is selected from this second algorithm sequence and sent to kernel Core1.

[0078] like Figure 5 As shown, contiguous memory regions are allocated for kernels Core1 to Core3, logically divided into Block1, Block2, and Block3. Each Block serves as the smallest unit of execution space for the algorithm, and execution proceeds sequentially according to time phases T1, T2, and T3. Core1: In stage T1, data transformation algorithm A1 is run in Block 1; in stage T2, address transformation algorithm B1 is run in Block 2; in stage T3, data address combination transformation algorithm C1 is run in Block 3. Each stage is executed serially in the order of Blocks.

[0079] Core2: In phase T1, address translation algorithm B1 is run in Block 1; in phase T2, data address combination translation algorithm C1 is run in Block 2; in phase T3, data translation algorithm A1 is run in Block 3, proceeding sequentially according to the Block order.

[0080] Core3: In phase T1, the data address combination transformation algorithm C1 is run in Block 1; in phase T2, the data transformation algorithm A1 is run in Block 2; in phase T3, the address transformation algorithm B1 is run in Block 3, and the algorithms are executed serially along the block sequence.

[0081] All three kernels follow the logic of "one block corresponds to one time stage T". They complete the test serially according to their respective algorithm sequences in the order of Block1→Block2→Block3, and the total duration of T1+T2+T3 remains the same.

[0082] After running all the target algorithm sequences in the current second algorithm sequence, kernel Core1 can continue to execute data transformation algorithm A2, address transformation algorithm B2, and data address combination transformation algorithm C2. Following this approach, a round-robin full distribution mechanism is used to distribute some or all of the algorithm sequences corresponding to all possible permutations and combinations of memory testing algorithms to each kernel. The kernel then runs the distributed algorithm sequences based on the allocated memory address blocks, performing aging test tasks until each kernel has traversed all memory testing algorithms.

[0083] exist Figure 5 In this system, each kernel is allocated three memory address blocks, but the execution order of the memory testing algorithms assigned to each kernel differs. This ensures that three different types of memory testing algorithms are executed simultaneously within the same timeframe, significantly increasing the complexity of the test scenario. Furthermore, due to the round-robin full distribution mechanism, each kernel has the same workload for executing aging test tasks. Therefore, it also ensures that each kernel completes the test of the three memory address blocks for the same duration, avoiding waste of processor resources.

[0084] In this embodiment, the processor's memory space is divided into multiple memory address blocks and allocated to the processor cores based on the number of processor cores. A round-robin full distribution mechanism is adopted to distribute memory test algorithms in different orders to the cores. The cores then run the distributed algorithm sequences based on the allocated memory address blocks to perform aging test tasks.

[0085] Furthermore, by classifying memory testing algorithms and combining different types of memory testing algorithms into algorithm combinations, and arranging the memory testing algorithms within the same algorithm combination in different orders, different first algorithm sequences are obtained. Based on the number of processor cores, different first algorithm sequences are selected and combined into an algorithm sequence array. Different first algorithm sequences within the algorithm sequence array are then arranged in different orders to obtain different second algorithm sequences. Based on the second algorithm sequences, the first algorithm sequences are sent to the kernels in different test rounds. This allows different types of memory testing algorithms to run simultaneously on different memory address blocks within the same time period, thereby increasing the overall complexity of the test scenario and accelerating the memory aging test process.

[0086] Furthermore, by adopting a round-robin full distribution mechanism, it is ensured that each processor core needs to execute the same test tasks in a different order during the aging test. While increasing the complexity of the test scenario, it can ensure that the time required for each core to complete the test of the allocated memory address block is basically the same, thereby avoiding the waste of processor resources.

[0087] The memory aging test system provided in the embodiments of this application is described below. The memory aging test system described below can be referred to in correspondence with the memory aging test method described above.

[0088] Reference Figure 6 The memory aging test system provided in this application includes: The memory allocation module 10 is used to divide the memory space of the processor into multiple memory address blocks and allocate them to the cores of the processor according to the number of cores of the processor to be tested. Algorithm management module 20 is used to arrange and combine multiple memory test algorithms to generate multiple first algorithm sequences; The test execution module 30 is used to distribute the first algorithm sequence to each kernel using a round-robin full distribution mechanism; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0089] In one embodiment, the algorithm management module 20 is further configured to: Multiple memory testing algorithms are categorized according to their algorithm types to obtain an algorithm array corresponding to each algorithm type; the algorithm types include data transformation type, address transformation type, and data-address combination transformation type. Memory testing algorithms are selected from the algorithm array to form an algorithm combination; the algorithm combination contains at least one memory testing algorithm from the algorithm array. The memory testing algorithms in the algorithm combination are arranged in different orders to obtain multiple first algorithm sequences.

[0090] In one embodiment, the test execution module 30 is further configured to: Based on the number of kernels, select target algorithm sequences from the first algorithm sequence to form an algorithm sequence array; The target algorithm sequences in the algorithm sequence array are arranged in different orders to obtain multiple second algorithm sequences; Assign the second algorithm sequence to the kernel; A round-robin full distribution mechanism is adopted. If the second algorithm sequence allocated to the kernel is not empty, a target algorithm sequence is selected sequentially from the second algorithm sequence allocated to the kernel and distributed to the kernel. If the second algorithm sequence is empty, return to and execute the step of selecting a target algorithm sequence from each of the algorithm sequences to form an algorithm sequence array according to the number of kernels, until the test termination condition is met; the test termination condition includes the kernel's test rounds reaching a preset number of rounds, or the kernel's test duration reaching a preset duration.

[0091] In one embodiment, the memory allocation module 10 is further configured to: The memory space partitioning parameters of the processor are determined based on the number of cores of the processor to be tested; the partitioning parameters include block size and number of blocks. The memory space is divided into multiple memory address blocks based on the partitioning parameters; The plurality of memory address blocks are allocated to the processor's kernel.

[0092] In one embodiment, the number of memory address blocks is an integer multiple of the number of kernels, the memory address blocks are evenly distributed among the kernels, and the number of memory address blocks allocated to each kernel is greater than or equal to a preset value.

[0093] In one embodiment, memory address blocks allocated to the same kernel execute aging test tasks in serial mode, while memory address blocks allocated to different kernels execute aging test tasks in parallel mode.

[0094] Figure 7 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 7As shown, the electronic device may include: a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute a memory aging test method, which includes: According to the number of cores of the processor to be tested, the memory space of the processor is divided into multiple memory address blocks and allocated to the cores of the processor; Multiple memory testing algorithms are combined and arranged to generate multiple first algorithm sequences; A round-robin full distribution mechanism is adopted to distribute the first algorithm sequence to each kernel; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0095] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0096] On the other hand, embodiments of this application also provide a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can perform the memory aging test method provided by the above methods, the method including: According to the number of cores of the processor to be tested, the memory space of the processor is divided into multiple memory address blocks and allocated to the cores of the processor; Multiple memory testing algorithms are combined and arranged to generate multiple first algorithm sequences; A round-robin full distribution mechanism is adopted to distribute the first algorithm sequence to each kernel; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0097] In another aspect, embodiments of this application also provide a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the memory aging test method provided by the methods described above, the method comprising: According to the number of cores of the processor to be tested, the memory space of the processor is divided into multiple memory address blocks and allocated to the cores of the processor; Multiple memory testing algorithms are combined and arranged to generate multiple first algorithm sequences; A round-robin full distribution mechanism is adopted to distribute the first algorithm sequence to each kernel; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

[0098] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0099] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0100] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A memory aging test method, characterized in that, include: According to the number of cores of the processor to be tested, the memory space of the processor is divided into multiple memory address blocks and allocated to the cores of the processor; Multiple memory testing algorithms are combined and arranged to generate multiple first algorithm sequences; A round-robin full distribution mechanism is adopted to distribute the first algorithm sequence to the kernels; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

2. The memory aging test method according to claim 1, characterized in that, The process of arranging and combining multiple memory testing algorithms to generate multiple first algorithm sequences includes: Multiple memory testing algorithms are categorized according to their algorithm types to obtain an algorithm array corresponding to each algorithm type; the algorithm types include data transformation type, address transformation type, and data-address combination transformation type. Memory testing algorithms are selected from the algorithm array to form an algorithm combination; the algorithm combination contains at least one memory testing algorithm from the algorithm array. The memory testing algorithms in the algorithm combination are arranged in different orders to obtain multiple first algorithm sequences.

3. The memory aging test method according to claim 1, characterized in that, The adoption of a round-robin full distribution mechanism to distribute the first algorithm sequence to the kernel includes: Based on the number of kernels, select target algorithm sequences from the first algorithm sequence to form an algorithm sequence array; The target algorithm sequences in the algorithm sequence array are arranged in different orders to obtain multiple second algorithm sequences; each second algorithm sequence contains at least one target algorithm sequence. Assign the second algorithm sequence to the kernel; A round-robin full distribution mechanism is adopted. If the second algorithm sequence allocated to the kernel is not empty, a target algorithm sequence is selected sequentially from the second algorithm sequence allocated to the kernel and distributed to the kernel. If the second algorithm sequence is empty, return to and execute the step of selecting a target algorithm sequence from the first algorithm sequence to form an algorithm sequence array based on the number of kernels, until the test termination condition is met; the test termination condition includes the kernel's test rounds reaching a preset number of rounds, or the kernel's test duration reaching a preset duration.

4. The memory aging test method according to claim 1, characterized in that, The step of dividing the processor's memory space into multiple memory address blocks and allocating them to the processor's cores according to the number of cores to be tested includes: The memory space partitioning parameters of the processor are determined based on the number of cores of the processor to be tested; the partitioning parameters include block size and number of blocks. The memory space is divided into multiple memory address blocks based on the partitioning parameters; The plurality of memory address blocks are allocated to the processor's kernel.

5. The memory aging test method according to claim 4, characterized in that, The number of memory address blocks is an integer multiple of the number of kernels, and the memory address blocks are evenly distributed among the kernels, with each kernel being allocated a number of memory address blocks greater than or equal to a preset value.

6. The memory aging test method according to claim 1, characterized in that, The aging test tasks are executed serially for memory address blocks allocated to the same kernel, and in parallel for memory address blocks allocated to different kernels.

7. A memory aging test system, characterized in that, include: The memory allocation module is used to divide the processor's memory space into multiple memory address blocks and allocate them to the processor's cores according to the number of cores of the processor to be tested; The algorithm management module is used to arrange and combine multiple memory test algorithms to generate multiple first algorithm sequences; The test execution module is used to distribute the first algorithm sequence to the kernels using a round-robin full distribution mechanism; each kernel runs the distributed first algorithm sequence based on the allocated memory address block to perform aging test tasks.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the memory aging test method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory aging test method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the memory aging test method as described in any one of claims 1 to 6.

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