PCIe overspeed mode implementation method, data transmission method and system

Abstract

The invention discloses a PCIe (Peripheral Component Interconnect Express) overspeed mode implementation method, a data transmission method and a system, and the PCIe overspeed mode implementation method comprises the steps: if a link state and hardware information support a PCIe overspeed mode, obtaining a pre-stored maximum overspeed rate, and determining whether a historical failure rate exists; if the maximum overspeed rate does not exist, the current rate of the PCIe link is increased according to a preset first step length, if the maximum overspeed rate exists and the historical failure rate is larger than the maximum overspeed rate, a second overspeed rate is determined, the second overspeed rate = the historical failure rate minus a third step length, and the third step length is smaller than the first step length; the method comprises the following steps: firstly, increasing a current rate of a PCIe link according to a first step length to enable a link rate to reach a maximum overspeed rate; and increasing the current rate of the PCIe link by adopting a third step length so as to enable the link rate to reach the second overspeed rate, and executing the balancing operation when / after the current rate is increased each time. According to the invention, the data transmission speed and stability can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer technology, and in particular to a PCIe overspeed mode implementation method, a data transmission method and system. BACKGROUND

[0002] In modern computer systems, high-speed data transmission technology has become an indispensable core component. Especially under the rapid development of big data, cloud computing, artificial intelligence and other fields, higher requirements are put forward for the speed and efficiency of data transmission. As a widely used high-speed serial computer expansion bus standard, PCI Express (PCIe) bus can provide efficient data transmission and flexible expansion capability. With the continuous evolution of technology, the standard of PCIe has developed from the initial 2.0 version to the latest 6.0 version. Among them, the data transmission rate of PCIe 2.0 is 5GT / s (about 500MB per second after conversion), and the data transmission rate of PCIe 6.0 is as high as 64GT / s.

[0003] In the scenario of high-speed data transmission, the quality and stability of the signal undoubtedly play a decisive role. Because of the existence of electromagnetic interference, signal reflection, cable loss and other factors, high-speed signals are likely to produce distortion or attenuation phenomenon during transmission, thereby causing transmission errors. In view of this, equalization technology is applied to high-speed data transmission. PCIe belongs to high-speed bus, and the propagation of high-speed signals will bring great interference and will be easily distorted. Equalization technology ensures the stability of high-speed transmission by preprocessing and post-processing the signal at the sending end and the receiving end. Therefore, to achieve higher transmission rate, effective transmission equalization is needed. Equalization technology uses pre-processing and correction of signals to ensure that signals can be stably transmitted under the condition of long-distance transmission or high-speed transmission, thereby ensuring the accuracy and reliability of data transmission.

[0004] Because PCIe is often designed with a larger deserializer (SerDes), SerDes is integrated in the PCIe hardware part to realize serialization and deserialization data. Because the rate of Serdes and the rate of PCIe do not match, in order to meet the rate requirement of PCIe, the designer considers a larger Serdes, such as the sixth generation PCIe standard maximum rate is 64GT / s, and its corresponding Serdes is as high as 112GT / s, which is far from fully utilizing the standard maximum rate of Serdes. SUMMARY

[0005] The purpose of the present application is to provide a PCIe overspeed mode implementation method, a data transmission method and system to improve the speed and stability of data transmission.

[0006] To achieve the above object, the technical scheme adopted by the present application is as follows:

[0007] A PCIe overspeed mode implementation method, comprising the following steps:

[0008] According to the preset PCIe overspeed mode corresponding PCIe link state requirements, judge whether the current PCIe link state supports PCIe overspeed mode;

[0009] According to the preset PCIe overspeed mode corresponding PCIe link hardware information requirements, judge whether the current PCIe link hardware information supports PCIe overspeed mode;

[0010] If the link state and the hardware information support PCIe overspeed mode, then start PCIe overspeed mode by the following way:

[0011] Get the maximum overspeed rate stored in advance, and determine whether there is a pre-stored historical failure rate; If there is no historical failure rate, increase the current speed of PCIe link according to the preset first step, and perform balancing operation every time / after increasing the current speed, so that the speed of PCIe link reaches the maximum overspeed rate;

[0012] If there is a pre-stored historical failure rate, and the historical failure rate is greater than the maximum overspeed rate, determine the second overspeed rate: the second overspeed rate = historical failure rate-third step, the third step is less than the first step;

[0013] Increase the current speed of PCIe link according to the preset first step, and perform balancing operation every time / after increasing the current speed, so that the speed of PCIe link reaches the maximum overspeed rate;

[0014] If the PCIe link is running at the maximum overspeed rate, use the third step to increase the current speed of PCIe link, and perform balancing operation every time / after increasing the current speed, so that the speed of PCIe link reaches the second overspeed rate.

[0015] Further, any of the above technical solutions or a combination of multiple technical solutions, starting PCIe overspeed mode, further comprises:

[0016] If there is a pre-stored historical failure rate, and the historical failure rate is not greater than the maximum overspeed rate, determine the first overspeed rate: first overspeed rate = historical failure rate-first step;

[0017] According to a preset first step, the current rate of the PCIe link is increased, and a balancing operation is performed to make the rate of the PCIe link reach the first overspeed rate;

[0018] If the PCIe link is stably operated at the first overspeed rate, a second step is used to increase the current rate of the PCIe link, and a balancing operation is performed each time the current rate is increased to make the rate of the PCIe link reach the maximum overspeed rate, and the second step is smaller than the first step.

[0019] Further, any one of the above technical solutions or a combination of multiple technical solutions, starting the PCIe overspeed mode further comprises:

[0020] Each time the current rate of the PCIe link is updated according to a preset first step, a balancing operation is performed, and if the balancing fails, the current rate of the PCIe link is reduced according to the preset first step and a balancing operation is performed until the balancing succeeds.

[0021] Further, any one of the above technical solutions or a combination of multiple technical solutions, the first step is a constant value or a variable value, and if the first step is a variable value, the closer the rate of the PCIe link is to the maximum overspeed rate during the starting of the PCIe overspeed mode, the smaller the first step is.

[0022] Further, any one of the above technical solutions or a combination of multiple technical solutions, further comprising: reducing the current rate of the PCIe link according to a preset first step and performing a balancing operation until the balancing succeeds, then determining the current rate corresponding to the balancing success as the maximum overspeed rate, and storing the maximum overspeed rate.

[0023] Further, any one of the above technical solutions or a combination of multiple technical solutions, after the balancing fails, the current rate of the PCIe link is reduced according to a preset first step and a balancing operation is performed until the balancing succeeds.

[0024] Determine the rate corresponding to the first balancing failure in the current starting of the PCIe overspeed mode process as the historical failure rate, or determine the rate corresponding to the last balancing failure in the current starting of the PCIe overspeed mode process as the historical failure rate.

[0025] Further, any one of the above technical solutions or a combination of multiple technical solutions, after starting the PCIe overspeed mode, if the PCIe link is stably operated at the maximum overspeed rate, the following steps are performed:

[0026] Then, the current rate of the PCIe link is increased according to a preset fourth step, and the fourth step is smaller than the first step.

[0027] And performing the equalization operation each time the current rate is increased / decreased until equalization failure occurs or the current rate of the PCIe link reaches a preset overspeed rate threshold, the overspeed rate threshold being greater than the maximum overspeed rate.

[0028] Further, any one of the above technical solutions or a combination of the above technical solutions, the maximum overspeed rate is the upper limit rate of stable operation of the PCIe link in the previous PCIe overspeed mode; or,

[0029] The maximum overspeed rate is the upper limit rate of stable operation in the overspeed mode predicted by the software and hardware of the PCIe link; or,

[0030] The maximum overspeed rate is determined according to the following formula: V Turbo =(1+α)V1, where V Turbo represents the maximum overspeed rate, V1 represents the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link, and 0<α<1.

[0031] Further, any one of the above technical solutions or a combination of the above technical solutions, the first step size corresponds to the maximum overspeed rate, the greater the maximum overspeed rate, the greater the first step size; or,

[0032] The difference between the maximum overspeed rate and the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link is determined, and the first step size corresponds to the difference, the greater the difference, the greater the first step size.

[0033] Further, any one of the above technical solutions or a combination of the above technical solutions, whether the link state of the PCIe link supports the PCIe overspeed mode is determined by:

[0034] Determine how many generations of PCIe the PCIe link supports at most, assuming the PCIe link supports the Kth generation of PCIe at most, K takes 2 or 3 or 4 or 5 or 6;

[0035] If the current rate of the PCIe link is the standard maximum rate corresponding to the Kth generation of PCIe, and the bit error rate is lower than the preset bit error rate threshold, it is determined that the link state of the PCIe link supports the PCIe overspeed mode.

[0036] Further, any one of the above technical solutions or a combination of the above technical solutions, if the PCIe link supports no less than the 5th generation of PCIe at most, and the current rate of the PCIe link does not reach the standard maximum rate corresponding to the 5th generation of PCIe, whether the PCIe link supports cross-level equalization is determined;

[0037] If the PCIe link supports cross-generation equalization, the current rate of the PCIe link is raised to the standard maximum rate corresponding to the 5th generation PCIe, and an equalization operation is performed;

[0038] If the PCIe link does not support cross-generation equalization, the current rate of the PCIe link is raised generation by generation to the standard maximum rate corresponding to the 5th generation PCIe, and an equalization operation is performed each time the rate of the PCIe link is raised.

[0039] Further, any one of the above technical solutions or a combination of multiple technical solutions, if the PCIe link supports not less than the 5th generation PCIe, and the current rate of the PCIe link reaches the standard maximum rate corresponding to the 5th generation PCIe, the current rate of the PCIe link is raised to the standard maximum rate corresponding to the 6th generation PCIe, and an equalization operation is performed;

[0040] If the equalization is successful, it is determined whether the PCIe link supports the PCIe turbo mode, if yes, the PCIe turbo mode is started, otherwise the PCIe link maintains the current running state;

[0041] If the equalization fails, the current rate of the PCIe link is reduced to make the PCIe link stably run at the standard maximum rate corresponding to the 5th generation PCIe, and it is determined whether the PCIe link supports the 5th generation PCIe, if yes, it is determined whether the PCIe link supports the PCIe turbo mode, if yes, the PCIe turbo mode is started, otherwise the PCIe link maintains the current running state.

[0042] Further, any one of the above technical solutions or a combination of multiple technical solutions, whether the hardware information of the PCIe link supports the PCIe turbo mode is determined by the following method:

[0043] If the hardware supports the PCIe turbo mode, and the working state of the hardware also supports the PCIe turbo mode, it is determined that the hardware information of the PCIe link supports the PCIe turbo mode;

[0044] The working state of the hardware also supports the PCIe turbo mode includes that the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold.

[0045] Further, any one of the above technical solutions or a combination of multiple technical solutions, after the PCIe turbo mode is implemented, further comprising maintaining the PCIe turbo mode by the following steps:

[0046] monitoring a link state of the PCIe link, the link state further comprising a signal jitter condition;

[0047] if the data transmission quality does not meet the preset first level requirement but meets the preset second level requirement, reducing the current rate of the PCIe link by a preset fifth step size and performing the equalization operation, the fifth step size being smaller than the fourth step size;

[0048] if the data transmission quality does not meet the preset second level requirement but meets the preset third level requirement, reducing the current rate of the PCIe link to a rate corresponding to a last stable operation and performing the equalization operation;

[0049] if the data transmission quality does not meet the preset third level requirement, closing the PCIe over-speed mode and performing the equalization operation;

[0050] the first level requirement, the second level requirement and the third level requirement have requirements for the data transmission quality in a descending order.

[0051] According to another aspect of the present application, a data transmission method is provided, which is based on the PCIe over-speed mode implementation method according to any one of the above technical solutions or a combination of multiple technical solutions.

[0052] According to another aspect of the present application, a data transmission system is provided, which is based on the PCIe over-speed mode implementation method according to any one of the above technical solutions or a combination of multiple technical solutions.

[0053] The technical solution provided by the present application has the following beneficial effects:

[0054] a. The PCIe over-speed mode implementation method provided by the present application combines multiple speed-up strategies and equalization operations, uses corresponding step sizes to improve the data transmission rate of the PCIe link for different situations, and combines the corresponding data of the historical PCIe over-speed mode including the maximum over-speed rate and the historical failure rate, so that the way of starting the PCIe over-speed mode can be adjusted more finely according to the changes in actual applications, thereby improving the equalization effect, stably and reliably realizing a higher PCIe transmission rate, and improving the utilization rate of the SerDes rate;

[0055] b. The present application can ensure the stability of data transmission through flexible and variable equalization adjustment strategies: when adjusting the data transmission rate, the present technical solution adopts a real-time monitoring link state and self-adaptive adjustment mechanism, which can adjust the rate of the PCIe link under the premise of ensuring the stability of data transmission, and exit the over-speed mode in time when the transmission is unstable, and restore the conservative transmission speed, thereby avoiding the problem of data transmission failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A flowchart of a method for implementing PCIe super-speed mode based on equalization technology provided by an exemplary embodiment of the present invention;

[0058] Figure 2 A flowchart of a process for implementing PCIe overspeed mode when the historical failure rate is less than the maximum overspeed rate is provided for an exemplary embodiment of the present invention;

[0059] Figure 3 A flowchart of a process for implementing PCIe overspeed mode when the historical failure rate is greater than the maximum overspeed rate is provided for an exemplary embodiment of the present invention;

[0060] Figure 4 A flowchart of a process for implementing PCIe overspeed mode after reaching the maximum overspeed rate is provided for an exemplary embodiment of the present invention;

[0061] Figure 5 A flowchart of a PCIe overspeed mode implementation process applicable to various generations of PCIe is provided as an exemplary embodiment of the present invention;

[0062] Figure 6 A flowchart of an adaptive adjustment mechanism in PCIe super-speed mode is provided as an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0064] It should be noted that the terms "first", "second", and the like in the description and claims of the application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, device, product or apparatus that includes a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products or apparatus.

[0065] Related terms involved in the application are introduced:

[0066] PCIe (PCI Express): a widely used high-speed serial computer expansion bus standard, which can provide efficient data transmission and flexible expansion capability;

[0067] PCIe standard mode: PCIe device / link / system transmits data at the standard rate corresponding to the PCIe version it supports, and the PCIe device / link / system transmits data at the base rate and bandwidth supported by the link it is in;

[0068] PCIe high-speed mode: PCIe device / link / system transmits data at the standard maximum rate corresponding to the PCIe version it supports, and the PCIe device / link / system operates at the standard maximum rate corresponding to the higher PCIe version it supports;

[0069] PCIe ultra-speed mode: PCIe device / link / system transmits data at a rate higher than the standard maximum rate corresponding to the highest PCIe version it supports, and the PCIe device / link / system operates at a rate higher than the standard maximum rate corresponding to the higher PCIe version it supports; for example, taking a PCIe device / link / system supporting the highest PCIe 6.0 version as an example, when the PCIe device / link / system works in PCIe high-speed mode, its rate is 64GT / s, when the PCIe device / link / system works in PCIe standard mode, its rate is usually less than 64GT / s; when the PCIe device / link / system works in PCIe ultra-speed mode, its rate is usually greater than 64GT / s;

[0070] Balancing technology: refers to a technology for compensating for loss, distortion and other problems caused by channel characteristics and other factors during signal transmission, thereby improving signal quality and transmission reliability;

[0071] Equalization success: the PCIe device / link / system can stably run at the current rate (current data transmission rate), which can be judged according to the eye opening degree in the equalization process, equalizer convergence, and other indicators, and data transmission quality (error rate);

[0072] Equalization failure: the PCIe device / link / system cannot stably run at the current rate (current data transmission rate), which can be judged according to the eye opening degree in the equalization process, equalizer convergence, and other indicators, and data transmission quality (error rate);

[0073] SerDes: deserializer integrated in the PCIe hardware part to realize serialization and deserialization of data.

[0074] In view of the rapid development in the fields of big data, cloud computing, artificial intelligence, etc., the requirements for data transmission speed and efficiency are becoming higher and higher. In the PCIe design, a higher rate deserializer is often selected, for example, the SerDes corresponding to the 6.0 version can reach 112GT / s, and the standard maximum rate of the 6.0 version of PCIe is 64GT / s, which is far from fully utilizing the standard maximum rate of Serdes, which gives SerDes more performance potential mining space.

[0075] Based on this, the application provides a PCIe-based super-speed Turbo mode and an equalization method thereof. By means of advanced equalization technology, the parameters of the signal are finely adjusted, and the signal attenuation and distortion problems caused by factors such as electromagnetic interference, signal reflection, and cable loss in the high-speed transmission process are effectively compensated, so that the rate utilization rate of SerDes is significantly improved, thereby creating favorable conditions for trying to break through the maximum rate limit of PCIe standard for super-speed mode.

[0076] In an embodiment of the application, a PCIe super-speed mode implementation method based on equalization technology is provided, as shown in Figure 1 The method comprises the following steps:

[0077] According to the link state requirement of the PCIe link corresponding to the preset PCIe super-speed mode, it is judged whether the link state of the current PCIe link supports the PCIe super-speed mode;

[0078] According to the hardware information requirement of the PCIe link corresponding to the preset PCIe super-speed mode, it is judged whether the hardware information of the current PCIe link supports the PCIe super-speed mode;

[0079] If the link state and the hardware information both support the PCIe super-speed mode, the PCIe super-speed mode is started by the following way:

[0080] acquiring a maximum overspeed rate stored in advance;

[0081] The current rate of the PCIe link is increased by a preset first step, and an equalization operation is performed each time the current rate is increased to reach the maximum overspeed rate.

[0082] The maximum overspeed rate is greater than a standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link. The maximum overspeed rate can be determined and stored in advance in the following ways.

[0083] The first way is to determine an upper limit rate at which the PCIe link stably operates in a previous PCIe overspeed mode. The upper limit rate can be the upper limit rate at which the PCIe link stably operates in the previous PCIe overspeed mode the last time, or the average of the upper limit rates at which the PCIe link stably operates in the previous PCIe overspeed mode multiple times. The upper limit rate is determined as the maximum overspeed rate.

[0084] The second way is that the maximum overspeed rate is an upper limit rate at which the PCIe link stably operates in an overspeed mode predicted based on software and hardware of the PCIe link. The prediction method can be prediction by technicians according to experience, or prediction by simulation, test, etc. The upper limit rate is determined as the maximum overspeed rate.

[0085] The third way is to determine the maximum overspeed rate by using a preset calculation formula. For example, the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link is determined as V1, and then V Turbo =(1+α)V1, where V Turbo represents the maximum overspeed rate, 0<α<1, and preferably, α takes values such as 0.05, 0.1, 0.15, 0.20, etc.

[0086] The first step can be a constant value or a variable value. Regardless of which of the above ways is used to determine the maximum overspeed rate, the first step corresponds to the maximum overspeed rate. The greater the maximum overspeed rate, the greater the first step. For example, for a larger maximum overspeed rate, the first step can be set to 2 GT / s, and for a smaller maximum overspeed rate, the first step can be set to 1 GT / s.

[0087] More preferably, the difference between the maximum overspeed rate and the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link is determined, and the first step corresponds to the difference (i.e., V Turbo -V1). The greater the difference, the greater the first step. For example, the first step β1 is determined according to the difference between V Turbo and V1, β1=(V TurboV1) / N, wherein N is a target update step number, N can be a natural number not less than 2, preferably, N can be 5, 10, 15, 20, 25, 30 and the like.

[0088] If the first step length is variable, the first step length is smaller when the speed of the PCIe link is closer to the maximum speed in the process of starting the PCIe speed-up mode. In practical applications, the first step length can be set to decrease step by step in the process of starting the PCIe speed-up mode.

[0089] In an embodiment of the present application, the PCIe speed-up mode implementation method based on the equalization technology starts the PCIe speed-up mode based on Figure 2 and Figure 3 In the embodiment, if there is no historical failed speed, the PCIe speed-up mode is started according to the flow shown in Figure 1 In the embodiment, the equalization operation is performed each time the current speed of the PCIe link is updated by the preset first step length, and if the equalization fails, the current speed of the PCIe link is reduced by the preset first step length and the equalization operation is performed until the equalization succeeds, and then it is determined that the PCIe speed-up mode is completed.

[0090] If there is the historical failed speed, not only the maximum speed-up speed stored in advance is needed to be obtained, but also it is needed to determine whether there is the historical failed speed stored in advance, and the PCIe speed-up mode is started in combination of the maximum speed-up speed and the historical failed speed.

[0091] As shown in Figure 2 In the embodiment, there is the historical failed speed stored in advance, and the historical failed speed is not greater than the maximum speed-up speed, and then the first speed-up speed is determined: first speed-up speed = historical failed speed - first step length.

[0092] The current speed of the PCIe link is increased by the preset first step length, and the equalization operation is performed, so that the speed of the PCIe link reaches the first speed-up speed. In the process of iteratively updating the speed of the PCIe link from the current speed to the first speed-up speed by the first step length, if there is a case of equalization failure, the current speed of the PCIe link is reduced by the first step length and the equalization operation is performed until the PCIe link stably operates at a speed-up speed or V1, and then it is determined that the PCIe speed-up mode is completed.

[0093] If each time the equalization operation is successful, when the PCIe link is stably running at the first overspeed rate, the following operation is performed: the current rate of the PCIe link is increased by a second step size, and the equalization operation is performed each time the current rate is increased, so that the rate of the PCIe link reaches the maximum overspeed rate, and the second step size is smaller than the first step size. In the process of iteratively updating the rate of the PCIe link from the current rate to the maximum overspeed rate according to the second step size, if there is an equalization failure, the current rate of the PCIe link is reduced according to the second step size and the equalization operation is performed until the PCIe link is stably running at an overspeed rate or V1, and it is determined that the PCIe overspeed mode is completed. If there is no equalization failure, when the PCIe link is stably running at the maximum overspeed rate, it is determined that the PCIe overspeed mode is completed.

[0094] As shown in Figure 3 In this embodiment, there is a pre-stored historical failure rate, and the historical failure rate is greater than the maximum overspeed rate, and the second overspeed rate is determined: the second overspeed rate = historical failure rate - third step size, β3 < β2 < β1, β1 is the first step size, β2 is the second step size, and β3 is the third step size.

[0095] The current rate of the PCIe link is increased according to the preset first step size, and the equalization operation is performed each time the current rate is increased, so that the rate of the PCIe link reaches the maximum overspeed rate. In the process of iteratively updating the rate of the PCIe link from the current rate to the maximum overspeed rate according to the first step size, if there is an equalization failure, the current rate of the PCIe link is reduced according to the first step size and the equalization operation is performed until the PCIe link is stably running at an overspeed rate or V1, and it is determined that the PCIe overspeed mode is completed.

[0096] If there is no equalization failure, when the PCIe link is stably running at the maximum overspeed rate, the following operation is performed: the current rate of the PCIe link is increased by a third step size, and the equalization operation is performed each time the current rate is increased, so that the rate of the PCIe link reaches the second overspeed rate.

[0097] In the process of iteratively updating the rate of the PCIe link from the current rate to the second overspeed rate according to the third step size, if there is an equalization failure, the current rate of the PCIe link is reduced according to the third step size and the equalization operation is performed until the PCIe link is stably running at an overspeed rate or V1, and it is determined that the PCIe overspeed mode is completed. If there is no equalization failure, when the PCIe link is stably running at the second overspeed rate, it is determined that the PCIe overspeed mode is completed.

[0098] In the above described process of starting the PCIe turbo mode, after determining that the PCIe turbo mode is completed, the current rate corresponding to the last successful equalization is determined as the maximum turbo rate, and the maximum turbo rate is stored for application in the next start of the PCIe turbo mode.

[0099] In one embodiment of the present application, as shown in Figure 4 After starting the PCIe turbo mode, if the PCIe link is stably running at the maximum turbo rate, the following steps are continuously executed:

[0100] The current rate of the PCIe link is increased by a preset fourth step size β4, β4<β3<β2<β1;

[0101] And each time the current rate is increased, an equalization operation is performed until equalization fails or the current rate of the PCIe link reaches a preset turbo rate threshold, which is greater than the maximum turbo rate.

[0102] After equalization fails, the current rate of the PCIe link is reduced by the fourth step size and an equalization operation is performed until equalization is successful again. The rate corresponding to the first equalization failure in the current start of the PCIe turbo mode is determined as the historical failure rate, or the rate corresponding to the last equalization failure in the current start of the PCIe turbo mode is determined as the historical failure rate, for application in the next start of the PCIe turbo mode.

[0103] In any of the above described embodiments, the specific conditions for starting the turbo mode generally include link state, hardware conditions and software conditions.

[0104] First, the link state is monitored. It is necessary to continuously and accurately monitor the running state of the PCIe link, focusing on whether it can stably and reliably run at the highest generation (such as Gen6) data rate it supports. This involves real-time evaluation of the bit error rate (BER) of the link, the completion of each stage of the link training state machine (LTSSM), and various physical layer parameters (such as signal strength, clock synchronization, etc.). Specific bit error rate thresholds (e.g., BER below 1x10-12) and other conditions can be set to determine whether the link meets the requirements for reliable operation, thereby providing the basic conditions for activating the Turbo mode.

[0105] Specifically, by reading the PCIe controller internal registers, the current rate and the supported standard maximum rate (maximum non-zero rate) are obtained, see Table 1, the standard maximum rate supported by each generation of PCIe is shown in Table 1. The bit error rate can be determined according to the hardware error counter on the PCIe link. By reading the internal registers, it is obtained whether the current link training state machine is in L0 state (L0 is the normal running state of the PCIe link, which represents the highest performance and health state of the link).

[0106] Table 1 PCIe specification evolution milestones

[0107]

[0108]

[0109] The link state can include the standard maximum rate and the bit error rate, and can also include the signal strength and the clock synchronization state. The evaluation of the signal strength is as follows: by comparing the received signal voltage with the preset threshold through the internal voltage comparison module on the PCIe link, it is judged whether the signal strength is within the acceptable range, so as to evaluate the signal integrity and ensure that the current communication quality meets the requirements.

[0110] The clock synchronization state is evaluated by the following way: by the clock jitter detection module, the quality of the clock signal is judged; the synchronization error counting module: records the clock synchronization errors, such as clock jump errors, and further evaluates the reliability and performance of data transmission.

[0111] Secondly, the hardware support condition is checked. To confirm whether the relevant hardware devices (such as PCIe controller, transceiver, etc.) have the function of supporting the super-speed mode, it can be determined by checking the internal registers of the device whether the hardware supports cross-generation balancing and whether it supports the super-speed mode. The hardware layer needs to ensure that its power, heat dissipation and other conditions can cope with the possible increased load under the super-speed mode. If the hardware supports the PCIe super-speed mode and the working state of the hardware also supports the PCIe super-speed mode, it is determined that the hardware information of the PCIe link supports the PCIe super-speed mode.

[0112] The working state of the hardware also supports the PCIe turbo mode, including that the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold. Specifically, the current power, temperature and heat dissipation of the hardware can be determined by an internal voltage / current sensor, a temperature sensor. For the power level, the PCIe device is internally provided with a voltage / current sensor to monitor the power consumption of the device. The data of the sensor can be read by an internal management controller and compared with the preset power threshold. The PCIe device usually defines a maximum power limit, i.e., the power threshold, and limits the performance when the power consumption exceeds the limit. For the heat dissipation level, the PCIe device is provided with a temperature sensor, such as a thermistor or a thermocouple, to measure the temperature of the device. The device compares the preset temperature threshold to determine whether the heat dissipation condition is sufficient.

[0113] In addition, the software support condition needs to be checked. Specifically, the software aspect needs to ensure that the start, speed adjustment and other operations of the turbo mode can be correctly configured and managed. Whether the software supports the turbo mode can be determined by a function register identification bit of the hardware device or a corresponding field in a software configuration file. Of course, in some specific applications, the driver and system software supporting the turbo mode can be pre-configured, and the software support condition does not need to be checked in actual application, and the software is assumed to support the turbo mode, thereby reducing the judgment conditions for starting the turbo mode.

[0114] In an embodiment of the present application, the PCIe turbo mode implementation method based on the equalization technology is performed according to the flow as shown in Figure 5

[0115] In the embodiment, the PCIe link bypasses the generation-by-generation equalization process at a lower data rate and directly enters the standard maximum rate supported by the PCIe link and performs the equalization operation. Specifically, as shown in Figure 5 When the PCIe version supported by the PCIe link is greater than or equal to 5, the PCIe link first performs training at the standard maximum rate corresponding to the first generation (Gen1) until the L0 state, i.e., the stable running state, is reached. Then, it is determined whether the PCIe link supports cross-generation equalization.

[0116] If the PCIe link supports cross-generation equalization, i.e., it is confirmed that the PCIe link (all components on the PCIe link, including the retimer if any) can be equalized across generations, it directly enters the fifth generation (Gen5), changes the rate of the PCIe link to the standard maximum rate corresponding to the fifth generation (Gen5) PCIe, and directly performs the equalization operation in the fifth generation (Gen5).

[0117] ​If the PCIe link does not support cross-generation equalization, the current rate of the PCIe link is increased to the standard maximum rate corresponding to the 5th generation PCIe by generations, and an equalization operation is performed each time the current rate of the PCIe link is increased.

[0118] In this embodiment, all equalization procedures for the 64.0 GT / s (i.e., the sixth generation) rate, including re-equalization, must be started from the 32.0 GT / s (the fifth generation) data rate to ensure that the PCIe link can stably and reliably transmit data. Specifically, if the PCIe link supports no less than the 5th generation PCIe and the current rate of the PCIe link reaches the standard maximum rate corresponding to the 5th generation PCIe, the current rate of the PCIe link is increased to the standard maximum rate corresponding to the 6th generation PCIe, and an equalization operation is performed.

[0119] If the standard maximum rate corresponding to the 6th generation PCIe is successfully equalized, it is determined whether the PCIe link supports the PCIe turbo mode. If yes, the PCIe turbo mode is enabled, otherwise the PCIe link maintains the current running state. If the equalization fails, the current rate of the PCIe link is reduced to enable the PCIe link to stably run at the standard maximum rate corresponding to the 5th generation PCIe, and it is determined whether the PCIe link supports the 5th generation PCIe. If yes, it is determined whether the PCIe link supports the PCIe turbo mode. If yes, the PCIe turbo mode is enabled, otherwise the PCIe link maintains the current running state.

[0120] Only when the PCIe link can stably run at the standard maximum rate supported by the device, the condition of the turbo mode is met, at this time, the "highest rate turbo enable" in the turbo capability register is set to 1b, and the "disable highest rate turbo enable" in the turbo control register is set to 0b.

[0121] After the above conditions are met, the turbo rate acceleration link is entered, the rate is increased in turn to perform the equalization operation, until the maximum stable equalization rate is reached, and finally the link runs at this maximum stable equalization rate. At the same time, the initial value of the turbo rate corresponding to this equalization operation is recorded as the standard maximum rate supported by the device (assuming that the initial value is set based on the rule that the standard maximum rate supported by the device is started).

[0122] The application does not specifically limit the equalization operation, and the protection scope of the application is not limited by the specific equalization operation mode. The equalization operation can include transmission end equalization operation, reception end equalization, and adaptive equalization, etc.

[0123] The sending-end equalization operation includes pre-emphasis, i.e. the amplitude of the specific frequency component, usually the high frequency component, of the signal is increased at the sending end, so that it can better resist the attenuation of the channel during transmission; de-emphasis, which is the reverse process of pre-emphasis, i.e. the low frequency component of the signal is appropriately attenuated at the sending end, and the amplitude of the high frequency component is relatively increased, so as to improve the spectral characteristics of the signal and reduce ISI.

[0124] The receiving-end equalization operation includes a continuous time linear equalizer (CTLE), a linear equalizer that compensates for the signal in the continuous time domain by amplifying and filtering the signal to recover the amplitude and shape of the signal, which is suitable for high-speed links and can compensate for signal loss in real time, and the gain and bandwidth parameters thereof are adjustable and can be optimized according to different channel conditions; a decision feedback equalizer that uses the decided data symbols to estimate and eliminate the interference of subsequent symbols, which further removes the inter-symbol interference by feedback processing of the detected signal, thereby improving the quality of the received signal, and is particularly suitable for processing signals with strong inter-symbol interference.

[0125] The adaptive equalization technology includes dynamically adjusting equalization parameters such as the gain of the CTLE and the weight of the DFE to adapt to different channel conditions and transmission environments. Adaptive equalization can automatically optimize the equalization settings based on real-time monitoring of signal quality indicators such as bit error rate and eye opening, so that the system always maintains good received signal quality.

[0126] After each equalization operation is completed, the success of the equalization is determined by analyzing the relevant indicators in the equalization process (e.g. the eye opening of the receiving end, the convergence of the equalizer, etc.). If the equalization is successful, the current speed of the PCIe link is increased by a certain step size (e.g. 1 GT / s), i.e. the current speed of the next equalization operation becomes the current speed of the last operation + 1 GT / s. Then, the next round of equalization operation is immediately started to adapt to the new speed requirement and ensure that the link can still maintain good signal transmission quality at a higher speed.

[0127] If the equalization fails after a certain equalization operation, the current speed needs to be adjusted downward and the equalization operation needs to be performed. When the equalization is successful, the current speed value can be recorded, and the PCIe link can be locked at this current speed for operation, and subsequent data transmission can be based on this current speed to ensure the stability and continuity of the link.

[0128] After implementing the PCIe speed-up mode, it also includes Figure 6The adaptive adjustment mechanism shown maintains the PCIe link to run stably in the PCIe turbo mode: the link state of the PCIe link is monitored, the current data transmission quality is evaluated according to the link state, and the link state also includes the signal jitter condition. If the data transmission quality does not meet the preset first level requirement but meets the preset second level requirement, the current speed of the PCIe link is reduced by a preset fifth step size and an equalization operation is performed, and the fifth step size is smaller than the fourth step size; if the data transmission quality does not meet the preset second level requirement but meets the preset third level requirement, the current speed of the PCIe link is reduced to the speed corresponding to the last stable operation and an equalization operation is performed; if the data transmission quality does not meet the preset third level requirement, the PCIe turbo mode is closed and an equalization operation is performed; the first level requirement, the second level requirement and the third level requirement are requirements for the data transmission quality in turn.

[0129] Specifically, the following measures are taken to ensure the stable operation of the PCIe link in the PCIe turbo mode running phase, including:

[0130] (1) Real-time monitoring and adaptive adjustment: during the operation of the PCIe link at the determined turbo speed, the link state is continuously monitored in real time. Because there may be various interference factors in the actual running environment or the fluctuation of hardware performance over time, once it is monitored that the link quality shows a downward trend (for example, the data transmission quality does not meet the first level requirement but meets the second level requirement according to the parameters such as the start of the rising of the bit error rate and the aggravation of the signal jitter), an adaptive adjustment mechanism is used to slightly reduce the turbo speed (i.e., by a small step size, such as 0.5 GT / s), and a round of light equalization operation is re-executed to maintain the reliable operation of the link and avoid serious situations such as link interruption.

[0131] (2) Error handling and recovery mechanism: if a serious error occurs during the operation at the turbo speed (such as continuous occurrence of multiple data frame errors, link lock loss, etc., and the data transmission quality does not meet the second level requirement but meets the third level requirement), a perfect error handling and recovery mechanism is used to solve the problem. It includes: first, try to quickly rollback the turbo speed to the last stable operation at a lower turbo speed value, and then restart the complete equalization process to try to restore the normal operation of the link; if multiple attempts still cannot restore (the data transmission quality does not meet the third level requirement), further reduce the speed or even close the PCIe turbo mode, restore to the regular link operation mode, and report the corresponding error information to the system for subsequent troubleshooting and repair operations.

[0132] In one embodiment of the present application, a configuration and management interface can be set up, for example, to set user configurable options, to provide certain configuration rights for users or system administrators, to allow users to adjust parameters related to PCIe turbo mode according to specific application requirements and hardware conditions in actual applications. For example, a switch option for enabling or disabling turbo mode, initial value setting and adjustment of maximum turbo rate, and increase step (not necessarily 1 GT / s) of turbo rate after each successful equalization can be set, and these configurable functions can be realized through a BIOS setting interface or a special system configuration tool to improve the flexibility of starting PCIe high-speed mode.

[0133] Compared with the prior art, the technical solution mainly solves the following technical problems:

[0134] (1) The technical solution provides a method for implementing PCIe turbo mode (Turbo transmission mode), and correspondingly designs an equalization algorithm implementation scheme, which can stably and reliably attempt a higher PCIe transmission rate and improve the utilization mode of SerDes rate;

[0135] (2) Fixed equalization adjustment step: the technical solution uses a self-definable adjustment step, which can make more precise adjustments according to changes in the actual environment, thereby improving the equalization effect;

[0136] (3) The flexible equalization adjustment strategy can ensure the stability of data transmission: the technical solution uses a real-time monitoring and adaptive adjustment mechanism when adjusting the data transmission rate, which can adjust on the premise of ensuring the stability of data transmission, and exit the Turbo mode in time when the transmission is unstable, and restore the conservative transmission speed, thereby avoiding the problem of data transmission failure;

[0137] (4) Configuration flexibility: the technical solution provides configurable options for users to adjust parameters related to Turbo mode according to specific application requirements and hardware conditions, thereby improving the flexibility and operability of the system.

[0138] In one embodiment of the present application, a data transmission method is provided, which is based on the equalization technology-based PCIe turbo mode implementation method according to any one of the above embodiments.

[0139] In one embodiment of the present application, a data transmission system is provided, which is based on the equalization technology-based PCIe turbo mode implementation method according to any one of the above embodiments.

[0140] It should be noted that the data transmission method and the data transmission system provided by the present application have the same inventive concept as the PCIe superspeed mode implementation method based on the equalization technology, and the contents of the PCIe superspeed mode implementation method based on the equalization technology are incorporated into the data transmission method and the data transmission system by introduction.

[0141] The technical solution provided by the present application can be widely applied in the fields of high-speed data transmission, computer hardware, signal processing, etc. In the field of data centers, it can accelerate data transmission between servers and storage devices and optimize virtualization environments. In the field of high-performance computing, it can help cluster computing and accelerator cards to run efficiently and improve computing efficiency. In the field of consumer electronics, it can provide fast connections for high-end computers and smart home appliances, and improve user experience. In the field of communication equipment, it can enhance the connection between 5G base stations and core networks and the internal communication of network equipment, and improve network performance.

[0142] Especially important is that the technical solution has a downward compatible feature, can perfectly adapt to the standard version PCIe, and expands performance on the basis of fully utilizing the existing PCIe ecosystem, which makes it more convenient to deploy in various fields and plays an important role in data transmission, device interconnection, etc., and has great application value and development potential. In general, with the development of technologies such as big data, cloud computing, and artificial intelligence, the demand for high-speed data transmission is increasing, and the technical solution has a significant advantage in improving data transmission speed and stability, and has a broad market demand.

[0143] It should be noted that in this document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0144] The above description is only a specific implementation of the present application, and it should be noted that for ordinary skilled persons in the technical field, without departing from the principles of the present application, a number of improvements and refinements can be made, and these improvements and refinements should be considered as the protection scope of the present application.

Claims

1. A method for implementing PCIe overspeed mode, characterized in that: The following steps are involved: Determining whether the current link state of the PCIe link supports the PCIe overspeed mode according to the link state requirement of the PCIe link corresponding to the preset PCIe overspeed mode; Determining whether the current PCIe link hardware information supports the PCIe overspeed mode based on the hardware information requirements of the PCIe link corresponding to the preset PCIe overspeed mode; If both the link status and the hardware information support PCIe overspeed mode, the PCIe overspeed mode is enabled in the following manner: Obtaining a pre-stored maximum overspeed rate and determining whether a pre-stored historical failure rate exists; if the historical failure rate does not exist, increasing the current rate of the PCIe link according to a preset first step length, and performing a balancing operation each time and after each increase in the current rate to bring the PCIe link rate to the maximum overspeed rate; If there is a pre-stored historical failure rate, and the historical failure rate is greater than the maximum overspeed rate, then determining a second overspeed rate: the second overspeed rate = the historical failure rate - the third step length, where the third step length is smaller than the first step length; Increasing the current rate of the PCIe link according to a preset first step length, and performing a balancing operation each time before or after increasing the current rate, so that the rate of the PCIe link reaches the maximum overspeed rate; If the PCIe link is stably running at the maximum overspeed rate, the current rate of the PCIe link is increased using a third step size, and an equalization operation is performed each time / after the current rate is increased to make the rate of the PCIe link reach the second overspeed rate.

2. The method for implementing PCIe overspeed mode according to claim 1, wherein: Enable PCIe overspeed mode, also includes: If there is a pre-stored historical failure rate, and the historical failure rate is not greater than the maximum overspeed rate, then determining a first overspeed rate: first overspeed rate = historical failure rate - first step length; Increasing the current rate of the PCIe link according to a preset first step length and performing a balancing operation so that the rate of the PCIe link reaches the first overspeed rate; If the PCIe link is stably operating at the first overspeed rate, a second step size is used to increase the current rate of the PCIe link, and an equalization operation is performed each time / after the current rate is increased so that the rate of the PCIe link reaches the maximum overspeed rate, and the second step size is smaller than the first step size.

3. The method for implementing PCIe overspeed mode according to claim 1, wherein: Starting the PCIe overspeed mode also includes: performing an equalization operation each time the current rate of the PCIe link is updated according to a preset first step length, and if equalization fails, reducing the current rate of the PCIe link according to the preset first step length and performing an equalization operation until equalization succeeds; and / or, The first step length is a fixed value or a variable value. If the first step length is a variable value, then during the process of starting the PCIe overspeed mode, the closer the rate of the PCIe link is to the maximum overspeed rate, the smaller the first step length is.

4. The method for implementing PCIe overspeed mode according to claim 3, wherein: Also includes: According to the preset first step length, the current rate of the PCIe link is reduced and an equalization operation is performed until the equalization is successful, and the current rate corresponding to the successful equalization is determined to be the maximum overspeed rate, and the maximum overspeed rate is stored.

5. The method for implementing PCIe overspeed mode according to claim 3, wherein: After a balancing failure occurs, the current rate of the PCIe link is reduced according to the preset first step length and the balancing operation is performed until the balancing is successful. The rate corresponding to the first equalization failure during the current startup of the PCIe overspeed mode is determined as the historical failure rate, or the rate corresponding to the last equalization failure during the current startup of the PCIe overspeed mode is determined as the historical failure rate.

6. The method for implementing PCIe overspeed mode according to claim 1, wherein: After the PCIe overspeed mode is enabled, if the PCIe link is stably operating at the maximum overspeed rate, the following steps are performed: Then, the current rate of the PCIe link is increased according to a preset fourth step length, wherein the fourth step length is smaller than the first step length; And each time the current rate is increased, a balancing operation is performed until a balancing failure occurs or the current rate of the PCIe link reaches a preset overspeed rate threshold, and the overspeed rate threshold is greater than the maximum overspeed rate.

7. The method for implementing PCIe overspeed mode according to claim 1, wherein: The maximum overspeed rate is the upper limit rate at which the PCIe link can achieve stable operation in the previous PCIe overspeed mode; or The maximum overdrive rate is the upper limit rate for stable operation in overdrive mode based on software and hardware predictions of the PCIe link; or, The maximum overspeed rate is determined according to the following calculation formula: V Turbo =(1+α)V1, where V Turbo represents the maximum overspeed rate, V1 represents the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link, 0<α<1; or, The first step length corresponds to the maximum overspeed rate, and the greater the maximum overspeed rate, the greater the first step length; or, The difference between the maximum overspeed rate and the standard maximum rate corresponding to the highest generation PCIe supported by the PCIe link is determined, and the first step length corresponds to the difference. The larger the difference, the larger the first step length.

8. The method for implementing PCIe overspeed mode according to claim 1, wherein: Whether the link status of the PCIe link supports the PCIe overspeed mode is determined by: Determine the highest PCIe generation supported by the PCIe link, assuming that the PCIe link supports the Kth PCIe generation, where K is 2, 3, 4, 5, or 6; If the current rate of the PCIe link is the standard maximum rate corresponding to the Kth generation PCIe and the bit error rate is lower than the preset bit error rate threshold, it is determined that the link state of the PCIe link supports the PCIe overspeed mode.

9. The method for implementing PCIe overspeed mode according to claim 8, wherein: If the PCIe link supports a maximum rate of not less than PCIe Gen 5 and the current rate of the PCIe link does not reach the standard maximum rate corresponding to PCIe Gen 5, determining whether the PCIe link supports cross-level balancing; If the PCIe link supports cross-level balancing, the current rate of the PCIe link is increased to the standard maximum rate corresponding to the fifth generation PCIe, and a balancing operation is performed; If the PCIe link does not support cross-level balancing, the current rate of the PCIe link is gradually increased to the standard maximum rate corresponding to the 5th generation PCIe, and a balancing operation is performed each time / after the rate of the PCIe link is increased.

10. The method for implementing PCIe overspeed mode according to claim 9, wherein: If the PCIe link supports a maximum rate of not less than PCIe Gen 5 and the current rate of the PCIe link reaches the standard maximum rate corresponding to PCIe Gen 5, then the current rate of the PCIe link is increased to the standard maximum rate corresponding to PCIe Gen 6, and a balancing operation is performed; If the balancing is successful, determining whether the PCIe link supports PCIe overspeed mode, and if so, enabling PCIe overspeed mode, otherwise maintaining the current operating state of the PCIe link; If balancing fails, the current rate of the PCIe link is reduced so that the PCIe link can stably operate at the standard maximum rate corresponding to the 5th generation PCIe, and it is determined whether the PCIe link supports up to the 5th generation PCIe. If so, it is determined whether the PCIe link supports PCIe overspeed mode. If so, the PCIe overspeed mode is turned on. Otherwise, the PCIe link maintains the current operating state.

11. The method for implementing PCIe overspeed mode according to claim 1, wherein: Whether the hardware information of the PCIe link supports the PCIe overspeed mode is determined by: If the hardware supports the PCIe overspeed mode and the operating state of the hardware also supports the PCIe overspeed mode, determining that the hardware information of the PCIe link supports the PCIe overspeed mode; The fact that the working state of the hardware also supports the PCIe overspeed mode includes: the power of the hardware is lower than a preset power threshold, and the temperature of the hardware is lower than a preset temperature threshold.

12. The method for implementing PCIe overspeed mode according to claim 1, wherein: After achieving PCIe OverSpeed ​​mode, the following steps are also required to maintain PCIe OverSpeed ​​mode: Monitor the link status of the PCIe link and evaluate the current data transmission quality based on the link status, which also includes signal jitter; If the data transmission quality does not meet the preset first level requirement but meets the preset second level requirement, reducing the current rate of the PCIe link according to a preset fifth step length and performing a balancing operation, wherein the fifth step length is smaller than the first step length; If the data transmission quality does not meet the preset second level requirement but meets the preset third level requirement, the current rate of the PCIe link is reduced to the rate corresponding to the last stable operation and a balancing operation is performed; If the data transmission quality does not meet the preset third level requirement, turning off the PCIe overspeed mode and performing a balancing operation; The first level requirement, the second level requirement and the third level requirement have decreasing requirements on data transmission quality.

13. A data transmission method, characterized in that: Data transmission is performed based on the PCIe super speed mode implementation method according to any one of claims 1 to 12.

14. A data transmission system, characterized in that: The data transmission system performs data transmission based on the PCIe super speed mode implementation method according to any one of claims 1 to 12.

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