Wafer yield analysis method and device

Abstract

The invention discloses a wafer yield analysis method and device, and belongs to the technical field of semiconductor quality detection, and the method comprises the following steps: obtaining wafer defect data which comprises defect quantification data of each minimum segmentation unit on a wafer; wafer test data are obtained, and the wafer test data comprise electrical performance parameters corresponding to each test unit; according to the wafer defect data and the wafer test data, training a deep learning neural network to obtain a wafer defect prediction model; predicting a defect threshold value in the current tape-out step according to the wafer defect prediction model; and when the number of certain defects exceeds a defect threshold value, triggering a reworking process. According to the method, the deep learning neural network is trained through the defect quantification data and the corresponding wafer test data to obtain the mapping relation between the wafer defects and the electrical properties, so that the types of the wafer defects are associated with the wafer yield, the wafer yield is fed back to the corresponding tape-out step, and real-time monitoring of the process is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor quality detection, and particularly relates to a wafer yield analysis method and device. BACKGROUND

[0002] The silicon carbide MOSFET is a high-performance power device based on a wide-bandgap semiconductor material, has high voltage resistance (breakdown field strength up to 3 MV / cm), high temperature stability (>200℃), low conduction loss and high frequency switching capability, and is widely used in new energy vehicles, photovoltaic inverters and other high-power scenes.

[0003] From the preparation cost of the silicon carbide MOSFET, the yield of the silicon carbide substrate and the epitaxy is a relatively key index, which determines the production cost of the device and also has an important influence on the product quality and reliability.

[0004] For example, the patent with the publication number CN116106691A discloses a wafer yield early failure model modeling method and a wafer yield early failure detection method, and the steps include: providing a wafer to be tested; establishing a test layout on the wafer to be tested, the test layout including a plurality of test devices; using a plurality of different test voltages to perform online failure testing on the test devices, and obtaining the device cumulative failure rate corresponding to each test voltage; obtaining an initial model; fitting the initial model, and obtaining an early failure model through each test voltage and the device cumulative failure rate. A wafer yield early failure detection method includes: providing a wafer to be tested, the wafer to be tested including a plurality of test devices, and providing a maximum cumulative failure rate; obtaining an early failure model; obtaining a cumulative failure rate threshold according to the maximum cumulative failure rate; obtaining a screening voltage based on the early failure model and the cumulative failure rate threshold; and performing online failure testing using the screening voltage. The early failure testing efficiency is improved, and the accuracy of screening defective products is increased.

[0005] However, the total number of defects of the silicon carbide substrate is relatively large, and each defect has different influences on the performance of the device. For example, due to the high-temperature environment for growing the silicon carbide substrate, the complex composition of the epitaxy and the high-stress environment in the polishing process, the wafer epitaxial defect density is usually 1-2 orders of magnitude higher than that of silicon, such as basal plane dislocation (BPD) and carrot defect. In the subsequent high-energy ion implantation process specific to the silicon carbide wafer, a large number of lattice damages are caused, and part of the damages are difficult to repair through subsequent high-temperature annealing, forming implantation defects. In wafer flow, particle defects such as surface particles, missing, and line break are introduced. These particle defects affect the performance of the device, for example, causing the source-drain current and gate-drain current to surge, and the on-resistance to abnormally rise, directly threatening the wafer yield.

[0006] Therefore, it is urgent to develop a wafer yield analysis method and device to solve the problems in the prior art. SUMMARY

[0007] The present application aims to provide a wafer yield analysis method and device, which trains a deep learning neural network with defect quantification data and corresponding wafer test data to obtain the mapping relationship between various wafer defects and electrical properties, so as to solve the problem that the existing model cannot reflect the yield to the corresponding wafer step.

[0008] To solve the above technical problems, the specific technical solutions of the present application are as follows:

[0009] A wafer yield analysis method, comprising the following steps:

[0010] Obtaining wafer defect data, wherein the wafer defect data includes defect quantification data of each minimum partition unit on the wafer at least one wafer step, and the defect quantification data includes epitaxial defect data, implantation defect data and particle defect data;

[0011] Obtaining wafer test data, wherein the wafer test data includes electrical performance parameters corresponding to each test unit after completing all wafer steps; one test unit includes at least one minimum partition unit;

[0012] Training a deep learning neural network according to the wafer defect data and the wafer test data to obtain a wafer defect prediction model;

[0013] According to the wafer defect prediction model, predicting the defect threshold value at the current wafer step; when the number of a certain defect exceeds the defect threshold value, triggering the rework process.

[0014] Further, the epitaxial defect data includes the number of multiple epitaxial defects;

[0015] The implantation defect data includes implantation damage defects caused by high-energy particle implantation;

[0016] The particle defect data includes the number of multiple particle defects.

[0017] Further, the epitaxial defects are jointly judged by the shape features of the optical spectrum and the characteristic peaks of the PL spectrum;

[0018] The implantation damage defects are quantified by the half-width of the characteristic peaks of the Raman spectrum;

[0019] The particle defects are judged by the bright field image and the dark field image of the optical spectrum.

[0020] Further, the epitaxial defects, implantation damage defects and particle defects are collected by a multi-spectrum imaging unit, wherein the multi-spectrum imaging unit comprises an integrated laser spectrometer, a photoluminescence imaging module and a Raman imaging module.

[0021] Further, the defect quantification data of the test unit is obtained by process defect IDs of minimum segmentation units contained in the test unit, wherein the process defect IDs comprise wafer numbers and coordinate information of the minimum segmentation units, types and quantities of various epitaxial defects, types and quantities of various implantation defects and types and quantities of various particle defects.

[0022] Further, the division scale of the minimum segmentation units is divided according to the minimum test accuracy of the test spectrum instrument and the required test speed.

[0023] Further, the training of the deep learning neural network according to the wafer defect data and the wafer test data comprises the following steps:

[0024] According to the defect quantification data and the wafer test data, a wafer defect feature matrix and an electrical performance target matrix are constructed, wherein the wafer defect feature matrix comprises an epitaxial defect feature matrix, an implantation defect feature matrix and a particle defect feature matrix.

[0025] According to the wafer defect feature matrix and the electrical performance target matrix, a data set is constructed.

[0026] The deep learning neural network is trained by the data set to obtain a wafer defect prediction model.

[0027] Further, the deep learning neural network is a fully connected feedforward neural network, and the network architecture of the fully connected feedforward neural network is in the form of a multi-layer perceptron, comprising an input layer, a plurality of hidden layers and an output layer.

[0028] The hidden layers adopt a Mish activation function, and a Dropout regularization mechanism is introduced between the hidden layers.

[0029] The output layer adopts a linear activation function, and a mean square error is used as a loss function.

[0030] A computer device comprises a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to realize the steps of the method.

[0031] A computer program product comprises a computer program, and the computer program is executed by a processor to realize the steps of the method.

[0032] The present application has the following advantages:

[0033] (1) The application trains a deep learning neural network by using three kinds of defect quantification data, i.e., epitaxial defect data, implantation defect data and particle defect data, and corresponding wafer test data, to obtain the mapping relationship between wafer defects and electrical performance in each tape-out step, thereby associating the types of wafer defects with wafer yield, and realizing the feedback of wafer yield to the corresponding tape-out step, which helps to improve wafer yield.

[0034] (2) The application quantifies epitaxial defects, implantation damage defects and particle defects by means of optical spectrum, PL spectrum and Raman spectrum, which helps the deep learning neural network to obtain the mapping relationship between wafer defects and electrical performance in each tape-out step, effectively identifies the influence of multiple defects on device electrical performance, and realizes high-precision prediction of wafer-level yield and real-time monitoring of process.

[0035] (3) The Mish activation function is used in the hidden layer of the model of the application to enhance the nonlinear fitting ability and gradient propagation efficiency of the model; at the same time, the Dropout regularization technology is introduced to randomly shield part of the neuron connection in the training process to prevent model overfitting and improve the generalization performance. The linear activation function is used in the output layer to realize simultaneous regression prediction of multiple electrical parameters. Finally, the network weight is optimized by the back propagation algorithm to minimize the mean square error (MSE) between the predicted electrical parameters and the measured values, and the training of the wafer defect prediction model is completed. The trained wafer defect prediction model can consider the coupling relationship between multiple defect modes and multiple dimensional electrical indicators, the deviation between the defect prediction value and the measured value is less than 10%, and the end-to-end accurate prediction from defect features to device performance degradation is realized, which provides data-driven support for process optimization and yield improvement.

[0036] (4) The application introduces a minimum segmentation unit, gives a process defect ID to the minimum segmentation unit, and the process defect ID monitors all defect change information, so that the minimum segmentation unit realizes the free regulation of process monitoring efficiency and accuracy.

[0037] Other features and advantages of the application will be disclosed in detail in the following specific embodiments and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 The flowchart of the application is shown in the figure;

[0039] Figure 2 The overall flowchart of the application is shown in the figure;

[0040] Figure 3 The schematic diagram of several minimum segmentation units of the application is shown in the figure;

[0041] Figure 4 The Raman spectrum of 4H-SiC before and after ion implantation is shown in the figure;

[0042] Figure 5 Process defect ID schematic diagram for test unit

[0043] Figure 6 SiC wafer gate breakdown field wafer mapping test result schematic diagram

[0044] Figure 7 SiC wafer test unit multi-dimensional defect and multi-dimensional electrical performance parameter schematic diagram

[0045] Figure 8 SiC wafer test unit surface particle defect and gate oxide E OX Actual data and model prediction data schematic diagram

[0046] Figure 9 SiC packaged device failure analysis-device defect number extraction schematic diagram

[0047] Figure 10 Defect assignment on minimum segmentation unit schematic diagram DETAILED DESCRIPTION

[0048] In order to better understand the purpose, structure and function of the present application, the present application will be further described in detail below in combination with the drawings.

[0049] A wafer yield analysis method, as shown in Figure 1 and Figure 2 , includes the following steps:

[0050] Obtain wafer defect data, wherein the wafer defect data includes defect quantization data of each minimum segmentation unit on the wafer at least one tape-out step, and the defect quantization data includes epitaxial defect data, implantation defect data and particle defect data;

[0051] Obtain wafer test data, wherein the wafer test data includes electrical performance parameters corresponding to each test unit after all tape-out steps are completed; one test unit includes at least one minimum segmentation unit;

[0052] According to the wafer defect data and the wafer test data, a deep learning neural network is trained to obtain a wafer defect prediction model to obtain a mapping relationship between wafer defects and electrical performance;

[0053] According to the wafer defect prediction model, defect threshold data at the current tape-out step is predicted; when the number of a certain defect exceeds the defect threshold, a rework process is triggered.

[0054] This application trains a deep learning neural network through the defect quantification data during the tape-out step and the corresponding electrical performance parameters to obtain a mapping relationship between wafer defects and electrical performance during different tape-out steps, thereby associating the type of wafer defects with the wafer yield, and realizing the feedback of the wafer yield to the corresponding tape-out step to improve the wafer yield.

[0055] In this embodiment, the test unit includes a PIN transistor, an SBD device, a planar MOSFET, a trench MOSFET or a fin-type FinFET. Figure 3 As shown, in this embodiment, a test unit includes 25 minimum division units. The minimum division units are divided according to the trade-off between the minimum test accuracy and the required test speed of the test spectrometer. In this embodiment, the minimum division units can be 1μm×1μm or 2μm×2μm.

[0056] In this embodiment, the wafer tape-out process consists of three steps. The defect quantification data, corresponding to the tape-out steps, includes epitaxial defect data, implanted defect data, and particle defect data, all collected by a multispectral imaging unit. The multispectral imaging unit includes an integrated laser spectrometer, a photoluminescence (PL) imaging module, and a Raman imaging module, which are used to sequentially collect wafer surface optical features, PL signals, and Raman scattering signals.

[0057] The epitaxial defect data includes the number of various epitaxial defects. In this embodiment, the epitaxial defects include: epitaxial contaminant particles (Epi Particles), surface pits (Pit) caused by chemical mechanical polishing over-etching, surface bumps (Bumps), scratches (ScratchTrace), pitted white etching defects (PL_White), micropipes (Micropipes), basal plane dislocations (BPDs), stacking faults (Stacking Faults), extended stacking faults (Propagated SFs), carrot defects (Carrots), dark field defects (DFs), complexes of DF defects and triangular structures (DF_Triangles), photoluminescent stacking faults (PL_SFs), and triangular defects (Triangles) caused by metal impurity segregation. In other words, the epitaxial defect data represents the number of the above 14 types of epitaxial defects.

[0058] In this embodiment, the epitaxial defects of the silicon carbide wafer are identified by PL spectroscopy and optical spectra. For example, a carrot defect has a characteristic shape similar to a carrot in the optical spectra and characteristic peaks around 480nm and 620nm in the PL spectrum.

[0059] Specifically, judging epitaxial defects by PL spectra and optical maps is a prior art and will not be described in detail in this application.

[0060] The injection defect data includes one or more defects generated during the injection, such as Figure 4 As shown in the embodiment, the injection defect includes an injection damage defect caused by high-energy particle injection, which is quantified by the half-height width of the characteristic peak of the Raman spectrum. Specifically, the injection damage defect caused by high-energy particle injection of silicon carbide is determined by the 4H-SiC Raman spectrum before and after injection, and the size of the lattice damage is quantified by the half-height width (Full Width at Half Maximum, FHWM) difference of the 4H-SiC Al(LO) longitudinal optical phonon peak at 777 cm -1 2.7 is Z 2, Thus, 3.6 is Z 11 .

[0061] The present application divides the half-height width difference of the Raman spectrum characteristic peak before and after high-energy particle injection into grades and counts the number of each grade, which is input into the deep learning neural network as different injection damage defects, which helps the deep learning neural network to obtain the mapping relationship between the injection damage defects and the electrical performance, and improves the prediction accuracy of the model.

[0062] The particle defect data includes the number of various particle defects. In the embodiment, the particle defects include: surface contamination (Strain), scratch (Scratch), surface particle (Surface Particle), missing (Missing), line break (Line Break), overlay (Overlay), PR peeling (PR Peeling), crack (Crack), and bridge (Bridge).

[0063] The particle defects are obtained by bright field and dark field images of the optical map.

[0064] For example, the surface particle bright field (BF) is a dark irregular spot with clear edges, and the size is >0.5 μm. The dark field (DF) is a high-light spot, and the small particles (<0.5 μm) are more obvious in the dark field. The position is randomly distributed and may be attached to the line or the blank area.

[0065] Specifically, the particle defect is determined by the bright field and dark field images of the optical map, which is a prior art and will not be described here.

[0066] As shown in the embodiment, specifically, the wafer flow step and the acquisition of the defect quantification data include the following steps: Figure 2 As shown in the embodiment, specifically, the wafer flow step and the acquisition of the defect quantification data include the following steps:

[0067] Step S11: Standard RCA cleaning is performed on the SiC epitaxial wafer to remove polishing chemical residues and contamination.

[0068] Step S12: The minimum partition unit is divided into 2 μm x 2 μm, and the SiC wafer analyzer is used to identify the epitaxial defects of the SiC epitaxial wafer through optical microscopy and photoluminescence spectrum.

[0069] Step S13: The epitaxial defects are coded to obtain epitaxial defect information; for example, W1 is an epitaxial particle (Epi Particle), W2 is a carrot defect (Carrot), W3 is a surface pit formed by over-etching during chemical mechanical polishing (Pit), W4 is a surface bump defect (Bump), W5 is a point-like white etching defect (PL_White), W6 is a micropipe (Micropipe), W7 is a basal plane dislocation (BPD), and W8 is a stacking fault (Stacking Fault), etc. As shown in FIG. 1, J-1 indicates the first time of epitaxial defect monitoring, and W7 indicates that a basal plane dislocation (BPD) is found. Figure 5

[0070] Step S21: Mask growth and ion implantation are performed on the wafer.

[0071] Step S22: The implant damage defects caused by high-energy particle implantation of SiC are determined by 4H-SiC Raman spectrum before and after implantation, and the size of the lattice damage is determined by the full width at half maximum (FHWM) of the 777 cm -1 peak of 4H-SiC Al(LO) longitudinal optical phonon. The 4H-SiC initial half-width is divided into grades, 2.5 is Z0, 2.6 is Z1, and 3.6 is Z11, to obtain implantation defect data.

[0072] Step S31: After completing the Raman spectrum, the wafer after defect testing is subjected to RCA cleaning, and the SiC is subjected to one-time sacrificial oxidation, and then the surface silicon oxide layer is removed using HF, and a 50 nm or so oxide layer is grown using a standard thermal oxidation process.

[0073] Step S32: The SiC oxidized wafer is subjected to NO or N2O annealing, the annealing time is 60 min, and the annealing temperature is 1000°C-1400°C.

[0074] Step S33: The SiC oxidized wafer is subjected to low-pressure chemical vapor deposition of polysilicon gate and phosphorus annealing, and the polysilicon after annealing is subjected to photolithography and first-time particle detection.

[0075] Step S34: Etching and forming a polysilicon gate, and second-time particle detection after cleaning.

[0076] ​Step S34: low pressure chemical vapor deposition is used to deposit an insulating dielectric layer forming the gate, source, and drain.

[0077] Step S35: perform ohmic contact lithography and perform the third particle detection; perform metal deposition after opening the hole; and perform the fourth particle detection.

[0078] Step S36: perform gate opening photolithography and the fifth particle detection; and etch the gate opening.

[0079] Step S37: forming gate metal by evaporating Ti / Al, and performing the sixth particle detection after cleaning.

[0080] Step S38: BOE etching is performed on the back of the silicon carbide wafer to remove the polycrystalline on the back, and then magnetron sputtering is performed on the back to sputter metal nickel. Annealing is performed in a rapid annealing device with inert gas internal annealing at a temperature of 950°C for 5 minutes to complete the production of all standard test structures.

[0081] Step S39: Encode the particle defects to obtain particle defect data. For example, L1 is surface contamination (Strain), L2 is surface particles (Surface Particle), L3 is missing focus (Missing), L4 is scratch (Scratch), L5 is line break (Line Break), L6 is offset (Overlay), L7 is crack (Crack), L8 is bridge (Bridge). Figure 5 As shown in the figure, K-1 represents the first particle monitoring, L2 represents the discovery of surface particle defects, KN ​​represents the Nth particle monitoring, and there is an L4 scratch inside the minimum segmentation unit.

[0082] like Figure 10 As shown in the figure, it is a schematic diagram of assigning values ​​to particle defects on multiple minimum division units. First, the defect type is determined. If it is a surface particle L2, if there is L2 inside the minimum division unit, it is directly assigned to L2. The place without defects is assigned to 0. Figure 10 The defect size is quantified.

[0083] In this embodiment, the particle detection method includes using linear laser scanning to quickly complete a rapid surface scan of the silicon carbide wafer, using an adaptive algorithm to complete image stitching of different areas of the silicon carbide wafer, and using a GNN image neural network to identify the type and area of ​​particles on the wafer. Specifically, this particle detection method is existing technology and will not be further described in this application.

[0084] In this embodiment, the electrical performance parameters include various parameters used to determine device performance. In this embodiment, they include: threshold voltage (V THThreshold voltage), breakdown electric field (BV, Breakdown Voltage), source leakage current (I DS Drain to source leakages), on-resistance (R ON , ON Resistance), gate breakdown electric field (Eox, Oxide Breakdown Electric Field), gate leakage current (I GS , Gate to source leakages). Optionally, the electrical performance parameter may also be one or more parameters for measuring semiconductor devices to be manufactured on the wafer.

[0085] Alternatively, the electrical performance parameters may be obtained by testing capacitors of different areas, MOSFET devices of different designs, PIN transistors of different designs, and / or SBD transistors of different designs. Alternatively, the electrical performance parameters may also be obtained by testing semiconductor devices to be fabricated on the wafer.

[0086] Specifically, after all the tape-out steps are completed, the acquisition of the wafer test data includes the following steps:

[0087] Step S41: Calculate the locations of devices on the wafer based on the test unit layout design, set the power analysis wafer mapping scanning program, and calibrate the power analyzer;

[0088] Step S42: Perform CV test of 1k-1M high and low frequency on the silicon carbide oxidation test capacitor; perform transfer, output and breakdown test on the silicon carbide MOSFET test unit to extract the threshold voltage (V TH , Threshold voltage), breakdown electric field (BV, Breakdown Voltage), source leakage current (I DS , Drain to source leakages), on-resistance (R ON , ON Resistance), gate breakdown electric field (Eox, Oxide Breakdown Electric Field), gate leakage current (I GS , Gate to source leakages); perform a breakdown voltage test on the capacitor with a maximum voltage of 100V, a current limit of 1mA, and a step size of 0.1V.

[0089] Among them, the oxide layer thickness T OX The formula is as follows:

[0090] ;

[0091] The breakdown voltage Eox is calculated as follows:

[0092] ;

[0093] The oxide layer thickness formula and the breakdown voltage formula are prior art, and will not be described herein.

[0094] As shown in FIG. 3, it is a wafer mapping test result of the gate breakdown electric field (Eox, Oxide Breakdown Electric Field). Figure 6

[0095] In this embodiment, the deep learning neural network is a fully connected feedforward neural network, and the training of the deep learning neural network according to the defect quantification data and the wafer test data includes the following steps:

[0096] According to the defect quantification data and the wafer test data, a plurality of wafer defect feature matrices and electrical performance target matrices corresponding to the wafer defect feature matrices are constructed; wherein the wafer defect feature matrices include an epitaxial defect feature matrix, an implantation defect feature matrix, and a particle defect feature matrix.

[0097] According to the plurality of wafer defect feature matrices and the electrical performance target matrices, a data set is constructed; optionally, the data set includes a training set and a test set.

[0098] The fully connected feedforward neural network is trained through the data set to obtain a wafer defect prediction model.

[0099] The construction of the wafer defect feature matrix includes the following steps:

[0100] According to the epitaxial defect data of each test unit, an epitaxial defect feature matrix is constructed.

[0101] According to the implantation defect data of each test unit, an implantation defect feature matrix is constructed.

[0102] According to the particle defect data of each test unit, a particle defect feature matrix is constructed.

[0103] The epitaxial defect feature matrix takes a test unit as a basic unit, each row represents a test unit, and each column corresponds to a quantification characteristic parameter of an epitaxial defect, forming a structure for input into a feature space. The construction method of the implantation defect feature matrix and the particle defect feature matrix is the same as that of the epitaxial defect feature matrix, and will not be described herein.

[0104] The construction of the electrical performance target matrix includes the following steps: ​

[0105] According to the electrical performance parameters of each test unit, a corresponding electrical performance target matrix is constructed.

[0106] The matrix is used to characterize the actual electrical behavior of the device as a supervision signal in subsequent model training.

[0107] In this embodiment, the construction of the training set and the test set and the training of the fully connected feedforward neural network are prior art, and the present application will not be described again.

[0108] In this embodiment, the training of the deep learning neural network according to the defect quantification data and the wafer test data further includes the following steps:

[0109] According to the test unit layout, the process defect IDs and silicon carbide IDs of all minimum segmentation units contained therein are counted, and the number and distribution of defects are counted; as shown in the figure, there are 3 minimum segmentation units with W7 as the basal plane dislocation (BPD) and 1 W2 as the epitaxial contaminant particle (Epi Particle) inside the test unit. Figure 7

[0110] As shown in the figure, the silicon carbide ID includes a wafer ID and a process defect ID. Figure 5

[0111] Before training the deep learning neural network, it further includes pre-processing the defect quantification data.

[0112] The pre-processing of the defect quantification data includes the following steps:

[0113] For missing data, average value or 0 value filling is adopted, such as 0 filling for null value and undetected defects in BPD data.

[0114] In this embodiment, the network architecture of the fully connected feedforward neural network is in the form of a multilayer perceptron (MLP), including an input layer, multiple hidden layers, and an output layer.

[0115] The number of input layer neurons is equal to the defect feature dimension, and the number of output layer neurons is equal to the target electrical parameter dimension, to realize end-to-end multi-output regression.

[0116] The hidden layer adopts a Mish activation function, and the Mish activation function is as follows:

[0117] Mish(x) = x*tanh(ln(1 + e^x));

[0118] Wherein, x is the input value.

[0119] Compared with the traditional ReLU, Mish has smoothness and self-gating characteristics, which is beneficial to gradient propagation and enhances the model expression ability.​​

[0120] Dropout regularization mechanism is introduced between the hidden layers to randomly mask part of the neuron connections during the training process to prevent overfitting and improve the generalization performance of the model.

[0121] The output layer uses a linear activation function to directly output the continuous electrical parameter prediction value. The mean square error (MSE) is used as the loss function, and the weight parameters are continuously adjusted through back propagation to minimize the deviation between the predicted value and the measured value.

[0122] After training, a wafer defect-performance joint prediction model suitable for this application is obtained, which can jointly consider multiple defect modes (such as particles, pits, dislocations, etc.) and multi-dimensional electrical performance degradation behavior. This model can be applied to early defect data analysis of new batches of wafers to achieve high-precision prediction of key electrical parameters and support process optimization decisions and yield improvement.

[0123] In the hidden layer of this application, the Mish activation function is used to enhance the non-linear fitting ability and gradient propagation efficiency of the model. At the same time, the Dropout regularization technique is introduced to randomly mask part of the neuron connections during the training process to prevent model overfitting and improve the generalization performance. The output layer uses a linear activation function to achieve simultaneous regression prediction of multi-dimensional electrical parameters (V TH , BV, R ON , Eox, etc.). Finally, the network weights are optimized through the back propagation algorithm to minimize the mean square error (MSE) between the predicted electrical parameters and the measured values, completing the training of the wafer defect prediction model. The trained wafer defect prediction model can jointly consider the coupling relationship between multiple defect modes (such as Missing, Particle, Pit, etc.) and multi-dimensional electrical indicators, and the deviation between the defect prediction value and the measured value is less than 10%, achieving end-to-end accurate prediction from defect features to device performance degradation, providing data-driven support for process optimization and yield improvement.

[0124] In this embodiment, the defect quantization data of the test unit is obtained through the process defect ID of the smallest partition unit included in the test unit, and the process defect ID includes: wafer number and coordinate information on the wafer, types and quantities of various epitaxial defects, types and quantities of various implantation defects, and types and quantities of various particle defects.

[0125] The process defect ID is used for failure analysis of packaged devices. For example, as shown in Figure 9 and Figure 10 , for devices that fail early, they belong to a test unit, and the failure analysis includes the following steps:

[0126] extracting all minimum partition units contained in the failed device;

[0127] Through the process defect ID, the defect traceability is performed, and the number distribution of all process flow defects around the failed device and the failed point is counted. If the process defect ID shows that the number of all process flow defects around the failed point is small, the early failure caused by the process defect can be excluded.

[0128] The process defect ID of the device damaged in advance is determined, and the number of all defects in the process flow is counted. The key defects affecting the performance of the device, silicon carbide epitaxial defects, ion implantation defects and particles can be traced, and it is determined whether the device damaged in advance is caused by the process defect, so as to accurately analyze the device failure reason, realize the analysis of the relationship between the multi-dimensional defects and the device failure through the deep learning model, and accelerate the device design iteration to reduce the cost.

[0129] In the embodiment, according to the wafer defect prediction model, the defect threshold data at the current flow step is predicted, and the specific process is as follows:

[0130] The wafer defect prediction model outputs the defect threshold data at the current flow step according to the preset electrical performance parameter for realizing the wafer demand yield.

[0131] The defect quantization data at each flow step is monitored in real time, and when the number of a certain defect exceeds the defect threshold, the rework process is triggered.

[0132] Optionally, the wafer defect prediction model predicts the defect threshold data at the current flow step, and the specific process is as follows:

[0133] The wafer defect prediction model outputs the defect threshold data at the current flow step according to the defect quantization data at the previous flow step and the preset electrical performance parameter for realizing the wafer demand yield.

[0134] Taking the surface particle (Surface Particle) defect as an example, as shown in Figure 8 The actual data and model prediction data of the surface particle (Surface Particle) and the gate oxide layer Eox are shown in the figure, the vertical coordinate is the gate oxide layer Eox unit (MV / cm), and the horizontal coordinate is the number of units, which represents the number of minimum units containing the surface particle in the test unit. The quantization process of the minimum unit to the defect size is shown in Figure 10 The actual data and model prediction data are well fitted, the threshold value of the surface particle (Surface Particle) defect is set to 3000, and if the surface particles in 10% of the area of the test wafer exceed the defect threshold value of the surface particle, the process rework process is triggered.

[0135] A wafer yield analysis device comprising a memory, a processor and a computer program stored on the memory, the processor executing the computer program to implement the steps of the method.

[0136] A computer program product comprising a computer program which, when executed by a processor, implements the steps of the method.

[0137] A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method.

[0138] It can be understood that the present application is described by some embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, under the guidance of the present application, the features and embodiments can be modified to adapt to specific conditions and materials without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of the present application are within the scope of the present application.

[0139] In addition, it should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments which can be understood by those skilled in the art.

Claims

1. A wafer yield analysis method, characterized in that: The steps include: Acquiring wafer defect data, wherein the wafer defect data includes defect quantification data of each minimum division unit on the wafer during at least one tape-out step, and the defect quantification data includes epitaxial defect data, implantation defect data, and particle defect data; Obtaining wafer test data, wherein the wafer test data includes electrical performance parameters corresponding to each test unit after all tape-out steps are completed; each test unit includes at least one minimum division unit; Based on wafer defect data and wafer test data, a deep learning neural network is trained to obtain a wafer defect prediction model; Based on the wafer defect prediction model, the defect threshold of the current tape-out step is predicted; when the number of certain defects exceeds the defect threshold, the rework process is triggered.

2. The wafer yield analysis method according to claim 1, wherein: The epitaxial defect data includes the number of multiple epitaxial defects; The injection defect data includes injection damage defects caused by high-energy particle injection; The particle defect data includes the number of various types of particle defects.

3. The wafer yield analysis method according to claim 2, wherein: The defect quantification data of the test unit is obtained through the process defect ID of the minimum division unit contained in the test unit. The process defect ID includes: the wafer number and coordinate information of the minimum division unit, the type and quantity of various epitaxial defects, the type and quantity of various injection defects, and the type and quantity of various particle defects. The process defect ID is also used in the subsequent failure analysis of the test unit to eliminate premature failure of devices caused by defects.

4. The wafer yield analysis method according to claim 3, wherein: The division scale of the minimum segmentation unit is divided according to a trade-off between the minimum test accuracy and the required test speed of the test spectrum instrument.

5. The wafer yield analysis method according to any one of claims 2 to 4, characterized in that: The epitaxial defects are determined by combining the shape characteristics of the optical spectrum and the characteristic peaks of the PL spectrum; The implantation damage defect is quantified by the half-maximum width of the characteristic peak of the Raman spectrum; The particle defects are determined by bright field images and dark field images of the optical spectrum.

6. The wafer yield analysis method according to claim 5, wherein: The epitaxial defects, implantation damage defects and particle defects are collected by a multi-spectral imaging unit, wherein the multi-spectral imaging unit includes: an integrated laser spectrometer, a photoluminescence imaging module and a Raman imaging module.

7. The wafer yield analysis method according to claim 5, wherein: The training of a deep learning neural network based on wafer defect data and wafer test data includes the following steps: Constructing a wafer defect feature matrix and an electrical performance target matrix based on defect quantification data and wafer test data; wherein the wafer defect feature matrix includes an epitaxial defect feature matrix, an injection defect feature matrix, and a particle defect feature matrix; Construct a data set based on the wafer defect feature matrix and the electrical performance target matrix; The deep learning neural network is trained using the dataset to obtain a wafer defect prediction model.

8. The wafer yield analysis method according to claim 7, wherein: The deep learning neural network is a fully connected feedforward neural network, and the network architecture of the fully connected feedforward neural network is in the form of a multi-layer perceptron, including an input layer, multiple hidden layers and an output layer; The hidden layer uses the Mish activation function, and the Dropout regularization mechanism is introduced between the hidden layers; The output layer uses a linear activation function; the loss function is the mean square error.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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