Method for extracting asynchronous path and constraint based on comprehensive netlist in chip design

Abstract

The invention provides a method for extracting asynchronous paths and constraints based on a comprehensive netlist in chip design. The method comprises the following steps: S1, reading the comprehensive netlist and sdc by using a prime tool; the invention provides a method for extracting asynchronous paths and constraints based on a comprehensive netlist in chip design, and the method comprises the steps: extracting all asynchronous paths of a chip according to the comprehensive netlist and an sdc file, carrying out the integrity check of the asynchronous paths, recognizing the asynchronous paths which are not subjected to cross-clock processing, and generating asynchronous constraints. All asynchronous paths in a chip can be rapidly extracted, the integrity of asynchronous design can be checked, whether asynchronous design calls a cross-clock universal module or not is checked, the asynchronous paths which do not call a common cross-clock module are printed out, developers are prompted to carry out corresponding modification, asynchronous constraints can be directly output, and the development efficiency is improved. The time cost of developers is greatly reduced, the iteration speed is high, and the project progress is not affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design development, and in particular to a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design. BACKGROUND

[0002] In the chip design development process, all timing paths need to be constrained, including synchronous paths and asynchronous paths. Timing constraints are delay constraints that ensure the normal operation of gate-level circuits. Just like cars driving on a highway, the speed and safe distance requirements are necessary to prevent crashes. If the speed is too fast and the distance is too close, a crash is likely to occur. If the speed is too slow and the distance is too large, congestion is likely to occur. Therefore, only appropriate speed and distance requirements can ensure the safety and smoothness of the highway. After the front-end design is completed, a constraint file (English full name: synopsys design constraints, abbreviated as sdc) is output to cooperate with the code for synthesis, and a synthesized netlist that meets the timing requirements is output. However, no asynchronous constraints are applied during the synthesis stage, but static timing analysis tools (such as primetime) are used during the physical implementation stage to perform timing convergence.

[0003] Initially, there were few asynchronous designs in chips, so a synchronizer (two-stage flip-flop) was used to handle asynchronous data transmission to avoid metastability. Moreover, there were only a few tens or hundreds of asynchronous paths, and developers could list the asynchronous paths and output asynchronous constraints.

[0004] However, with the continuous evolution of chip manufacturing processes, more and more modules can be integrated in chips, i.e., the circuit complexity is increasing, and the clock frequency is also increasing, leading to an increase in asynchronous designs. The number of asynchronous processing types and asynchronous paths is also increasing, making it difficult for developers to confirm and requiring a large amount of time and manpower to confirm. Even the lag in asynchronous constraint output can affect project progress.

[0005] Therefore, it is necessary to provide a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design to solve the above technical problems. SUMMARY

[0006] The present application provides a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design, which solves the problem of difficult confirmation for developers, the need for a large amount of time and manpower to confirm, and even the lag in asynchronous constraint output affecting project progress.

[0007] To solve the above technical problems, the present application provides a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design, which includes the following steps:

[0008] S1: reading the synthesized netlist and sdc using the primetime tool;

[0009] S2: Extracting the interactive clock pair by using the check_timing-include clock_crossing command, and processing the real asynchronous clock pair list by script;

[0010] S3: Looping the asynchronous clock pair list, extracting all asynchronous path related information by using the [get_timing_path-from start clock-to end asynchronous clock] command, and printing out the report;

[0011] S4: Reading the asynchronous path list, matching the end register with the common cross-clock module, putting the matched one into the temporary file, and printing the unmatched one into the abnormal asynchronous path list;

[0012] S5: Comparing the start and end clock frequencies of each asynchronous path, setting the asynchronous constraint Set_max_delay 0.5*period-from start register-to end register according to the 0.5 period of the clock with higher frequency, and printing out the asynchronous constraint which can be directly used by the back end.

[0013] Preferably, the design information obtained by reading the synthesized netlist and sdc file by using the primetime tool includes pin information, register, combinational logic and clock information.

[0014] Preferably, the clock_group is set in the sdc between the asynchronous clocks, all interactive clock pairs in the design are extracted by using the check_timing-include clock_crossing command, including synchronous and asynchronous, only the asynchronous clock pairs are reserved, the list of asynchronous clock pairs is output, and each row has only one pair of asynchronous clocks.

[0015] Preferably, the asynchronous clock pair list is looped, the start clock is in front of each row, and the end clock is behind, the timing path under each asynchronous clock pair is extracted by using the get_timing_path-from start clock-to end clock, the start and end registers, clock frequencies and start and end clock names are grabbed, the complete asynchronous path is obtained, and the asynchronous path list is printed out in a certain format.

[0016] Preferably, the asynchronous path list is read, the end register is matched with the common cross-clock module, the matched one is put into the temporary file, the unmatched one is printed into the abnormal asynchronous path list, and is provided to the development for confirmation.

[0017] Preferably, the traversal preserves the matching asynchronous path in a temporary file, compares the start and end clock frequencies of each asynchronous path, and provides the asynchronous constraint by using 0.5 period of the clock with higher frequency as the constraint basis, printing the asynchronous constraint to the asynchronous constraint file line by line, and providing the backend for direct use.

[0018] Preferably, the S4 step further comprises the following steps: S41, identifying the start and end of the asynchronous path; S42, checking the clock frequency of the asynchronous path; S43, generating the asynchronous constraint; S44, providing the list of abnormal paths; S45, ignoring by using the set_false_path command; and S46, checking the cross-clock-domain path by using the report_cdc command.

[0019] Preferably, in the S41 step, the check_timing command extracts all asynchronous paths and records the start and end registers thereof; the get_clocks command is used to obtain the clock information of the start and end registers; the clock frequency of the asynchronous path is compared with the clock frequencies of the start and end registers, and 0.5 period of the clock with higher frequency is determined as the constraint basis.

[0020] Preferably, the path that does not match is ignored by using the set_max_delay command to generate the asynchronous constraint, and the list of paths that do not match is saved to a temporary file for confirmation and modification by the developer.

[0021] Preferably, the start and end clocks of the asynchronous path have a clear asynchronous relationship, the timing check of the path is ignored by using the set_false_path command, and the safety and correctness of the cross-clock-domain path are checked by using the report_cdc command.

[0022] Compared with the related art, the method for extracting the asynchronous path and constraint based on the synthesized netlist in the chip design provided by the present application has the following beneficial effects:

[0023] The application provides a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 A step schematic diagram of the first embodiment of the method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design provided by the application is provided.

[0025] Figure 2 A step schematic diagram of the second embodiment of the method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design provided by the application is provided. DETAILED DESCRIPTION

[0026] The application will be further described below in combination with the drawings and embodiments.

[0027] The first embodiment

[0028] Please refer to Figure 1 , wherein Figure 1 A step schematic diagram of the first embodiment of the method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design provided by the application is provided.

[0029] The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design comprises the following steps:

[0030] S1: reading the synthesized netlist and sdc by using the primetime tool;

[0031] S2: extracting the interactive clock pairs by using the check_timing-include clock_crossng command, and processing the real asynchronous clock pair list by using a script;

[0032] S3: looping the asynchronous clock pair list, extracting all asynchronous path related information by using the [get_timing_path-from start clock-to end asynchronous clock] command, and printing out a report;

[0033] S4: read the asynchronous path list, match the end register with the common cross clock module, match pass put into temporary file, match fail print to the abnormal asynchronous path list;

[0034] S5: compare the start and end clock frequency of each asynchronous path, set the asynchronous constraint Set_max_delay 0.5*period-from start register-to end register according to 0.5 period of the clock with higher frequency, print the asynchronous constraint, which can be directly used by the backend.

[0035] The design information obtained by reading the synthesized netlist and sdc file using the primetime tool includes pin information, registers, combinational logic and clock information.

[0036] The clock_group is set in the sdc, and the check_timing-includeclock_crossing command is used to extract all the interactive clock pairs in the design, including synchronous and asynchronous, only the asynchronous clock pairs are retained, and the list of asynchronous clock pairs is output, each row has only one pair of asynchronous clocks.

[0037] The asynchronous clock pair list is traversed, the start clock is in front of each row, and the end clock is behind, the get_timing_path-from start clock-to end clock is used to extract the timing path under each asynchronous clock pair, the start and end registers, clock frequency, and start and end clock names are extracted, that is, the complete asynchronous path, which is printed in a certain format.

[0038] The asynchronous path list is read, the end register is matched with the common cross clock module, the match pass is put into the temporary file, the match fail is printed to the abnormal asynchronous path list, and the development is confirmed.

[0039] The asynchronous paths saved in the temporary file are traversed, the start and end clock frequency of each asynchronous path is compared, the asynchronous constraint Set_max_delay 0.5*period-from start register-to end register is set according to 0.5 period of the clock with higher frequency, and the asynchronous constraint file is printed row by row, which can be directly used by the backend.

[0040] The path that does not pass the match in step S4 is a problem in the asynchronous design, which needs to be modified, so these asynchronous constraints are not output; after the code is updated in the next version, the new synthesized netlist is used to extract the new version of asynchronous constraint.

[0041] The project reaches a certain stage, and asynchronous processing is required to submit the backend implementation without problems, so the empty asynchronous path list is required to submit the backend implementation.

[0042] The working principle of the method for extracting asynchronous paths and constraints based on a synthesized netlist in the chip design provided by the application is as follows:

[0043] In operation, first, the primetime tool is used to read the synthesized netlist and the sdc file to obtain complete design information, mainly to obtain pin information, registers and clock information.

[0044] Since the clock_group has been set between asynchronous clocks in the sdc, the check_timing-include clock_crossing command can be used to extract all the interactive clock pairs in the design, including synchronous and asynchronous, and a simple processing is required to only keep the asynchronous clock pairs and output the list of asynchronous clock pairs, so as to ensure that each row has only one pair of asynchronous clocks.

[0045] The asynchronous clock pair list is traversed, the start clock is in front of each row, and the end clock is behind each row, the get_timing_path-from start clock-to end clock is used to extract the timing path under each asynchronous clock pair, the start and end registers are captured, the clock frequency is captured, and the start and end clock names are added, that is, the complete asynchronous path, and the asynchronous path list is printed in a certain format.

[0046] The asynchronous path list is read, the end register is matched with the public cross-clock module, the matching is passed to the temporary file, the matching is not passed to the abnormal asynchronous path list, and the development is confirmed.

[0047] The asynchronous paths saved in the temporary file are traversed, the start and end clock frequencies of each asynchronous path are compared, the asynchronous constraint is performed according to 0.5 periods of the clock with the highest frequency, Set_max_delay 0.5*period-from start register-to end register, and each row is printed to the asynchronous constraint file, which can be directly used by the backend.

[0048] Compared with the related art, the method for extracting asynchronous paths and constraints based on a synthesized netlist in the chip design provided by the application has the following beneficial effects:

[0049] The application provides a method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design, extracts all asynchronous paths of a chip according to a synthesized netlist and an sdc file, performs integrity checking on the asynchronous paths, identifies asynchronous paths that are not processed by a cross-clock processing or asynchronous paths that are processed by an incorrect cross-clock module, generates asynchronous constraints, can quickly extract all asynchronous paths in the chip, can perform integrity checking on the asynchronous design, can check whether the asynchronous design calls a cross-clock general module, can print asynchronous paths that do not call a common cross-clock module to prompt a developer to make corresponding modifications, can directly output asynchronous constraints, greatly reduces the time cost of the developer, and has a fast iteration speed and does not affect the project progress.

[0050] Second embodiment

[0051] Please refer to Figure 2 Based on the method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design provided by the first embodiment of the application, the second embodiment of the application provides another method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design. The second embodiment is only a preferred mode of the first embodiment, and the implementation of the second embodiment does not affect the implementation of the first embodiment.

[0052] Specifically, the method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design provided by the second embodiment of the application is different in that the S4 step further includes the following steps: S41: identifying a starting point and an ending point of the asynchronous path; S42: checking a clock frequency of the asynchronous path; S43: generating an asynchronous constraint; S44: providing an abnormal path list; S45: ignoring using a set_false_path command; and S46: checking a cross-clock domain path using a report_cdc command.

[0053] In the S41 step, a check_timing command extracts all asynchronous paths and records starting point and ending point registers thereof; a get_clocks command is used to obtain clock information of the starting point and ending point registers; and the clock frequency of the asynchronous path is compared with the clock frequencies of the starting point and ending point registers, and 0.5 periods of a clock with a higher frequency are determined as a constraint basis.

[0054] The path that does not pass the matching is ignored using a set_false_path command, and a list of the path that does not pass the matching is saved into a temporary file for confirmation and modification by a developer.

[0055] The starting point and ending point clocks of the asynchronous path have a clear asynchronous relationship, the timing checking of the path is ignored using a set_false_path command, and the safety and correctness of the cross-clock domain path are checked using a report_cdc command.

[0056] The working principle of the method for extracting asynchronous paths and constraints based on a comprehensive netlist in chip design provided by the present invention is as follows:

[0057] When working, first use the check_timing command to extract all asynchronous paths and record their start and end registers; use the get_clocks command to obtain the clock information of the start and end registers;

[0058] The clock frequency of the asynchronous path is an important basis for generating constraints. It is necessary to compare the clock frequencies of the start and end registers and determine 0.5 cycles of the higher-frequency clock as the constraint basis. If the frequency of the start clock is and the frequency of the end clock is , the constraint should be based on 0.5 cycles of the higher-frequency clock.

[0059] For paths that fail matching, you can use the set_max_delay command to generate asynchronous constraints. For example, the command is: set_max_delay 0.5*[get_property period-of[get_clocks clk1]]-from[get_registers reg1]-to[get_registers reg2], where clk1 is a clock with a higher frequency, and reg1 and reg2 are the starting and ending registers. This command ensures that the delay of the asynchronous path does not exceed 0.5 cycles, thus avoiding metastability issues.

[0060] Save the list of paths that fail to match to a temporary file for developers to confirm and modify. The command can be: fileput_contents "async_paths.txt"[join$async_paths "\n"]; developers can check the file to confirm whether the paths need to be modified and rerun the synthesis process in subsequent versions to generate new asynchronous constraints.

[0061] If there is a clear asynchronous relationship between the start and end clocks of an asynchronous path, you can use the set_false_path command to ignore the timing check of these paths. The command can be: set_false_path-from[get_clocksclk1]-to[get_clocks clk2]. The command can ensure that the tool does not perform timing analysis on these paths, thereby avoiding unnecessary optimization and errors.

[0062] To ensure the correctness of the asynchronous path, the safety of the cross clock domain path can be checked using the report_cdc command, which can be report_cdc-all-hier, the command will generate a report listing all cross clock domain paths and marking possible safety problems, the developer can repair according to the suggestions in the report.

[0063] Compared with the related art, the method for extracting asynchronous paths and constraints based on a synthesized netlist in the chip design has the following beneficial effects:

[0064] The method for extracting asynchronous paths and constraints based on a synthesized netlist in the chip design provided by the application can ensure the correct processing of the asynchronous path, avoid the metastable state problem, improve the reliability of the design, and improve the process, which includes extracting the asynchronous path, generating the asynchronous constraint, providing the list of abnormal paths, and checking the safety of the path using the report_cdc, thereby ensuring the correctness and efficiency of the asynchronous design.

[0065] The above description is only an embodiment of the application, and does not limit the patent scope of the application, and any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the application.

Claims

1. A method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design, characterized in that: The following steps are involved: S1: Use the PrimeTime tool to read the synthesized netlist and SDC; S2: Use the check_timing-include clock_crossng command to extract the interactive clock pairs and use the script to process the list of real asynchronous clock pairs. S3: Circulate the asynchronous clock pair list, use the [get_timing_path-from starting point clock-to end point asynchronous clock] command to extract all asynchronous path related information, and print a report; S4: Read the asynchronous path LIS, match the endpoint register with the common cross-clock module, put the matching result into a temporary file, and print the matching result into the abnormal asynchronous path list; S5: Compare the start and end clock frequencies of each asynchronous path, and set the asynchronous constraint Set_max_delay0.5*period - from the start register to the end register according to 0.5 cycles of the higher-frequency clock. Print the asynchronous constraint and provide it to the backend for direct use.

2. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, characterized in that: The design information obtained by using the primetime tool to read the integrated netlist and sdc file includes pin information, registers, combinational logic and clock information.

3. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, wherein: In the sdc, a clock_group is set between asynchronous clocks. The check_timing-includeclock_crossing command is used to extract all interacting clock pairs in the design, including synchronous and asynchronous ones, and only asynchronous clock pairs are retained. A list of asynchronous clock pairs is output, with only one pair of asynchronous clocks in each row.

4. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, wherein: The asynchronous clock pair list is traversed in a loop, with the starting clock at the front and the ending clock at the back of each line. The timing path under each asynchronous clock pair is extracted using get_timing_path-from starting clock-to ending clock. The starting and ending registers, clock frequencies, and the starting and ending clock names are captured to form the complete asynchronous path. The asynchronous path list is printed out in a certain format.

5. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, wherein: The asynchronous path list is read, the endpoint register is matched with the common cross-clock module, and the matching is put into a temporary file, and the matching failure is printed into the abnormal asynchronous path list and submitted to the developer for confirmation.

6. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 4, wherein: The traversal saves the matched asynchronous paths in a temporary file, compares the start and end clock frequencies of each asynchronous path, and performs asynchronous constraints according to 0.5 cycles of the clock with the higher frequency. Set_max_delay 0.5*period-from the start register-to the end register, and prints it line by line into the asynchronous constraint file, which can be provided to the backend for direct use.

7. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, wherein: The S4 step also The method comprises the following steps: S41: identifying a starting point and an end point of an asynchronous path; S42: Check the clock frequency of the asynchronous path; S43: Generate asynchronous constraints; S44: Provide a list of abnormal paths; S45: Ignore using the set_false_path command; S46: Use report_cdc to check the cross-clock domain path.

8. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 7, wherein: In the S41 step, the check_timing command extracts all asynchronous paths and records their starting and ending registers; the clock information of the starting and ending registers is obtained through the get_clocks command; the clock frequency of the asynchronous path is compared with the clock frequency of the starting and ending registers, and 0.5 cycles of the higher frequency clock are determined as the constraint basis.

9. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 1, wherein: For the paths that fail to match, an asynchronous constraint is generated using the set_max_delay command, and a list of paths that fail to match is saved in a temporary file for the developer to confirm and modify.

10. The method for extracting asynchronous paths and constraints based on a synthesized netlist in chip design according to claim 7, wherein: There is a clear asynchronous relationship between the start and end clocks of the asynchronous path. The set_false_path command is used to ignore the timing check of the path; the report_cdc command is used to check the security and correctness of the cross-clock domain path.

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