PCB layout optimization method, system, device and medium based on evolutionary algorithm

Abstract

The application discloses an evolutionary algorithm-based PCB layout optimization method, system, device and medium, and relates to the field of electronic design automation.The method comprises the following steps: S1, obtaining an initial layout generated by a PCB; S2, judging whether the iteration number is greater than or equal to the maximum iteration number; S3, if yes, ending; S4, if no, generating a new layout according to random disturbance of the current layout; S5, comparing the new layout with the current layout by using a target function, and judging whether the new layout is better than the current layout; S6, if no, judging whether an acceptance probability function is greater than a set value; S7, if less than or equal to, returning to S2; S8, if the acceptance probability function is greater than the set value or the new layout is better than the current layout, taking the new layout as the current layout; and S9, when the current layout is better than the best layout, updating the best layout by using the current layout, and returning to S2.The method realizes the optimization of the PCB layout, and achieves a more ideal layout effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic design automation, and in particular to a PCB layout optimization method, system, device and medium based on an evolutionary algorithm. BACKGROUND

[0002] In the field of electronic design automation (EDA), the device layout design of a printed circuit board (PCB) is a crucial link that directly affects the performance, reliability, manufacturability and cost of a product. With the development of electronic products towards miniaturization, high density and complexity, the challenges of PCB layout design are increasing.

[0003] In board-level EDA, existing automatic layout methods often use heuristic search algorithms such as simulated annealing algorithms. The key to this type of algorithm is the design of the objective function. Simulated annealing algorithms are derived from the principle of solid annealing, which solves optimization problems by simulating the random motion of particles at high temperatures and the gradual stabilization process when the temperature is lowered. The algorithm accepts poor solutions with a probability, avoids being trapped in local optima, and is affected by parameters such as initial temperature and cooling strategy. It is suitable for fields such as combinatorial optimization and machine learning. There are two main problems in the design of the objective function:

[0004] 1. There is no universal objective function that can express all cases.

[0005] 2. In multi-objective optimization, it is difficult to normalize data, leading to complex weight design. Many times, only two or three indicators can be used as the objective function. SUMMARY

[0006] The purpose of the present application is to provide a PCB layout optimization method, system, device and medium based on an evolutionary algorithm, which realizes automatic layout and optimization of a PCB, thereby achieving a more ideal layout effect.

[0007] The present application is implemented by the following technical solutions:

[0008] In a first aspect, the present application provides a PCB layout optimization method based on an evolutionary algorithm, comprising:

[0009] S1: obtaining an initial layout generated by a PCB according to a signal flow method;

[0010] S2: determining whether the number of iterations is greater than or equal to a preset maximum number of iterations;

[0011] S3: if yes, ending;

[0012] S4: if no, generating a new layout according to a random disturbance of the current layout;

[0013] S5: comparing the new layout with the current layout by using the target function to determine whether the new layout is better than the current layout;

[0014] S6: if not, determining whether the acceptance probability function is greater than a set value;

[0015] S7: if less than or equal to, returning to step S2;

[0016] S8: if the acceptance probability function is greater than the set value or the new layout is better than the current layout, accepting the new layout and taking the new layout as the current layout;

[0017] S9: determining whether the current layout is better than the best layout;

[0018] S10: if not, returning to step S2;

[0019] S11: if yes, updating the best layout by using the current layout and returning to step S2.

[0020] Further, the target function comprises a comparison model, which judges the input first PCB layout image and second PCB layout image, the first PCB layout image and the second PCB layout image are the same PCB layout module but different layout schemes, and outputs that the layout scheme of the first PCB layout image is better or the layout scheme of the second PCB layout image is better.

[0021] Further, the comparison model uses a visual Transformer model to extract features in the PCB layout image.

[0022] Further, the target function further comprises line length, flying wire intersection, flying wire length, half circle length and layout area.

[0023] Further, different types of PCB layout modules use different target functions, specifically: BGA modules containing chips and layout modules not containing chips use a target function with dynamic weight adjustment, and non-BGA modules containing chips use a comparison model.

[0024] Further, the target function with dynamic weight adjustment Reward is:

[0025] ;

[0026] wherein, is the weight corresponding to the normalized parameter, is the normalized parameter.

[0027] In a second aspect, another embodiment of the present application provides an evolutionary algorithm-based PCB layout optimization system for implementing the evolutionary algorithm-based PCB layout optimization method described in the first embodiment, the system comprising: an information acquisition module, a random disturbance module, and a layout scheme analysis module,

[0028] The information acquisition module is configured to acquire an initial layout of a PCB generated in a signal flow manner.

[0029] The random disturbance module is configured to generate a new layout by randomly disturbing a current layout.

[0030] The layout scheme analysis module is configured to compare the new layout with the current layout using a target function and determine whether the new layout is better than the current layout.

[0031] If not, it is determined whether an acceptance probability function is greater than a set value.

[0032] If less than or equal to, it is determined whether an iteration number is greater than or equal to a preset maximum iteration number.

[0033] If the acceptance probability function is greater than the set value or the new layout is better than the current layout, the new layout is accepted and used as the current layout.

[0034] It is determined whether the current layout is better than an optimal layout.

[0035] If not, it is determined whether the iteration number is greater than or equal to the preset maximum iteration number.

[0036] If yes, the optimal layout is updated using the current layout, and it is determined whether the iteration number is greater than or equal to the preset maximum iteration number. If the iteration number is greater than or equal to the preset maximum iteration number, the process ends.

[0037] Further, the target function comprises a comparison model configured to determine whether a first PCB layout image or a second PCB layout image is better, wherein the first PCB layout image and the second PCB layout image are of the same PCB layout module but have different layout schemes.

[0038] In a third aspect, another embodiment of the present application provides an electronic device comprising a processor, an input device, an output device, and a memory, wherein the processor, the input device, the output device, and the memory are connected to each other, the memory is configured to store a computer program, the computer program comprises program instructions, and the processor is configured to invoke the program instructions to execute the method described in the first embodiment.

[0039] In a fourth aspect, another embodiment of the present application provides a computer readable storage medium storing a computer program, the computer program comprising program instructions, which when executed by a processor, cause the processor to perform the method described in the first embodiment.

[0040] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0041] The PCB layout optimization method, system, device and medium based on the evolutionary algorithm provided by the embodiment of the present application generate a layout scheme through the evolutionary algorithm, compare the new layout with the current layout by using the objective function, determine a better layout scheme, take the better layout scheme as the current layout scheme, compare the current layout scheme with the best layout scheme, and if the current layout scheme is better than the best layout scheme, update the best layout scheme with the current layout scheme, so that the automatic layout and optimization of the PCB are realized, and thus a more ideal layout effect is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and thus should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor. In the drawings:

[0043] Figure 1 The flow chart of the PCB layout optimization method based on the evolutionary algorithm provided for the first embodiment of the present application;

[0044] Figure 2 The framework diagram of the evolutionary algorithm;

[0045] Figure 3 The network structure diagram of the comparative model;

[0046] Figure 4 The schematic diagram of the layout module initializing the layout;

[0047] Figure 5 The schematic diagram of the new layout after the optimization of the layout module;

[0048] Figure 6 The structural block diagram of the PCB layout optimization system based on the evolutionary algorithm provided for another embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, further, the present application is described in detail below with reference to the embodiments and drawings, the illustrative embodiments and the description thereof are only used to explain the present application, and do not limit the present application.

[0050] As shown in Figure 1 The first embodiment of the present application provides a PCB layout optimization method based on an evolutionary algorithm, comprising the following steps:

[0051] S1: obtaining an initial layout of a PCB generated in a signal flow manner;

[0052] S2: determining whether the iteration number is greater than or equal to a preset maximum iteration number;

[0053] S3: if yes, ending;

[0054] S4: if no, generating a new layout according to random disturbance of the current layout;

[0055] S5: comparing the new layout with the current layout by using a target function, and determining whether the new layout is better than the current layout;

[0056] S6: if no, determining whether an acceptance probability function is greater than a set value;

[0057] S7: if less than or equal to, returning to step S2;

[0058] S8: if the acceptance probability function is greater than the set value or the new layout is better than the current layout, accepting the new layout, and taking the new layout as the current layout;

[0059] S9: determining whether the current layout is better than a best layout;

[0060] S10: if no, returning to step S2;

[0061] S11: if yes, updating the best layout by using the current layout, and returning to step S2.

[0062] In the embodiment, the evolutionary algorithm is used to continuously optimize the layout scheme. As shown in Figure 2As shown, first, the PCB board generates an initial layout in a signal flow manner, at which time the initial layout can be taken as the best layout. Then, it is judged whether the iteration number is greater than or equal to the preset maximum iteration number, if less, a new layout is generated according to the random disturbance of the current layout, the random disturbance includes translation, rotation, exchange, and turning, etc. The target function is used to compare the new layout and the current layout, it is judged whether the new layout is better than the current layout, if not, the new layout is accepted as the current layout according to a certain probability, if yes, the new layout is selected as the current layout. Finally, it is judged whether the current layout is better than the best layout, if yes, the current layout is used to update the best layout, and it is returned to judge whether the iteration number is greater than or equal to the preset maximum iteration number, if the best layout is better than the current layout, it is returned to judge whether the iteration number is greater than or equal to the preset maximum iteration number, and the process is ended when the iteration number is greater than or equal to the preset maximum iteration number. The maximum iteration number is designed according to the number of devices, generally set to 100 times of the number of devices, and the maximum is 3000 times. The evolutionary algorithm is used to realize the automatic generation of the layout module layout scheme.

[0063] The target function includes a comparison model, including line length, flying wire intersection point, flying wire length, half cycle length, and layout area, such as Figure 3 As shown, the comparison model is used to compare two different layout schemes of the same PCB layout module, and the better one is selected. The schematic diagram of the two different layout schemes of the same PCB layout module is as shown in Figure 4 、 5 As shown, the comparison model structure: first, the visual Transformer model (ViT, Vision Transformer) is used for feature extraction, the extracted features are processed through the linear layer 1, the dropout layer and the linear layer 2, and the 768-dimensional features output by the ViT are mapped to the score of the 1-dimensional data. Using an end-to-end way, only the ViT will load a pre-training file. Forward propagation logic: score scalars s1 and s2 are obtained by scoring the two input images at the same time. Loss function: using nn.MarginRankingLoss, comparing the difference between two scores s1 and s2, and comparing with the label (1 or -1) to calculate the loss. 1 represents that the first layout scheme is better, and -1 represents that the second layout scheme is better. In the trained comparison model, the first PCB board layout image and the second PCB board layout image are input, the comparison model judges the first PCB board layout image and the second PCB board layout image, the first PCB board layout image and the second PCB board layout image are the same PCB layout module but different layout schemes, and outputs that the layout scheme of the first PCB board layout image is better or the layout scheme of the second PCB board layout image is better. Using the comparison model, the problem of difficult design of the target function in the traditional layout algorithm is solved.

[0064] Although the contrast model has an ideal effect, the time-consuming of generating pictures is long, therefore, the PCB layout module is classified, different types of PCB layout module use different objective functions, the BGA module containing key devices and the layout module not containing key devices adopt the objective function of dynamic weight adjustment, the non-BGA module containing key devices adopts the contrast model. The key device refers to the core device in a layout module, which usually refers to a chip. The objective function Reward with dynamic weight adjustment is:

[0065] ;

[0066] Wherein, is the weight corresponding to the normalized parameter, is the normalized parameter. Different layout modules select different parameters and weights. Through the weight dynamic adjustment algorithm, the weight of the parameter with large change range is reduced, and the weight of the parameter with small change range is increased, so as to realize the uniform decrease of each parameter.

[0067] The PCB layout optimization method based on the evolutionary algorithm provided by the embodiment of the application generates a layout scheme through an evolutionary algorithm, compares a new layout with a current layout by using an objective function, judges a better layout scheme, takes the better layout scheme as the current layout scheme, compares the current layout scheme with the best layout scheme, and if the current layout scheme is better than the best layout scheme, updates the best layout scheme with the current layout scheme, realizes the automatic layout and optimization of the PCB, and thus a more ideal layout effect is achieved.

[0068] As shown in Figure 6 The PCB layout optimization system based on the evolutionary algorithm provided by another embodiment of the application is used to realize the PCB layout optimization method based on the evolutionary algorithm described in the first embodiment, and the system comprises an information acquisition module, a random disturbance module and a layout scheme analysis module. The information acquisition module is used to acquire an initial layout generated by a PCB according to a signal flow mode. The random disturbance module is used to generate a new layout by randomly disturbing a current layout. The layout scheme analysis module compares the new layout with the current layout by using an objective function, judges whether the new layout is better than the current layout, judges whether an acceptance probability function is greater than a set value if the new layout is not better than the current layout, judges whether an iteration number is greater than or equal to a preset maximum iteration number if the acceptance probability function is less than or equal to the set value, accepts the new layout and takes the new layout as the current layout if the acceptance probability function is greater than the set value or the new layout is better than the current layout, judges whether the current layout is better than a best layout, judges whether the iteration number is greater than or equal to the preset maximum iteration number if the current layout is not better than the best layout, uses the current layout to update the best layout if the iteration number is greater than or equal to the preset maximum iteration number, and ends if the iteration number is greater than or equal to the preset maximum iteration number.

[0069] The target function comprises a comparison model for judging input first and second PCB layout images, the first and second PCB layout images being the same PCB layout module but different layout schemes, and outputting that the layout scheme of the first PCB layout image is better or the layout scheme of the second PCB layout image is better.

[0070] The embodiment of the present application provides a PCB layout optimization system based on an evolution algorithm, generates a layout scheme through the evolution algorithm, compares the new layout with a current layout by using a target function, judges a better layout scheme, takes the better layout scheme as the current layout scheme, compares the current layout scheme with a best layout scheme, and updates the best layout scheme with the current layout scheme if the current layout scheme is better than the best layout scheme, so that automatic layout and optimization of the PCB are realized, and thus a more ideal layout effect is achieved.

[0071] The embodiment of the present application provides an electronic device, which comprises a processor, an input device, an output device and a memory, the processor, the input device, the output device and the memory are connected with each other, the memory is used for storing a computer program, the computer program comprises program instructions, the processor is configured to invoke the program instructions, and the method described in the first embodiment is executed.

[0072] It should be understood that, in the embodiments of the present application, the processor can be a central processing unit (CPU), and the processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), ready-to-program gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0073] The input device can include a touchpad, a microphone, etc., and the output device can include a display (LCD, etc.), a speaker, etc.

[0074] The memory can include read-only memory and random access memory, and provide instructions and data for the processor. A part of the memory can also include non-volatile random access memory. For example, the memory can also store device type information.

[0075] In particular implementations, the processor, the input device, and the output device described in the embodiments of the present application can execute the implementation manners of the method embodiments described in the embodiments of the present application, and can also execute the implementation manners of the system embodiments described in the embodiments of the present application, which will not be described herein again.

[0076] In the embodiments of the present application, a computer readable storage medium is also provided, which stores a computer program. The computer program includes program instructions, which, when executed by a processor, cause the processor to perform the method described in the first embodiment.

[0077] The computer readable storage medium can be an internal storage unit of the device, such as a hard disk or a memory of the device. The computer readable storage medium can also be an external storage device of the device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like. Further, the computer readable storage medium can include both the internal storage unit and the external storage device of the device. The computer readable storage medium is used to store the computer program and other programs and data required by the device. The computer readable storage medium can also be used to temporarily store data that has been output or will be output.

[0078] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in the above description in general terms. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0079] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the devices and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein again.

[0080] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. For example, the division of the units is only a logical function division, and other division manners can be adopted during actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electric, mechanical or in other forms.

[0081] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the specification of the present application.

Claims

1. A PCB board layout optimization method based on evolutionary algorithms, characterized in that, include: S1: Obtain the initial layout of the PCB board generated according to the signal flow method; S2: Determine if the number of iterations is greater than or equal to the preset maximum number of iterations; S3: If yes, then end; S4: If not, generate a new layout by creating a random perturbation based on the current layout. S5: Use an objective function to compare the new layout with the current layout and determine whether the new layout is better than the current layout; S6: If not, determine whether the acceptance probability function is greater than the set value; S7: If it is less than or equal to, return to step S2; S8: If the acceptance probability function is greater than the set value or the new layout is better than the current layout, then accept the new layout and use the new layout as the current layout; S9: Determine if the current layout is better than the optimal layout; S10: If not, return to step S2; S11: If yes, update the best layout using the current layout and return to step S2; Different objective functions are used for different types of PCB layout modules. Specifically, BGA modules containing chips and layout modules without chips use a dynamic weight adjustment objective function, while non-BGA modules containing chips use a comparative model. The objective function Reward, which employs dynamic weight adjustment, is: ； in, The weights corresponding to the normalized parameters. These are the normalized parameters.

2. The PCB layout optimization method based on evolutionary algorithm according to claim 1, characterized in that, The objective function includes a comparison model, which judges the input first PCB layout image and second PCB layout image. The first PCB layout image and the second PCB layout image are the same PCB layout module but have different layout schemes. The model outputs that the layout scheme of the first PCB layout image is better or the layout scheme of the second PCB layout image is better.

3. The PCB layout optimization method based on evolutionary algorithm according to claim 2, characterized in that, The comparison model uses a visual Transformer model to extract features from the PCB layout image.

4. The PCB layout optimization method based on evolutionary algorithm according to claim 2, characterized in that, The objective function also includes line length, fly line intersection point, fly line length, half-circle line length, and layout area.

5. A PCB layout optimization system based on an evolutionary algorithm, characterized in that, To implement the PCB layout optimization method based on evolutionary algorithms as described in any one of claims 1-4, the system comprises: an information acquisition module, a random perturbation module, and a layout scheme analysis module. The information acquisition module is used to acquire the initial layout of the PCB board generated according to the signal flow method; The random perturbation module is used to generate random perturbations based on the current layout to obtain a new layout; The layout scheme analysis module uses an objective function to compare the new layout with the current layout to determine whether the new layout is better than the current layout. If not, then determine whether the acceptance probability function is greater than the set value; If the number of iterations is less than or equal to the preset maximum number of iterations, then determine whether the number of iterations is greater than or equal to the preset maximum number of iterations. If the acceptance probability function is greater than the set value or the new layout is better than the current layout, then the new layout is accepted and used as the current layout. Determine if the current layout is better than the optimal layout; If not, then determine whether the number of iterations is greater than or equal to the preset maximum number of iterations; If so, update the best layout using the current layout and determine if the number of iterations is greater than or equal to the preset maximum number of iterations. If the number of iterations is greater than or equal to the preset maximum number of iterations, then the process ends.

6. The PCB layout optimization system based on evolutionary algorithm according to claim 5, characterized in that, The objective function includes a comparison model, which judges the input first PCB layout image and second PCB layout image. The first PCB layout image and the second PCB layout image are the same PCB layout module but have different layout schemes. The model outputs that the layout scheme of the first PCB layout image is better or the layout scheme of the second PCB layout image is better.

7. An electronic device, comprising: The system includes a processor, an input device, an output device, and a memory, which are interconnected. The memory is used to store a computer program, which includes program instructions. The processor is configured to invoke the program instructions to execute the method as described in any one of claims 1-4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 1-4.

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