Layout detection method and device

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to a layout detection method and device.The method comprises the steps that according to film layer information in different areas in a to-be-detected layout, device types of the different areas are obtained; obtaining device structure definition information of device types in the truth table; obtaining design rule information of device types in a design rule manual; according to the device structure definition information, rule information is designed, and rule violation information is generated; and generating a target violation identification result of the to-be-detected layout according to the violation rule information. At least the violation design of the device structure and the film layer in the publication can be efficiently, intelligently and comprehensively detected.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and particularly relates to a layout detection method and device. BACKGROUND

[0002] Before performing a semiconductor manufacturing process to produce a semiconductor structure, LVS (Layout Versus Schematic) is generally used to check whether there is a device design that does not meet the process requirements in the layout, so as to improve the yield of manufacturing the semiconductor structure.

[0003] However, the LVS defect checking technology generally compares the layout extraction netlist with the circuit netlist, and relies on manual checking to identify the device design that does not meet the process requirements. Not only can it not identify the film layer design error inside the device, but also it is difficult to achieve comprehensive checking, and a large amount of time is required. SUMMARY

[0004] Therefore, it is necessary to provide a layout detection method and device to at least efficiently and intelligently and comprehensively detect the illegal design of the device structure and the film layer in the published layout, so as to avoid the illegal design from entering the manufacturing process.

[0005] To achieve the above object and other objects, according to various embodiments of the present disclosure, an aspect of the present disclosure provides a layout detection method, comprising:

[0006] obtaining a to-be-detected layout, a truth table of a semiconductor device structure, and a design rule manual;

[0007] obtaining a device type of different regions according to film layer information in the different regions in the to-be-detected layout; the film layer information comprises at least one of a film layer name, a film layer thickness, a film layer size, a doping concentration and type, a material type, a conductive type, and a layer sequence structure;

[0008] obtaining device structure definition information of the device type in the truth table;

[0009] obtaining design rule information of the device type in the design rule manual;

[0010] generating rule violation information according to the device structure definition information and the design rule information; the rule violation information comprises a violation of a semiconductor device structure rule and / or a size rule;

[0011] generating a target illegal identification result of the to-be-detected layout according to the rule violation information; the target illegal identification result comprises at least one of illegal film layer information, illegal device information, and respective illegal information.

[0012] In one embodiment, obtaining the device type of the different regions comprises:

[0013] obtaining typical film layer characteristics of a preset semiconductor device;

[0014] traversing different regions in the layout to be detected, determining device types of the different regions according to the typical film layer characteristics of the preset semiconductor device and film layer information in the different regions; the typical film layer characteristics include necessary film layer information and / or prohibited film layer information.

[0015] In one embodiment, the typical film layer characteristics of the preset semiconductor device include at least one of the following characteristics:

[0016] The typical film layer characteristics of a metal-oxide-semiconductor field effect transistor include a gate, a source-drain region, and a gate oxide layer with a preset thickness;

[0017] The typical film layer characteristics of a diode include a single-layer or double-layer doping structure, and no gate or insulating layer;

[0018] The typical film layer characteristics of a bipolar transistor include a base region, and a three-layer stack structure with a conductive type of NPN or PNP in sequence;

[0019] The typical film layer characteristics of an integrated circuit interconnection structure include a plurality of via structures, and alternating metal and dielectric layers;

[0020] The typical film layer characteristics of a junction gate bipolar transistor include a bipolar collector region structure and a gate.

[0021] In one embodiment, the design rule information of the device type includes user-predefined definition film layer information, the definition film layer information includes film layer information that cannot be used, and / or film layer information that meets the design rules of the semiconductor device.

[0022] In one embodiment, generating a target violation identification result of the layout to be detected includes:

[0023] According to the violation film layer information and the violation device information, highlighting the violation film layer and / or the violation device in the layout to be detected.

[0024] In one embodiment, the violation film layer information and the violation device information are updated to a violation information library; the layout detection method further includes: obtaining violation rule information that matches the device structure definition information in the violation information library.

[0025] In one embodiment, the layout detection method further includes: adjusting the semiconductor device structure rules and / or dimensions according to the violation rule information until the obtained violation rule information is reduced to meet the target requirements.

[0026] Some embodiments of the present disclosure also disclose a layout detection device, comprising a data acquisition module, a device type identification module, a definition information acquisition module, a rule information acquisition module, a violation information acquisition module and a violation result generation module. The data acquisition module is configured to acquire a layout to be detected, a truth table of a semiconductor device structure and a design rule manual. The device type identification module is configured to acquire device types of different regions according to film layer information in the different regions in the layout to be detected. The film layer information comprises at least one of a film layer name, a film layer thickness, a film layer size, a doping concentration and type, a material type, a conductive type and a layer sequence structure. The definition information acquisition module is configured to acquire device structure definition information of the device types in the truth table. The rule information acquisition module is configured to acquire design rule information of the device types in the design rule manual. The violation information acquisition module is configured to generate violation rule information according to the device structure definition information and the design rule information. The violation rule information comprises violation semiconductor device structure rules and / or size rules. The violation result generation module is configured to generate target violation identification results of the layout to be detected according to the violation rule information. The target violation identification results comprise at least one of violation film layer information, violation device information and respective violation information.

[0027] In one embodiment, the device type identification module comprises a typical film layer feature acquisition unit and a device type generation unit. The typical film layer feature acquisition unit is configured to acquire typical film layer features of a preset semiconductor device. The device type generation unit is configured to traverse different regions in the layout to be detected, and determine device types of the different regions according to the typical film layer features of the preset semiconductor device and film layer information in the different regions. The typical film layer features comprise necessary film layer information and / or prohibited film layer information.

[0028] In one embodiment, the rule information acquisition module further comprises a custom rule information acquisition unit. The custom rule information acquisition unit is configured to acquire definition film layer information pre-set by a user. The definition film layer information comprises film layer information that cannot be used and / or film layer information that satisfies semiconductor device design rules.

[0029] The above embodiments of the present disclosure can at least produce the following unexpected technical effects:

[0030] After obtaining the to-be-detected layout, the truth table of the semiconductor device structure, and the design rule manual, the device type of different regions in the to-be-detected layout is obtained according to the film layer information in the different regions in the to-be-detected layout, wherein the film layer information includes at least one of the film layer name, the film layer thickness, the film layer size, the doping concentration and type, the material type, the conductive type, and the layer sequence structure; the device structure definition information of the device type in the truth table is queried and obtained; the design rule information of the device type in the design rule manual is queried and obtained; the device structure definition information and the design rule information are compared, and the rule violation information is generated according to the comparison result, wherein the rule violation information includes the violation of the semiconductor device structure rule and / or the size rule; the target rule violation identification result of the to-be-detected layout is generated according to the rule violation information, and the target rule violation identification result includes at least one of the rule violation film layer information, the rule violation device information, and the respective rule violation information. Therefore, the rule violation design of the device structure and the film layer in the to-be-detected layout is efficiently and intelligently and comprehensively detected, the rule violation design is avoided from entering the manufacturing process, the comprehensiveness, the intelligence, and the efficiency of the layout detection are improved, the dependence on the experience and the ability of the related workers is avoided, the detection cost is reduced, and the yield and the performance of the subsequent semiconductor device preparation are improved. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort.

[0032] Figure 1 A top view schematic diagram of a rule violation design provided in an embodiment of the present disclosure;

[0033] Figure 2 A flowchart of a layout detection method provided in an embodiment of the present disclosure;

[0034] Figure 3 A flowchart of a layout detection method provided in another embodiment of the present disclosure;

[0035] Figure 4 A structural schematic diagram of a layout detection device provided in an embodiment of the present disclosure;

[0036] Figure 5 A structural schematic diagram of a layout detection device provided in another embodiment of the present disclosure;

[0037] Explanation of reference signs:

[0038] 100, layout detection device; 10, data acquisition module; 20, device type identification module; 30, definition information acquisition module; 40, rule information acquisition module; 50, violation information acquisition module; 60, violation result generation module; 21, typical film layer feature acquisition unit; 22, device type generation unit; 41, self-defined rule information acquisition unit. DETAILED DESCRIPTION

[0039] For the purpose of promoting the understanding of the present disclosure, the present disclosure will be more fully described by referring to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure can be more thoroughly and completely understood.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0041] In the case of using "include", "have", and "contain" described herein, unless an explicit limiting term is used, such as "only", "consisting of", and the like, another component can be added. Unless otherwise mentioned, the singular form of the term can include the plural form and cannot be understood as one in number.

[0042] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0043] In addition, the terms "first", "second", and the like are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0044] GDS (Graphic Data System) is a binary file format used to describe and store the layout information of a semiconductor chip. It can be used for comparison and checking between the netlist extracted from the GDS layout and the circuit netlist, for example, comparing the layout netlist of a chip with the schematic netlist, that is, using LVS (Layout Versus Schematic) netlist comparison to ensure the logical consistency of the two, so as to avoid the design that does not meet the process requirements flowing into production.

[0045] Tape-out refers to the process of submitting design files to a semiconductor foundry for production after the completion of integrated circuit design. The main process of tape-out involves multiple key steps, including design verification, physical design, layout, manufacturing preparation, and file generation. The process of tape-out usually starts from the design verification stage, and customers generally use tape-out to detect errors in the layout in advance. However, the layout file checked by tape-out needs to be manually checked to identify device design errors with the naked eye. For example, Figure 1 is a design error found by relevant workers on the file after tape-out checking, that is, Figure 1 the N-type well region LVNW of the low voltage complementary metal oxide semiconductor device (Low Voltage Complementary Metal-Oxide-Semiconductor, LVCMOS) in covers the active area (AA, Active Area) of the high voltage complementary metal oxide semiconductor device (High Voltage Complementary Metal-Oxide-Semiconductor, HVCMOS), wherein Figure 1 the PO in can indicate a gate. Depending on manual inspection, not only is it inefficient and prone to error, but it also cannot be fully checked.

[0046] Therefore, the present disclosure aims to provide a layout detection method and device that can at least efficiently and intelligently detect illegal designs of device structures and film layers in the layout, and avoid illegal designs from entering the manufacturing process.

[0047] The layout detection method and device provided by the embodiments of the present disclosure can be applied to a layout detection processor, the layout detection processor communicates with a server through a network, the server is in communication connection with a server receiving end, and the layout detection processor can also be directly in communication connection with the server receiving end. The communication connection mode includes wired or wireless connection.

[0048] For example, the layout detection method and device are applied to a layout detection processor, and the layout detection processor can obtain the layout to be detected, the truth table of the semiconductor device structure, and the design rule manual, etc. from the receiving end of the server; the layout detection processor can obtain the device types in different areas based on the film layer information in different areas of the layout to be detected; the film layer information includes at least one of the film layer name, film layer thickness, film layer size, doping concentration and type, material type, conductivity type, and layer sequence structure; the layout detection processor can obtain the device structure definition information of the device type in the truth table and the design rule information of the device type in the design rule manual; then, after the layout detection processor generates violation information based on the device structure definition information and the design rule information, it generates a target violation identification result of the layout to be detected based on the violation information, and the target violation identification result includes the violation film layer information, the violation device information, and at least one of the respective violation information, and the violation information includes violation of the semiconductor device structure rules and / or size rules.

[0049] For another example, the layout detection method and device are applied to a server, and the server obtains the layout to be detected, the truth table of the semiconductor device structure, and the design rule manual from the server receiving end; the server can obtain the device types in different areas based on the film layer information in different areas of the layout to be detected; the film layer information includes at least one of the film layer name, film layer thickness, film layer size, doping concentration and type, material type, conductivity type, and layer sequence structure; the server can obtain the device structure definition information of the device type in the truth table and the design rule information of the device type in the design rule manual; then, after generating the rule violation information based on the device structure definition information and the design rule information, the server generates the target violation identification result of the layout to be detected based on the rule violation information, and the target violation identification result includes the violation film layer information, the violation device information, and at least one of the respective violation information, and the rule violation information includes violation of the semiconductor device structure rules and / or size rules.

[0050] like Figure 2 As shown, in some embodiments, a layout detection method is provided, comprising the following steps:

[0051] Step S11: Obtaining the truth table and design rule manual of the layout to be tested, semiconductor device structure;

[0052] Step S12: obtaining device types in different areas based on film layer information in different areas of the layout to be inspected; the film layer information includes at least one of film layer name, film layer thickness, film layer size, doping concentration and type, material type, conductivity type, and layer sequence structure;

[0053] Step S13: Obtain device structure definition information of the device type in the truth table;

[0054] Step S14: obtaining the design rule information of the device type in the design rule manual;

[0055] Step S15: generating the rule violation information according to the device structure definition information and the design rule information, the rule violation information including the violation of the semiconductor device structure rule and / or the size rule;

[0056] Step S16: generating the target rule violation identification result of the to-be-detected layout according to the rule violation information, the target rule violation identification result including at least one of the rule violation film layer information, the rule violation device information, and the respective rule violation information.

[0057] The above embodiments of the present disclosure can at least produce the following unexpected technical effects:

[0058] After obtaining the to-be-detected layout, the truth table of the semiconductor device structure, and the design rule manual, the device type of different regions in the to-be-detected layout is obtained according to the film layer information in the different regions, wherein the film layer information includes at least one of the film layer name, the film layer thickness, the film layer size, the doping concentration and type, the material type, the conductive type, and the layer sequence structure; the device structure definition information of the device type in the truth table is queried and obtained; the design rule information of the device type in the design rule manual is queried and obtained; the rule violation information is generated according to the comparison result by comparing the device structure definition information and the design rule information, the rule violation information including the violation of the semiconductor device structure rule and / or the size rule; the target rule violation identification result of the to-be-detected layout is generated according to the rule violation information, the target rule violation identification result including at least one of the rule violation film layer information, the rule violation device information, and the respective rule violation information. Thus, the rule violation design of the device structure and the film layer in the layout is efficiently and intelligently detected comprehensively, the rule violation design is avoided from entering the manufacturing process, the time of layout detection is effectively shortened, the comprehensiveness, intelligence, and efficiency of layout detection are improved, the dependence on the experience and ability of related workers is avoided, the detection cost is reduced, and the yield and performance of subsequent semiconductor device preparation are improved.

[0059] As shown in FIG. 1, in some embodiments, the step of obtaining the device type of different regions in step S12 can include the following steps: Figure 3

[0060] Step S121: obtaining the typical film layer characteristics of the preset semiconductor device;

[0061] Step S122: traversing different regions in the to-be-detected layout, and determining the device type of different regions according to the typical film layer characteristics of the preset semiconductor device and the film layer information in different regions; the typical film layer characteristics including the necessary film layer information and / or the prohibited use film layer information.

[0062] ​Specifically, for common semiconductor device types, the typical film layer features of different semiconductor device types can be set according to their key film layer features or structural features relative to other devices. For example, a typical film layer feature library of semiconductor device types can be set, which includes the typical film layer features of preset semiconductor devices, and the typical film layer features of the preset semiconductor devices include at least one of the following features: the typical film layer features of a metal-oxide-semiconductor field-effect transistor include a gate, a source-drain region, and a gate oxide layer with a preset thickness; the typical film layer features of a diode include a single-layer or double-layer doped structure, and no gate or insulating layer; the typical film layer features of a bipolar transistor include a base region, and a three-layer stack structure with the conductive types being NPN or PNP in sequence; the typical film layer features of an integrated circuit interconnection structure include a plurality of via structures, and alternating metal and dielectric layers; and the typical film layer features of a junction gate bipolar transistor include a bipolar collector region structure and a gate.

[0063] For example, in a metal-oxide-semiconductor field-effect transistor, the thickness of the gate oxide layer is generally set to 1 nm-5 nm, such as 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm, etc., and the polysilicon or metal of the gate is located above the gate oxide layer, with the conductive type matching that of the channel, and the source-drain region includes a highly doped N⁺ or P⁺ region forming a PN junction with the substrate.

[0064] For example, the core layer of a diode (PN junction or Schottky diode) includes a single semiconductor layer and a metal contact layer, without a complex gate or insulating layer.

[0065] For example, the core layer of a bipolar transistor (BJT) includes an emitter, a base, and a collector, for example, the emitter includes a highly doped N⁺ or P⁺ layer; the base includes an extremely thin and lightly doped layer of the opposite conductive type; and the collector includes a lowly doped N-type or P-type layer.

[0066] For example, the core layer of an integrated circuit (IC) interconnection structure includes a plurality of metal layers for signal transmission, dielectric layers for isolating the metal layers, and vias and contact holes for connecting different metal layers.

[0067] For example, the core layer of an insulated gate bipolar transistor (IGBT) includes a gate oxide layer, a collector region, and a drift region.

[0068] For example, in step S122, by traversing different regions in the layout to be detected, by determining the film layer information of each layer material, thickness, and doping in different regions, by comparing the typical film layer characteristics of the preset semiconductor device, and by comparing the film layer information in different regions, the device type of different regions is determined. The typical film layer characteristics include necessary film layer information and / or prohibited film layer information. For example, the necessary film layer information of a diode includes a single-layer or double-layer doping structure for forming a PN junction, and the prohibited film layer information includes a gate or an insulating layer.

[0069] Since different semiconductor device manufacturers have different special design requirements for different devices, by setting a window for user to input custom information, the user can set the definition film layer information according to his own special needs through the window, so as to customize the design rule information of the device type, or to calibrate and update in time. For example, the user-defined film layer information can include film layer information that cannot be used, and / or film layer information that meets the design rules of the semiconductor device.

[0070] In some embodiments, after obtaining the device types of different regions in the layout to be detected, in step S13, the device structure definition information corresponding to the device type can be searched in the truth table according to the device type. Since the actual film layer information of the devices in different regions of the layout to be detected is reflected in the truth table, after obtaining the device types of different regions in the layout to be detected, the device structure definition information corresponding to the device type can be obtained by querying the truth table.

[0071] In some embodiments, after obtaining the device types of different regions in the layout to be detected, in step S14, the design rule information corresponding to the device type can be searched in the design rule manual of the semiconductor device structure according to the device type. For example, a low-voltage NMOS transistor cannot use high-voltage film layers, cannot use P-type doping layers, and cannot use typical film layers of diodes.

[0072] In some embodiments, in step S15, by comparing the device structure definition information corresponding to the same device type and the design rule information, the violation rule information including the violation of the semiconductor device structure rule and / or the size rule can be generated.

[0073] In some embodiments, in step S16, the target violation identification result of the layout to be detected with better visibility and warning can be generated according to the violation rule information. The target violation identification result includes at least one of the violation film layer information, the violation device information, the violation information of the violation film layer, and the violation information of the violation device.

[0074] In some embodiments, in step S16, the target violation identification result of the layout to be detected is generated, including:

[0075] Step S161: according to the illegal film layer information and the illegal device information, highlight the illegal film layer and / or the illegal device in the layout to be detected.

[0076] For example, please continue to refer to Figure 1 The N-type well region LVNW layer in the layout can be highlighted, and the illegal information of the film layer can be directly sent to the monitor of the relevant worker, so as to timely and intelligently inform the relevant worker of all the checked illegal film layer or illegal structure information. Figure 1

[0077] In some embodiments, the illegal film layer information and the illegal device information can be updated to the illegal information library; when the layout detection method is started next time, the illegal information library matching the device structure definition information can be directly obtained, so as to further reduce the detection complexity and improve the detection efficiency.

[0078] In some embodiments, the layout detection method further comprises: adjusting the semiconductor device structure rule and / or size according to the illegal information, so that the obtained illegal information is reduced to meet the target requirement, avoiding the illegal design into the manufacturing process, and improving the yield and performance of the subsequent semiconductor device.

[0079] It should be understood that, although Figure 2-Figure 3 the steps in the flowchart of the layout detection method are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps has no strict sequence limitation, and these steps can be executed in other sequences. Moreover, Figure 2-Figure 3 at least part of the steps in the layout detection method can include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or steps or stages in other steps.

[0080] As Figure 4 ​As shown in some embodiments, a layout detection device 100 is provided, comprising a data acquisition module 10, a device type identification module 20, a definition information acquisition module 30, a rule information acquisition module 40, a violation information acquisition module 50, and a violation result generation module 60. The data acquisition module 10 is configured to acquire a layout to be detected, a truth table of a semiconductor device structure, and a design rule manual. The device type identification module 20 is configured to acquire device types of different regions according to film layer information in the different regions in the layout to be detected. The film layer information includes at least one of a film layer name, a film layer thickness, a film layer size, a doping concentration and type, a material type, a conductivity type, and a layer sequence structure. The definition information acquisition module 30 is configured to acquire device structure definition information of the device types in the truth table. The rule information acquisition module 40 is configured to acquire design rule information of the device types in the design rule manual. The violation information acquisition module 50 is configured to generate violation rule information according to the device structure definition information and the design rule information. The violation rule information includes violation of a semiconductor device structure rule and / or a size rule. The violation result generation module 60 is configured to generate a target violation identification result of the layout to be detected according to the violation rule information. The target violation identification result includes at least one of violation film layer information, violation device information, and respective violation information.

[0081] As shown in some embodiments, Figure 5 The device type identification module 20 includes a typical film layer feature acquisition unit 21 and a device type generation unit 22. The typical film layer feature acquisition unit 21 is configured to acquire typical film layer features of a preset semiconductor device. The device type generation unit 22 is configured to traverse different regions in the layout to be detected, and determine device types of the different regions according to the typical film layer features of the preset semiconductor device and film layer information in the different regions. The typical film layer features include necessary film layer information and / or prohibited film layer information.

[0082] As shown in some embodiments, Figure 5 The rule information acquisition module 40 further includes a custom rule information acquisition unit 41. The custom rule information acquisition unit 41 is configured to acquire definition film layer information pre-set by a user. The definition film layer information includes film layer information that cannot be used, and / or film layer information that satisfies a semiconductor device design rule. The custom rule information acquisition unit 41 facilitates the user to input the pre-set definition film layer information to meet special design requirements of different devices.

[0083] The above embodiments of the present disclosure can at least produce the following unexpected technical effects:

[0084] After the data acquisition module acquires the to-be-detected layout, the true value table of the semiconductor device structure, and the design rule manual, the device type recognition module can acquire the device types of different regions in the to-be-detected layout according to film layer information in different regions in the to-be-detected layout, wherein the film layer information includes at least one of a film layer name, a film layer thickness, a film layer size, a doping concentration and type, a material type, a conductive type, and a layer sequence structure; the definition information acquisition module can query and acquire device structure definition information of the device types in the true value table; the rule information acquisition module can query and acquire design rule information of the device types in the design rule manual; the rule violation information acquisition module generates rule violation information according to a comparison result by comparing the device structure definition information and the design rule information, wherein the rule violation information includes a violation of a semiconductor device structure rule and / or a size rule; and the rule violation result generation module can generate a target rule violation identification result of the to-be-detected layout according to the rule violation information, wherein the target rule violation identification result includes at least one of rule violation film layer information, rule violation device information, and respective rule violation information. Thus, the rule violation design of the device structure and the film layer in the layout can be efficiently and intelligently and comprehensively detected, the rule violation design can be avoided from entering the manufacturing process, the comprehensiveness, the intelligence, and the efficiency of the layout detection are improved, the dependence on the experience and the ability of related workers is avoided, the detection cost is reduced, and the yield and the performance of the subsequent semiconductor device preparation are improved.

[0085] In some embodiments, the semiconductor device structure rule and / or the size are adjusted according to the rule violation information, and the obtained rule violation information is reduced to meet a target requirement, for example, the rule violation information is substantially 0, and then the optical proximity correction can be performed on the layout again, the pattern distortion in the photolithography process is compensated by pre-adjusting the mask pattern (such as adding auxiliary structures or changing the edge position), and the yield and the performance of the prepared semiconductor device are further improved.

[0086] In some embodiments, a computer device is provided, including a memory and a processor, the memory stores a computer program, and the processor implements the steps of any one of the layout detection methods in the embodiments of the present disclosure when executing the computer program.

[0087] In some embodiments, a computer readable storage medium is provided, which stores a computer program, and the processor implements the steps of any one of the layout detection methods in the embodiments of the present disclosure when executing the computer program.

[0088] In some embodiments, a computer program product is provided, including a computer program, and the processor implements the steps of any one of the layout detection methods in the above-mentioned methods when executing the computer program.

[0089] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided by the present disclosure can include non-volatile, volatile memory or a combination thereof. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetic variable memory (MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM) or graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided by the present disclosure can include a relational database, a non-relational database or a combination thereof. The non-relational database can include a distributed database based on a block chain, etc., without limitation. The processor involved in the embodiments provided by the present disclosure can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device or a data processing logic device based on quantum computing, etc., without limitation.

[0090] Please note that the above-mentioned embodiments are only for illustrative purposes and do not mean a limitation of the present disclosure.

[0091] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between each embodiment can be referred to each other.

[0092] Each technical feature of the above-mentioned embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of each technical feature in the above-mentioned embodiments are not described, but as long as the combination of these technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0093] The above embodiments only express several implementation manners of the present disclosure, which are described in a more specific and detailed manner, but should not be understood as a limitation to the scope of the patent application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, which are all within the protection scope of the present disclosure.

Claims

1. A layout detection method, characterized in that: include: Obtain the truth table and design rule manual of the layout to be tested and semiconductor device structure; Obtaining device types in different regions according to film layer information in different regions of the layout to be inspected; the film layer information includes at least one of film layer name, film layer thickness, film layer size, doping concentration and type, material type, conductivity type, and layer sequence structure; Obtain device structure definition information of the device type in the truth table; Obtaining design rule information of the device type in the design rule manual; generating rule violation information according to the device structure definition information and the design rule information, wherein the rule violation information includes violation of semiconductor device structure rules and / or size rules; A target violation identification result of the layout to be inspected is generated according to the rule violation information, wherein the target violation identification result includes at least one of the violation film layer information, the violation device information, and the respective violation information.

2. The layout detection method according to claim 1, characterized in that: Obtaining device types in different regions includes: Obtaining typical film characteristics of a preset semiconductor device; Traversing different areas of the layout to be inspected, determining the device types of the different areas based on the typical film layer characteristics of the preset semiconductor device and the film layer information in the different areas; the typical film layer characteristics include necessary film layer information and / or prohibited film layer information.

3. The layout detection method according to claim 2, characterized in that: The typical film layer characteristics of the predetermined semiconductor device include at least one of the following characteristics: Typical film features of a metal oxide semiconductor field effect transistor include a gate, source and drain regions, and a gate oxide layer of a predetermined thickness; Typical film characteristics of diodes include single-layer or double-layer doping structure, no gate or insulating layer; The typical film layer features of a bipolar transistor include a base region and a three-layer stacked structure with conductivity types of NPN or PNP; Typical film layer features of integrated circuit interconnect structures include multiple through-hole structures and alternating metal and dielectric layers; Typical film features of an edge-gate bipolar transistor include a bipolar collector structure and a gate.

4. The layout detection method according to any one of claims 1 to 3, characterized in that: The design rule information of the device type includes defined film layer information preset by a user, where the defined film layer information includes unusable film layer information and / or film layer information that meets the semiconductor device design rules.

5. The layout detection method according to any one of claims 1 to 3, characterized in that: Generating a target violation identification result of the layout to be detected, including: According to the illegal film layer information and illegal device information, the illegal film layer and / or illegal device are highlighted in the layout to be inspected.

6. The layout detection method according to any one of claims 1 to 3, characterized in that: Updating the illegal film layer information and illegal device information into the illegal information database; The method further comprises: Obtain rule violation information in the violation information library that matches the device structure definition information.

7. The layout detection method according to any one of claims 1 to 3, characterized in that: Also includes: The semiconductor device structure rules and / or dimensions are adjusted according to the rule violation information until the obtained rule violation information is reduced to meet target requirements.

8. A layout detection device, characterized in that: include: Data acquisition module, used to obtain the truth table and design rule manual of the layout to be tested, semiconductor device structure; a device type identification module, configured to obtain device types in different regions based on film layer information in the layout to be detected; the film layer information includes at least one of film layer name, film layer thickness, film layer size, doping concentration and type, material type, conductivity type, and layer sequence structure; A definition information acquisition module, configured to acquire device structure definition information of the device type in the truth table; A rule information acquisition module, configured to acquire design rule information of the device type in the design rule manual; a violation information acquisition module, configured to generate rule violation information based on the device structure definition information and the design rule information, wherein the rule violation information includes violation of semiconductor device structure rules and / or size rules; The violation result generating module is used to generate a target violation identification result of the layout to be detected according to the rule violation information, wherein the target violation identification result includes at least one of the violation film layer information, the violation device information, and the respective violation information.

9. The layout detection device according to claim 8, characterized in that: The device type identification module includes: A typical film layer feature acquisition unit, used to acquire typical film layer features of a preset semiconductor device; A device type generation unit is used to traverse different areas in the layout to be tested and determine the device types of the different areas based on the typical film layer characteristics of the preset semiconductor device and the film layer information in the different areas; the typical film layer characteristics include necessary film layer information and / or prohibited film layer information.

10. The layout detection device according to claim 8 or 9, characterized in that: The rule information acquisition module also includes: The custom rule information acquisition unit is used to acquire the defined film layer information preset by the user, wherein the defined film layer information includes unusable film layer information and / or film layer information that meets the semiconductor device design rules.

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